From: LemonBoy <thatlemon@gmail.com>
To: qemu-devel@nongnu.org
Cc: Giuseppe Musacchio <thatlemon@gmail.com>,
qemu-ppc@nongnu.org, david@gibson.dropbear.id.au
Subject: [PATCH 1/2] ppc/translate: Implement lxvwsx opcode
Date: Mon, 9 Nov 2020 10:17:10 +0100 [thread overview]
Message-ID: <d7d533e18c2bc10d924ee3e09907ff2b41fddb3a.1604912739.git.thatlemon@gmail.com> (raw)
Implement the "Load VSX Vector Word & Splat Indexed" opcode, introduced
in Power ISA v3.0.
Buglink: https://bugs.launchpad.net/qemu/+bug/1793608
Signed-off-by: Giuseppe Musacchio <thatlemon@gmail.com>
---
target/ppc/translate/vsx-impl.c.inc | 30 +++++++++++++++++++++++++++++
target/ppc/translate/vsx-ops.c.inc | 1 +
2 files changed, 31 insertions(+)
diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc
index b518de46db..075f063e98 100644
--- a/target/ppc/translate/vsx-impl.c.inc
+++ b/target/ppc/translate/vsx-impl.c.inc
@@ -139,6 +139,36 @@ static void gen_lxvw4x(DisasContext *ctx)
tcg_temp_free_i64(xtl);
}
+static void gen_lxvwsx(DisasContext *ctx)
+{
+ TCGv EA;
+ TCGv_i32 data;
+
+ if (xT(ctx->opcode) < 32) {
+ if (unlikely(!ctx->vsx_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_VSXU);
+ return;
+ }
+ } else {
+ if (unlikely(!ctx->altivec_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_VPU);
+ return;
+ }
+ }
+
+ gen_set_access_type(ctx, ACCESS_INT);
+ EA = tcg_temp_new();
+
+ gen_addr_reg_index(ctx, EA);
+
+ data = tcg_temp_new_i32();
+ tcg_gen_qemu_ld_i32(data, EA, ctx->mem_idx, MO_TEUL);
+ tcg_gen_gvec_dup_i32(MO_UL, vsr_full_offset(xT(ctx->opcode)), 16, 16, data);
+
+ tcg_temp_free(EA);
+ tcg_temp_free_i32(data);
+}
+
static void gen_bswap16x8(TCGv_i64 outh, TCGv_i64 outl,
TCGv_i64 inh, TCGv_i64 inl)
{
diff --git a/target/ppc/translate/vsx-ops.c.inc b/target/ppc/translate/vsx-ops.c.inc
index 7fd3942b84..1d41beef26 100644
--- a/target/ppc/translate/vsx-ops.c.inc
+++ b/target/ppc/translate/vsx-ops.c.inc
@@ -5,6 +5,7 @@ GEN_HANDLER_E(lxsibzx, 0x1F, 0x0D, 0x18, 0, PPC_NONE, PPC2_ISA300),
GEN_HANDLER_E(lxsihzx, 0x1F, 0x0D, 0x19, 0, PPC_NONE, PPC2_ISA300),
GEN_HANDLER_E(lxsspx, 0x1F, 0x0C, 0x10, 0, PPC_NONE, PPC2_VSX207),
GEN_HANDLER_E(lxvd2x, 0x1F, 0x0C, 0x1A, 0, PPC_NONE, PPC2_VSX),
+GEN_HANDLER_E(lxvwsx, 0x1F, 0x0C, 0x0B, 0, PPC_NONE, PPC2_ISA300),
GEN_HANDLER_E(lxvdsx, 0x1F, 0x0C, 0x0A, 0, PPC_NONE, PPC2_VSX),
GEN_HANDLER_E(lxvw4x, 0x1F, 0x0C, 0x18, 0, PPC_NONE, PPC2_VSX),
GEN_HANDLER_E(lxvh8x, 0x1F, 0x0C, 0x19, 0, PPC_NONE, PPC2_ISA300),
--
2.27.0
next reply other threads:[~2020-11-09 9:26 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-09 9:17 LemonBoy [this message]
2020-11-09 9:17 ` [PATCH 2/2] ppc/translate: Rewrite gen_lxvdsx to use gvec primitives LemonBoy
2020-11-09 17:40 ` Richard Henderson
2020-11-09 17:39 ` [PATCH 1/2] ppc/translate: Implement lxvwsx opcode Richard Henderson
2020-11-10 9:14 ` LemonBoy
2020-11-11 6:22 ` David Gibson
2020-11-14 17:13 ` Richard Henderson
2020-11-23 6:13 ` David Gibson
2020-11-12 6:57 ` Greg Kurz
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