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Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.10.1 Subject: Re: [PATCH 2/3] hw/intc: Add NULL pointer check on LoongArch ipi device Content-Language: en-US To: Song Gao , qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, maobibo@loongson.cn, yangxiaojuan@loongson.cn References: <20230406100052.3355632-1-gaosong@loongson.cn> <20230406100052.3355632-2-gaosong@loongson.cn> <0de07b1e-1371-9bad-11e0-e57d8fb379fe@linaro.org> <255a9693-3660-35b4-8213-a609018bbb2c@loongson.cn> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= In-Reply-To: <255a9693-3660-35b4-8213-a609018bbb2c@loongson.cn> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=philmd@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-2.124, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 12/5/23 05:01, Song Gao wrote: > Hi,  Philippe > > 在 2023/5/12 上午3:03, Philippe Mathieu-Daudé 写道: >> On 6/4/23 12:00, Song Gao wrote: >>> When ipi mailbox is used, cpu index is decoded from iocsr register. >>> cpu maybe does not exist. This patch adss NULL pointer check on >>> ipi device. >> >> How can that happens from a guest vcpu context? >> > cpuid(cs->cpu_index)  is decoded from iocsr register. > >     cpuid = (val >> 16) & 0x3ff;   // ipi_sned [25:16] > > The value maybe invalid.  qemu only support 4 vcpu. What about something like this? -- >8 -- -static void ipi_send(uint64_t val) +static void ipi_send(uint32_t val) { - int cpuid, data; + uint32_t cpuid; + uint8_t vector; CPULoongArchState *env; CPUState *cs; LoongArchCPU *cpu; - cpuid = (val >> 16) & 0x3ff; + cpuid = extract32(val, 16, 10); + if (cpuid >= MAX_IPI_CORE_NUM) { + trace_loongarch_ipi_unsupported_cpuid("IOCSR_IPI_SEND", cpuid); + return; + } /* IPI status vector */ - data = 1 << (val & 0x1f); + vector = extract8(val, 0, 5); + cs = qemu_get_cpu(cpuid); cpu = LOONGARCH_CPU(cs); env = &cpu->env; address_space_stl(&env->address_space_iocsr, 0x1008, - data, MEMTXATTRS_UNSPECIFIED, NULL); + BIT(vector), MEMTXATTRS_UNSPECIFIED, NULL); } --- > you can find more about ipi_send registers at: > https://github.com/loongson/LoongArch-Documentation/releases/download/2023.04.20/Loongson-3A5000-usermanual-v1.03-EN.pdf > Table 63. Processor core inter-processor communication registers > >>> Signed-off-by: Song Gao >>> --- >>>   hw/intc/loongarch_ipi.c | 31 +++++++++++++++++++------------ >>>   1 file changed, 19 insertions(+), 12 deletions(-) >>> >>> diff --git a/hw/intc/loongarch_ipi.c b/hw/intc/loongarch_ipi.c >>> index 0563d83a35..39e899df46 100644 >>> --- a/hw/intc/loongarch_ipi.c >>> +++ b/hw/intc/loongarch_ipi.c >>> @@ -86,11 +86,12 @@ static void ipi_send(uint64_t val) >>>       /* IPI status vector */ >>>       data = 1 << (val & 0x1f); >>>       cs = qemu_get_cpu(cpuid); >>> -    cpu = LOONGARCH_CPU(cs); >>> -    env = &cpu->env; >>> -    address_space_stl(&env->address_space_iocsr, 0x1008, >>> -                      data, MEMTXATTRS_UNSPECIFIED, NULL); >>> - >>> +    if (cs) { >>> +        cpu = LOONGARCH_CPU(cs); >>> +        env = &cpu->env; >>> +        address_space_stl(&env->address_space_iocsr, 0x1008, >>> +                          data, MEMTXATTRS_UNSPECIFIED, NULL); >>> +    } >> >> Is that the hardware behavior? >> > Yes. >> Could logging the invalid cpuid request be useful? >> > Sure. > > Thanks. > Song Gao >