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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43999e5beebsm67795315e9.22.2025.02.20.13.46.12 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 20 Feb 2025 13:46:13 -0800 (PST) Message-ID: Date: Thu, 20 Feb 2025 22:46:12 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 002/162] tcg: Remove INDEX_op_ext{8,16,32}* To: Richard Henderson , qemu-devel@nongnu.org References: <20250216231012.2808572-1-richard.henderson@linaro.org> <20250216231012.2808572-3-richard.henderson@linaro.org> Content-Language: en-US From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: <20250216231012.2808572-3-richard.henderson@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=philmd@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 17/2/25 00:07, Richard Henderson wrote: > Use the fully general extract opcodes instead. > > Signed-off-by: Richard Henderson > --- > include/tcg/tcg-opc.h | 10 - > tcg/aarch64/tcg-target-has.h | 10 - > tcg/arm/tcg-target-has.h | 4 - > tcg/i386/tcg-target-has.h | 10 - > tcg/loongarch64/tcg-target-has.h | 10 - > tcg/mips/tcg-target-has.h | 13 - > tcg/ppc/tcg-target-has.h | 12 - > tcg/riscv/tcg-target-has.h | 10 - > tcg/s390x/tcg-target-has.h | 10 - > tcg/sparc64/tcg-target-has.h | 10 - > tcg/tcg-has.h | 6 - > tcg/tci/tcg-target-has.h | 10 - > tcg/optimize.c | 61 +---- > tcg/tcg-op.c | 430 ++++++++----------------------- > tcg/tcg.c | 46 ---- > tcg/tci.c | 36 --- > docs/devel/tcg-ops.rst | 14 - > tcg/aarch64/tcg-target.c.inc | 22 +- > tcg/arm/tcg-target.c.inc | 7 - > tcg/i386/tcg-target.c.inc | 24 +- > tcg/loongarch64/tcg-target.c.inc | 22 +- > tcg/mips/tcg-target.c.inc | 20 +- > tcg/ppc/tcg-target.c.inc | 17 +- > tcg/riscv/tcg-target.c.inc | 22 +- > tcg/s390x/tcg-target.c.inc | 22 +- > tcg/sparc64/tcg-target.c.inc | 14 +- > tcg/tci/tcg-target.c.inc | 102 +++----- > 27 files changed, 147 insertions(+), 827 deletions(-) > diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c > index fec6d678a2..48793ed439 100644 > --- a/tcg/tcg-op.c > +++ b/tcg/tcg-op.c > @@ -414,17 +414,19 @@ void tcg_gen_andi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) > case -1: > tcg_gen_mov_i32(ret, arg1); > return; > - case 0xff: > - /* Don't recurse with tcg_gen_ext8u_i32. */ > - if (TCG_TARGET_HAS_ext8u_i32) { > - tcg_gen_op2_i32(INDEX_op_ext8u_i32, ret, arg1); > - return; > - } > - break; > - case 0xffff: > - if (TCG_TARGET_HAS_ext16u_i32) { > - tcg_gen_op2_i32(INDEX_op_ext16u_i32, ret, arg1); > - return; > + default: > + /* > + * Canonicalize on extract, if valid. This aids x86 with its > + * 2 operand MOVZBL and 2 operand AND, selecting the TCGOpcode > + * which does not require matching operands. Other backends can > + * trivially expand the extract to AND during code generation. > + */ unsigned ofs = ctz32(arg2); int32_t val = arg2 >> ofs; if (!(val & (val + 1))) { unsigned len = cto32(val); if (TCG_TARGET_extract_valid(TCG_TYPE_I32, ofs, len)) { tcg_gen_extract_i32(ret, arg1, ofs, len); return; } } > + if (!(arg2 & (arg2 + 1))) { > + unsigned len = ctz32(~arg2); > + if (TCG_TARGET_extract_valid(TCG_TYPE_I32, 0, len)) { > + tcg_gen_extract_i32(ret, arg1, 0, len); > + return; > + } > } > break; > }