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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id 132-20020a62198a000000b00575caf8478dsm20232033pfz.41.2023.01.17.07.20.53 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 17 Jan 2023 07:20:54 -0800 (PST) Message-ID: Date: Tue, 17 Jan 2023 05:20:49 -1000 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.4.2 Subject: Re: [PATCH 0/2] target/arm: Look up ARMCPRegInfo at runtime To: Peter Maydell Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org References: <20230106194451.1213153-1-richard.henderson@linaro.org> <4db4ccba-1985-f1b2-6c5a-615b865ba749@linaro.org> Content-Language: en-US From: Richard Henderson In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x435.google.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.097, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 1/17/23 00:28, Peter Maydell wrote: > On Mon, 16 Jan 2023 at 20:16, Richard Henderson > wrote: >> >> Ping. > > What did you think of my suggestion in the other thread of hashing > the info we need to determine the cpreg set (ID regs, feature flags, > etc) and using that to look up whether we've already created a > cpreg hashtable for this config? If we did that, we could refcount > the cpreg hashtable and only free it when all CPUs are done with > it, which would mean we don't need this indirection. I thought it a decent idea, but not small. While we currently have a struct for some isar regs, we'd want a larger struct containing every bit of info that wants hashing. I think it would take 40-50 patches to get all of the properties etc moved out of ARMCPU and CPUARMState. Anyway, I didn't want to leave the user-only thread leak blocked in the meantime. r~