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[174.21.72.5]) by smtp.gmail.com with ESMTPSA id n4-20020a170902e54400b001e3f4f1a2aasm6273749plf.23.2024.04.14.10.20.52 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 14 Apr 2024 10:20:53 -0700 (PDT) Message-ID: Date: Sun, 14 Apr 2024 10:20:50 -0700 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] target/sparc: resolve ASI_USERTXT correctly To: M Bazz Cc: qemu-devel@nongnu.org, Artyom Tarasenko , Mark Cave-Ayland References: <20240411212936.945-1-bazz@bazz1.com> <48ec5cfe-e584-4e84-85d8-856bfd46345a@linaro.org> Content-Language: en-US From: Richard Henderson In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 4/13/24 18:54, M Bazz wrote: > This thought just came to me. `lda` is a privileged instruction. It has to > run in supervisor mode. So, I'm struggling to understand how the > kernel permission was wrong. Isn't that the right permission for this instruction? The "current" permission, as computed by > - case ASI_KERNELTXT: /* Supervisor code access */ > - oi = make_memop_idx(memop, cpu_mmu_index(env_cpu(env), true)); was correct for ASI_KERNELTXT, because as you say "lda" is a supervisor-only instruction prior to sparcv9. However, using the same value for ASI_USERTXT would be incorrect. For ASI_USERTXT and ASI_USERDATA (and the new names for sparcv9, ASI_AIU*, "as-if user"), we need permissions for the user context. That's what > + case ASI_USERTXT: /* User text access */ > + mem_idx = MMU_USER_IDX; this is for in my patch. This gets passed into the helper, > + case GET_ASI_CODE: > +#if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64) > + { > + MemOpIdx oi = make_memop_idx(da->memop, da->mem_idx); > + TCGv_i64 t64 = tcg_temp_new_i64(); > + > + gen_helper_ld_code(t64, tcg_env, addr, tcg_constant_i32(oi)); and then into the core memory access functions, > + ret = cpu_ldl_code_mmu(env, addr, oi, ra); Unfortunately, we do not have any good documentation for tcg softmmu or the intended role of the mmu_idx. Partly that's due to the final use of the mmu_idx is target-specific. For sparc32, there are 3 mmu_idx: > #define MMU_USER_IDX 0 > #define MMU_KERNEL_IDX 1 > #define MMU_PHYS_IDX 2 The interpretation of mmu_idx happens in target/sparc/mmu_helper.c, get_physical_address (note there are two versions, for sparc32 and sparc64). Ignoring MMU_PHYS_IDX, which is handled early, the difference between kernel and user is is_user = mmu_idx == MMU_USER_IDX; ... full->prot = perm_table[is_user][access_perms]; This controls the read/write/execute permissions for the page. Note that perm_table matches the Access Allowed table on page 248 of the Sparc V8 architecture manual. r~