From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48965) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ba5mV-0005Q9-0E for qemu-devel@nongnu.org; Wed, 17 Aug 2016 14:41:39 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ba5mR-0001YN-1b for qemu-devel@nongnu.org; Wed, 17 Aug 2016 14:41:38 -0400 Received: from mail-qk0-x244.google.com ([2607:f8b0:400d:c09::244]:36272) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ba5mQ-0001YG-TV for qemu-devel@nongnu.org; Wed, 17 Aug 2016 14:41:34 -0400 Received: by mail-qk0-x244.google.com with SMTP id v123so10975022qkh.3 for ; Wed, 17 Aug 2016 11:41:34 -0700 (PDT) Sender: Richard Henderson References: <87mvkeqph3.fsf@linaro.org> <20160815154626.GA8768@flamenco> <20160815154940.GA11939@flamenco> <17473d21-f53e-b46f-8882-4b54b6444bc4@twiddle.net> <20160817175800.GA5084@flamenco> From: Richard Henderson Message-ID: Date: Wed, 17 Aug 2016 11:41:28 -0700 MIME-Version: 1.0 In-Reply-To: <20160817175800.GA5084@flamenco> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH] aarch64: use TSX for ldrex/strex List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: "Emilio G. Cota" Cc: =?UTF-8?Q?Alex_Benn=c3=a9e?= , mttcg@greensocs.com, qemu-devel@nongnu.org, fred.konrad@greensocs.com, a.rigo@virtualopensystems.com, bobby.prani@gmail.com, nikunj@linux.vnet.ibm.com, mark.burton@greensocs.com, pbonzini@redhat.com, jan.kiszka@siemens.com, serge.fdrv@gmail.com, peter.maydell@linaro.org, claudio.fontana@huawei.com, "Dr. David Alan Gilbert" , Peter Crosthwaite On 08/17/2016 10:58 AM, Emilio G. Cota wrote: >> (2) that we should start a new TB upon encountering a load-exclusive, so >> that we maximize the chance of the store-exclusive being a part of the same >> TB and thus have *nothing* extra between the beginning and commit of the >> transaction. > > I don't know how to do this. If it's easy to do, please let me know how > (for aarch64 at least, since that's the target I'm using). It's a simple matter of peeking at the next instruction. One way is to partially decode the insn before advancing the PC. static void disas_a64_insn (CPUARMState *env, DisasContext *s, int num_insns) { uint32_t insn = arm_ldl_code(env, s->pc, s->sctlr_b); + + if (num_insns > 1 && (insn & xxx) == yyy) { + /* Start load-exclusive in a new TB. */ + s->is_jmp = DISAS_UPDATE; + return; + } s->insn = insn; s->pc += 4; ... Alternately, store num_insns into DisasContext, and do pc -= 4 in disas_ldst_excl. r~