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[200.207.104.238]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-720bc1e592asm7530342b3a.60.2024.11.04.06.36.31 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 04 Nov 2024 06:36:33 -0800 (PST) Message-ID: Date: Mon, 4 Nov 2024 11:36:30 -0300 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] target/arm: Enable FEAT_CMOW for -cpu max To: Richard Henderson , qemu-devel@nongnu.org, qemu-arm@nongnu.org, alex.bennee@linaro.org, peter.maydell@linaro.org References: <20241101013541.883785-1-gustavo.romero@linaro.org> <9994b8dd-0522-43ff-94ff-1a94aafd5ce2@linaro.org> Content-Language: en-US From: Gustavo Romero In-Reply-To: <9994b8dd-0522-43ff-94ff-1a94aafd5ce2@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=gustavo.romero@linaro.org; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi Richard, On 11/4/24 07:59, Richard Henderson wrote: > On 11/1/24 01:35, Gustavo Romero wrote: >> FEAT_CMOW introduces support for controlling cache maintenance >> instructions executed in EL0/1 and is mandatory from Armv8.8. >> >> On real hardware, the main use for this feature is to prevent processes >> from invalidating or flushing cache lines for addresses they only have >> read permission, which can impact the performance of other processes. >> >> QEMU implements all cache instructions as NOPs, and, according to rule >> [1], which states that generating any Permission fault when a cache >> instruction is implemented as a NOP is implementation-defined, no >> Permission fault is generated for any cache instruction when it lacks >> read and write permissions. >> >> QEMU does not model any cache topology, so the PoU and PoC are before >> any cache, and rules [2] apply. These rules states that generating any >> MMU fault for cache instructions in this topology is also >> implementation-defined. Therefore, for FEAT_CMOW, we do not generate any >> MMU faults either, instead, we only advertise it in the feature >> register. >> >> [1] Rule R_HGLYG of section D8.14.3, Arm ARM K.a. >> [2] Rules R_MZTNR and R_DNZYL of section D8.14.3, Arm ARM K.a. >> >> Signed-off-by: Gustavo Romero >> --- >>   docs/system/arm/emulation.rst | 1 + >>   target/arm/cpu-features.h     | 5 +++++ >>   target/arm/cpu.h              | 1 + >>   target/arm/tcg/cpu64.c        | 1 + >>   4 files changed, 8 insertions(+) >> >> diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst >> index 35f52a54b1..a2a388f091 100644 >> --- a/docs/system/arm/emulation.rst >> +++ b/docs/system/arm/emulation.rst >> @@ -26,6 +26,7 @@ the following architecture extensions: >>   - FEAT_BF16 (AArch64 BFloat16 instructions) >>   - FEAT_BTI (Branch Target Identification) >>   - FEAT_CCIDX (Extended cache index) >> +- FEAT_CMOW (Control for cache maintenance permission) >>   - FEAT_CRC32 (CRC32 instructions) >>   - FEAT_Crypto (Cryptographic Extension) >>   - FEAT_CSV2 (Cache speculation variant 2) >> diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h >> index 04ce281826..e806f138b8 100644 >> --- a/target/arm/cpu-features.h >> +++ b/target/arm/cpu-features.h >> @@ -802,6 +802,11 @@ static inline bool isar_feature_aa64_tidcp1(const ARMISARegisters *id) >>       return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, TIDCP1) != 0; >>   } >> +static inline bool isar_feature_aa64_cmow(const ARMISARegisters *id) >> +{ >> +    return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, CMOW) != 0; >> +} > > This isn't used, so it may be omitted. > > Otherwise, > Reviewed-by: Richard Henderson Got it. I wasn’t entirely sure if I should add it for future convenience. k, I'll omit it if I come across a similar case. Thanks. Since I'm using it after Peter's comment for v2, I kept it, and added your R-b. Cheers, Gustavo