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[90.181.218.29]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5c46302d647sm2807875a12.32.2024.09.21.21.56.08 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 21 Sep 2024 21:56:09 -0700 (PDT) Message-ID: Date: Sun, 22 Sep 2024 06:56:06 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] target/ppc: Fix lxvx/stxvx facility check To: Ilya Leoshkevich , Claudio Fontana , Fabiano Rosas , qemu-devel@nongnu.org Cc: qemu-stable@nongnu.org, Nicholas Piggin , Daniel Henrique Barboza References: <20240911141651.6914-1-farosas@suse.de> <9e6212ca-5c2f-459c-a59d-11fbdb796c07@suse.de> Content-Language: en-US From: Richard Henderson In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::532; envelope-from=richard.henderson@linaro.org; helo=mail-ed1-x532.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 9/20/24 11:24, Ilya Leoshkevich wrote: > On Thu, 2024-09-19 at 13:36 +0200, Claudio Fontana wrote: >> ping, adding Richard. >> >> We will need to include this downstream because of the breakage its >> lack causes. >> It is already reviewed by me, but some TCG maintainer indicating it >> will be included in some queue would help, >> >> Thanks, >> >> Claudio >> >> On 9/18/24 17:11, Claudio Fontana wrote: >>> Adding Ilya FYI. >>> >>> Ciao, >>> >>> Claudio >>> >>> On 9/11/24 18:19, Claudio Fontana wrote: >>>> On 9/11/24 16:16, Fabiano Rosas wrote: >>>>> The XT check for the lxvx/stxvx instructions is currently >>>>> inverted. This was introduced during the move to decodetree. >>>>> >>>>> From the ISA: >>>>>   Chapter 7. Vector-Scalar Extension Facility >>>>>   Load VSX Vector Indexed X-form >>>>> >>>>>   lxvx XT,RA,RB >>>>>   if TX=0 & MSR.VSX=0 then VSX_Unavailable() >>>>>   if TX=1 & MSR.VEC=0 then Vector_Unavailable() >>>>>   ... >>>>>   Let XT be the value 32×TX + T. >>>>> >>>>> The code currently does the opposite: >>>>> >>>>>     if (paired || a->rt >= 32) { >>>>>         REQUIRE_VSX(ctx); >>>>>     } else { >>>>>         REQUIRE_VECTOR(ctx); >>>>>     } >>>>> >>>>> This was already fixed for lxv/stxv at commit "2cc0e449d1 >>>>> (target/ppc: >>>>> Fix lxv/stxv MSR facility check)", but the indexed forms were >>>>> missed. >>>>> >>>>> Cc: qemu-stable@nongnu.org >>>>> Fixes: 70426b5bb7 ("target/ppc: moved stxvx and lxvx from >>>>> legacy to decodtree") >>>>> Signed-off-by: Fabiano Rosas >>>>> --- >>>>>  target/ppc/translate/vsx-impl.c.inc | 2 +- >>>>>  1 file changed, 1 insertion(+), 1 deletion(-) >>>>> >>>>> diff --git a/target/ppc/translate/vsx-impl.c.inc >>>>> b/target/ppc/translate/vsx-impl.c.inc >>>>> index 40a87ddc4a..a869f30e86 100644 >>>>> --- a/target/ppc/translate/vsx-impl.c.inc >>>>> +++ b/target/ppc/translate/vsx-impl.c.inc >>>>> @@ -2244,7 +2244,7 @@ static bool do_lstxv_PLS_D(DisasContext >>>>> *ctx, arg_PLS_D *a, >>>>> >>>>>  static bool do_lstxv_X(DisasContext *ctx, arg_X *a, bool >>>>> store, bool paired) >>>>>  { >>>>> -    if (paired || a->rt >= 32) { >>>>> +    if (paired || a->rt < 32) { >>>>>          REQUIRE_VSX(ctx); >>>>>      } else { >>>>>          REQUIRE_VECTOR(ctx); >>>> >>>> Reviewed-by: Claudio Fontana > > FWIW > > Acked-by: Ilya Leoshkevich > > But I'm not a maintainer, I guess Richard will need to pick it up. Queued, thanks. r~