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[88.21.205.47]) by smtp.gmail.com with ESMTPSA id 25sm4358911wmi.32.2020.02.25.06.09.23 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 25 Feb 2020 06:09:23 -0800 (PST) Subject: Re: [RFC PATCH v2 2/2] hw/arm/integratorcp: Map a CFI parallel flash To: Peter Maydell , =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= References: <20200223233033.15371-1-f4bug@amsat.org> <20200223233033.15371-3-f4bug@amsat.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: Date: Tue, 25 Feb 2020 15:09:23 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.4.1 MIME-Version: 1.0 In-Reply-To: Content-Language: en-US X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.120 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm , QEMU Developers Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 2/25/20 1:47 PM, Peter Maydell wrote: > On Sun, 23 Feb 2020 at 23:30, Philippe Mathieu-Daud=C3=A9 wrote: >> >> The Linux kernel displays errors why trying to detect the flash: >> >> Linux version 4.16.0 (linus@genomnajs) (gcc version 7.2.1 20171011 (L= inaro GCC 7.2-2017.11)) #142 PREEMPT Wed May 9 13:24:55 CEST 2018 >> CPU: ARM926EJ-S [41069265] revision 5 (ARMv5TEJ), cr=3D00093177 >> CPU: VIVT data cache, VIVT instruction cache >> OF: fdt: Machine model: ARM Integrator/CP >> ... >> of-flash 24000000.flash: Integrator/CP flash protection >> of-flash 24000000.flash: do_map_probe() failed for type cfi_probe >> of-flash 24000000.flash: do_map_probe() failed >> >> Since we have a CFI pflash model available, wire it. >> The kernel properly detects it: >> >> of-flash 24000000.flash: Integrator/CP flash protection >> 24000000.flash: Found 1 x32 devices at 0x0 in 32-bit bank. Manufactur= er ID 0x000000 Chip ID 0x000000 >> Intel/Sharp Extended Query Table at 0x0031 >> Using buffer write method >> >> Signed-off-by: Philippe Mathieu-Daud=C3=A9 >> --- >> v2: Kconfig change was not committed >> >> RFC because I have no idea of the flash model, its ID code, and which >> default CFI family (1 or 2). >=20 > ARM DUI 0102G ("ARM Firmware Suite Reference Guide") helpfully has > a few details: >=20 > Device Size Organization Flash part > Integrator/AP Boot flash 512KB 1x512K block Atmel AT49= LV040 > Integrator/AP Application flash 32MB 256x128K blocks Intel 28F3= 20S3 > Integrator/CP Boot/Application flash 16MB 64x256K blocks Intel 28F6= 40J3A >=20 > (of which we only model the CP.) With luck that's enough to > nail down the relevant device properties. "Intel 28F640J3A" is everything we need, thanks! >=20 >> @@ -646,6 +649,14 @@ static void integratorcp_init(MachineState *machine= ) >> qdev_get_gpio_in_named(icp, ICP_GPIO_MMC_CAR= DIN, 0)); >> sysbus_create_varargs("pl041", 0x1d000000, pic[25], NULL); >> >> + dinfo =3D drive_get(IF_PFLASH, 0, 0); >> + if (!pflash_cfi01_register(0x24000000, "pflash", 16 * MiB, >> + dinfo ? blk_by_legacy_dinfo(dinfo) : NUL= L, >> + 64 * KiB, 4, 0, 0, 0, 0, 0)) { >> + error_report("Error registering flash memory"); >> + exit(1); >> + } >=20 > Passing a 'width' argument of 0 means "weird legacy backcompat > device that's a bad emulation of a pair of 16-bit devices"; > we should avoid that for new code, and instead set > the width and device-width properties to whatever the > hardware has. (This in turn means you can't use the old > pflash_cfi01_register() function.) OK I'll try to document that. > Should we be using blk_by_legacy_dinfo() in new code? > I'm not sure if there's a better way to do this if we don't > need to maintain back-compat with old commandline specifications > of the flash contents. >=20 > thanks > -- PMM >=20