From: "Philippe Mathieu-Daudé" <philmd@redhat.com>
To: Peter Maydell <peter.maydell@linaro.org>, Marc Zyngier <maz@kernel.org>
Cc: Will Deacon <will@kernel.org>,
Richard Henderson <richard.henderson@linaro.org>,
QEMU Developers <qemu-devel@nongnu.org>,
kvmarm@lists.cs.columbia.edu, Quentin Perret <qperret@google.com>
Subject: Re: [PATCH] target/arm: Fix ISR_EL1 tracking when executing at EL2
Date: Fri, 22 Nov 2019 16:34:38 +0100 [thread overview]
Message-ID: <d91a9721-1a76-7434-cfc0-493ed4d0d7e2@redhat.com> (raw)
In-Reply-To: <CAFEAcA-aRwc9bogn-QbT-q5FzkqieYmQOZMr6H=kK5ixMGANMg@mail.gmail.com>
On 11/22/19 3:16 PM, Peter Maydell wrote:
> On Fri, 22 Nov 2019 at 13:59, Marc Zyngier <maz@kernel.org> wrote:
>>
>> The ARMv8 ARM states when executing at EL2, EL3 or Secure EL1,
>> ISR_EL1 shows the pending status of the physical IRQ, FIQ, or
>> SError interrupts.
>>
>> Unfortunately, QEMU's implementation only considers the HCR_EL2
>> bits, and ignores the current exception level. This means a hypervisor
>> trying to look at its own interrupt state actually sees the guest
>> state, which is unexpected and breaks KVM as of Linux 5.3.
>>
>> Instead, check for the running EL and return the physical bits
>> if not running in a virtualized context.
>>
>> Fixes: 636540e9c40b
>> Reported-by: Quentin Perret <qperret@google.com>
>> Signed-off-by: Marc Zyngier <maz@kernel.org>
>
> Congratulations on your first QEMU patch :-)
:))
next prev parent reply other threads:[~2019-11-22 15:35 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-11-22 13:58 [PATCH] target/arm: Fix ISR_EL1 tracking when executing at EL2 Marc Zyngier
2019-11-22 14:16 ` Peter Maydell
2019-11-22 15:34 ` Philippe Mathieu-Daudé [this message]
2019-11-22 16:17 ` Richard Henderson
2019-11-22 14:24 ` Edgar E. Iglesias
2019-11-22 15:38 ` Quentin Perret
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