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[88.21.102.131]) by smtp.gmail.com with ESMTPSA id u18sm7934629wrp.14.2019.11.22.07.34.38 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 22 Nov 2019 07:34:39 -0800 (PST) Subject: Re: [PATCH] target/arm: Fix ISR_EL1 tracking when executing at EL2 To: Peter Maydell , Marc Zyngier References: <20191122135833.28953-1-maz@kernel.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: Date: Fri, 22 Nov 2019 16:34:38 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.1.1 MIME-Version: 1.0 In-Reply-To: Content-Language: en-US X-MC-Unique: K4VAiBpCP8mlDuDkgBmIUA-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.81 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Will Deacon , Richard Henderson , QEMU Developers , kvmarm@lists.cs.columbia.edu, Quentin Perret Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 11/22/19 3:16 PM, Peter Maydell wrote: > On Fri, 22 Nov 2019 at 13:59, Marc Zyngier wrote: >> >> The ARMv8 ARM states when executing at EL2, EL3 or Secure EL1, >> ISR_EL1 shows the pending status of the physical IRQ, FIQ, or >> SError interrupts. >> >> Unfortunately, QEMU's implementation only considers the HCR_EL2 >> bits, and ignores the current exception level. This means a hypervisor >> trying to look at its own interrupt state actually sees the guest >> state, which is unexpected and breaks KVM as of Linux 5.3. >> >> Instead, check for the running EL and return the physical bits >> if not running in a virtualized context. >> >> Fixes: 636540e9c40b >> Reported-by: Quentin Perret >> Signed-off-by: Marc Zyngier >=20 > Congratulations on your first QEMU patch :-) :))