From: Julia Suvorova <jusual@mail.ru>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: "QEMU Developers" <qemu-devel@nongnu.org>,
"Stefan Hajnoczi" <stefanha@redhat.com>,
"Joel Stanley" <joel@jms.id.au>,
"Jim Mussared" <jim@groklearning.com>,
"Steffen Görtz" <mail@steffen-goertz.de>
Subject: Re: [Qemu-devel] [PATCH 1/2] nvic: Handle ARMv6-M SCS reserved registers
Date: Thu, 5 Jul 2018 14:25:47 +0300 [thread overview]
Message-ID: <d9228ff1-bdfa-506c-e32f-d0fbb69578be@mail.ru> (raw)
In-Reply-To: <CAFEAcA_ojVz=2Kbivr8b-VQQRCJUwnOf4w+pLAb4AoukMd8c_g@mail.gmail.com>
On 05.07.2018 13:54, Peter Maydell wrote:
> On 4 July 2018 at 20:58, Julia Suvorova <jusual@mail.ru> wrote:
>> Handle SCS reserved registers listed in ARMv6-M ARM D3.6.1.
>> All reserved registers are RAZ/WI.
>>
>> Signed-off-by: Julia Suvorova <jusual@mail.ru>
>> ---
>> hw/intc/armv7m_nvic.c | 69 +++++++++++++++++++++++++++++++++++--------
>> 1 file changed, 57 insertions(+), 12 deletions(-)
>
> Hi; this patch is generally good, but I have a couple of comments
> below, and in most (but not all) of these cases we should be
> checking the ARM_FEATURE_M_MAIN bit rather than ARM_FEATURE_V7 --
> I've annotated which should be which.
Thank you for the review. I did not dare to set the ARM_FEATURE_M_MAIN,
because I was not completely sure about the v8M behavior in certain cases.
I'll update the code taking into account all the comments, and send v2.
Best regards, Julia Suvorova.
next prev parent reply other threads:[~2018-07-05 11:25 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-07-04 19:58 [Qemu-devel] [PATCH 0/2] nvic: Handle ARMv6-M SCS reserved registers Julia Suvorova
2018-07-04 19:58 ` [Qemu-devel] [PATCH 1/2] " Julia Suvorova
2018-07-05 10:54 ` Peter Maydell
2018-07-05 11:25 ` Julia Suvorova [this message]
2018-07-05 12:06 ` Peter Maydell
2018-07-04 19:58 ` [Qemu-devel] [RFC 2/2] tests: Add ARMv6-M reserved register test Julia Suvorova
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