Re: [PATCH v1 14/15] tcg/riscv: Implement vector roti/v/x shi ops

[Richard Henderson <richard.henderson@linaro.org>]

On 8/13/24 21:34, LIU Zhiwei wrote:
> +    case INDEX_op_shli_vec:
> +        if (a2 > 31) {
> +            t2 = tcg_temp_new_i32();
> +            tcg_gen_movi_i32(t2, (int32_t)a2);
> +            tcg_gen_shls_vec(vece, v0, v1, t2);

Drop the movi, just pass tcg_constant_i32(a2) as the second source.

> +    case INDEX_op_rotls_vec:
> +        t1 = tcg_temp_new_vec(type);
> +        t2 = tcg_temp_new_i32();
> +        tcg_gen_sub_i32(t2, tcg_constant_i32(8 << vece),
> +                        temp_tcgv_i32(arg_temp(a2)));
> +        tcg_gen_shrs_vec(vece, v0, v1, t2);

Only the low lg2(SEW) bits are used; you can just tcg_gen_neg_i32.

> +    case INDEX_op_rotlv_vec:
> +        v2 = temp_tcgv_vec(arg_temp(a2));
> +        t1 = tcg_temp_new_vec(type);
> +        c1 = tcg_constant_vec(type, vece, 8 << vece);
> +        tcg_gen_sub_vec(vece, t1, c1, v2);

Likewise tcg_gen_neg_vec.

> +    case INDEX_op_rotrv_vec:
> +        v2 = temp_tcgv_vec(arg_temp(a2));
> +        t1 = tcg_temp_new_vec(type);
> +        c1 = tcg_constant_vec(type, vece, 8 << vece);
> +        tcg_gen_sub_vec(vece, t1, c1, v2);

Likewise.


r~