Re: [PATCH 1/1] hw/arm/sbsa-ref: use XHCI to replace EHCI

[Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>]

W dniu 1.06.2023 o 17:01, Peter Maydell pisze:
> On Wed, 31 May 2023 at 17:37, Leif Lindholm <quic_llindhol@quicinc.com> wrote:

>> Ah, thanks! That explains why we did the thing that made no sense :)
>>
>> To skip the migration hazard, my prefernece is we just leave the EHCI
>> device in for now, and add a separate XHCI on PCIe. We can drop the
>> EHCI device at some point in the future.
> 
> Why PCIe for the XHCI and not sysbus? At the time the board
> was originally added the argument was in favour of using
> a sysbus USB controller (you can see Ard making that point
> in the linked archive thread).

So something like below? I only tested does system boot into Debian.
To make it work also changes to EDK2 would be needed to list XHCI
controller in DSDT.

"info qtree" in QEMU monitor lists controller with usb devices
attached (added them by cli arguments).

 From 8f5af99a670be226a1dfc5b06cbdd3eff4841d27 Mon Sep 17 00:00:00 2001
From: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Date: Thu, 1 Jun 2023 17:27:24 +0200
Subject: [PATCH] WIP: arm/sbsa-ref: add XHCI on sysbus

EHCI controller is not working as it requires 32-bit memory.
XHCI one should work fine.
---
  hw/arm/sbsa-ref.c | 13 +++++++++++++
  1 file changed, 13 insertions(+)

diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
index de21200ff9..0bc87abbf4 100644
--- a/hw/arm/sbsa-ref.c
+++ b/hw/arm/sbsa-ref.c
@@ -83,6 +83,7 @@ enum {
      SBSA_SECURE_MEM,
      SBSA_AHCI,
      SBSA_EHCI,
+    SBSA_XHCI,
  };
  
  struct SBSAMachineState {
@@ -120,6 +121,7 @@ static const MemMapEntry sbsa_ref_memmap[] = {
      /* Space here reserved for more SMMUs */
      [SBSA_AHCI] =               { 0x60100000, 0x00010000 },
      [SBSA_EHCI] =               { 0x60110000, 0x00010000 },
+    [SBSA_XHCI] =               { 0x60120000, 0x00010000 },
      /* Space here reserved for other devices */
      [SBSA_PCIE_PIO] =           { 0x7fff0000, 0x00010000 },
      /* 32-bit address PCIE MMIO space */
@@ -142,6 +144,7 @@ static const int sbsa_ref_irqmap[] = {
      [SBSA_EHCI] = 11,
      [SBSA_SMMU] = 12, /* ... to 15 */
      [SBSA_GWDT_WS0] = 16,
+    [SBSA_XHCI] = 17,
  };
  
  static const char * const valid_cpus[] = {
@@ -575,6 +578,15 @@ static void create_ahci(const SBSAMachineState *sms)
      }
  }
  
+static void create_xhci(const SBSAMachineState *sms)
+{
+    hwaddr base = sbsa_ref_memmap[SBSA_XHCI].base;
+    int irq = sbsa_ref_irqmap[SBSA_XHCI];
+
+    sysbus_create_simple("sysbus-xhci", base,
+                         qdev_get_gpio_in(sms->gic, irq));
+}
+
  static void create_ehci(const SBSAMachineState *sms)
  {
      hwaddr base = sbsa_ref_memmap[SBSA_EHCI].base;
@@ -804,6 +816,7 @@ static void sbsa_ref_init(MachineState *machine)
      create_ahci(sms);
  
      create_ehci(sms);
+    create_xhci(sms);
  
      create_pcie(sms);
  
-- 
2.40.1