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([2a01:e0a:59e:9d80:527b:9dff:feef:3874]) by smtp.gmail.com with ESMTPSA id af79cd13be357-7a160b92ba7sm414925685a.27.2024.07.17.08.28.05 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 17 Jul 2024 08:28:07 -0700 (PDT) Message-ID: Date: Wed, 17 Jul 2024 17:28:03 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 09/18] hw/arm/smmu-common: Rework TLB lookup for nesting Content-Language: en-US To: Mostafa Saleh , qemu-arm@nongnu.org, peter.maydell@linaro.org, qemu-devel@nongnu.org Cc: jean-philippe@linaro.org, alex.bennee@linaro.org, maz@kernel.org, nicolinc@nvidia.com, julien@xen.org, richard.henderson@linaro.org, marcin.juszkiewicz@linaro.org References: <20240715084519.1189624-1-smostafa@google.com> <20240715084519.1189624-10-smostafa@google.com> From: Eric Auger In-Reply-To: <20240715084519.1189624-10-smostafa@google.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=170.10.129.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: eric.auger@redhat.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 7/15/24 10:45, Mostafa Saleh wrote: > In the next patch, combine_tlb() will be added which combines 2 TLB > entries into one for nested translations, which chooses the granule > and level from the smallest entry. > > This means that with nested translation, an entry can be cached with > the granule of stage-2 and not stage-1. > > However, currently, the lookup for an IOVA is done with input stage > granule, which is stage-1 for nested configuration, which will not > work with the above logic. > This patch reworks lookup in that case, so it falls back to stage-2 > granule if no entry is found using stage-1 granule. > > Also, drop aligning the iova to avoid over-aligning in case the iova > is cached with a smaller granule, the TLB lookup will align the iova > anyway for each granule and level, and the page table walker doesn't > consider the page offset bits. > > Signed-off-by: Mostafa Saleh Reviewed-by: Eric Auger Eric > --- > hw/arm/smmu-common.c | 64 +++++++++++++++++++++++++++++--------------- > 1 file changed, 43 insertions(+), 21 deletions(-) > > diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c > index 21982621c0..f224e9c1e0 100644 > --- a/hw/arm/smmu-common.c > +++ b/hw/arm/smmu-common.c > @@ -66,8 +66,10 @@ SMMUIOTLBKey smmu_get_iotlb_key(int asid, int vmid, uint64_t iova, > return key; > } > > -SMMUTLBEntry *smmu_iotlb_lookup(SMMUState *bs, SMMUTransCfg *cfg, > - SMMUTransTableInfo *tt, hwaddr iova) > +static SMMUTLBEntry *smmu_iotlb_lookup_all_levels(SMMUState *bs, > + SMMUTransCfg *cfg, > + SMMUTransTableInfo *tt, > + hwaddr iova) > { > uint8_t tg = (tt->granule_sz - 10) / 2; > uint8_t inputsize = 64 - tt->tsz; > @@ -88,6 +90,36 @@ SMMUTLBEntry *smmu_iotlb_lookup(SMMUState *bs, SMMUTransCfg *cfg, > } > level++; > } > + return entry; > +} > + > +/** > + * smmu_iotlb_lookup - Look up for a TLB entry. > + * @bs: SMMU state which includes the TLB instance > + * @cfg: Configuration of the translation > + * @tt: Translation table info (granule and tsz) > + * @iova: IOVA address to lookup > + * > + * returns a valid entry on success, otherwise NULL. > + * In case of nested translation, tt can be updated to include > + * the granule of the found entry as it might different from > + * the IOVA granule. > + */ > +SMMUTLBEntry *smmu_iotlb_lookup(SMMUState *bs, SMMUTransCfg *cfg, > + SMMUTransTableInfo *tt, hwaddr iova) > +{ > + SMMUTLBEntry *entry = NULL; > + > + entry = smmu_iotlb_lookup_all_levels(bs, cfg, tt, iova); > + /* > + * For nested translation also try the s2 granule, as the TLB will insert > + * it if the size of s2 tlb entry was smaller. > + */ > + if (!entry && (cfg->stage == SMMU_NESTED) && > + (cfg->s2cfg.granule_sz != tt->granule_sz)) { > + tt->granule_sz = cfg->s2cfg.granule_sz; > + entry = smmu_iotlb_lookup_all_levels(bs, cfg, tt, iova); > + } > > if (entry) { > cfg->iotlb_hits++; > @@ -569,18 +601,21 @@ int smmu_ptw(SMMUTransCfg *cfg, dma_addr_t iova, IOMMUAccessFlags perm, > SMMUTLBEntry *smmu_translate(SMMUState *bs, SMMUTransCfg *cfg, dma_addr_t addr, > IOMMUAccessFlags flag, SMMUPTWEventInfo *info) > { > - uint64_t page_mask, aligned_addr; > SMMUTLBEntry *cached_entry = NULL; > SMMUTransTableInfo *tt; > int status; > > /* > - * Combined attributes used for TLB lookup, as only one stage is supported, > - * it will hold attributes based on the enabled stage. > + * Combined attributes used for TLB lookup, holds the attributes for > + * the input stage. > */ > SMMUTransTableInfo tt_combined; > > - if (cfg->stage == SMMU_STAGE_1) { > + if (cfg->stage == SMMU_STAGE_2) { > + /* Stage2. */ > + tt_combined.granule_sz = cfg->s2cfg.granule_sz; > + tt_combined.tsz = cfg->s2cfg.tsz; > + } else { > /* Select stage1 translation table. */ > tt = select_tt(cfg, addr); > if (!tt) { > @@ -590,22 +625,9 @@ SMMUTLBEntry *smmu_translate(SMMUState *bs, SMMUTransCfg *cfg, dma_addr_t addr, > } > tt_combined.granule_sz = tt->granule_sz; > tt_combined.tsz = tt->tsz; > - > - } else { > - /* Stage2. */ > - tt_combined.granule_sz = cfg->s2cfg.granule_sz; > - tt_combined.tsz = cfg->s2cfg.tsz; > } > > - /* > - * TLB lookup looks for granule and input size for a translation stage, > - * as only one stage is supported right now, choose the right values > - * from the configuration. > - */ > - page_mask = (1ULL << tt_combined.granule_sz) - 1; > - aligned_addr = addr & ~page_mask; > - > - cached_entry = smmu_iotlb_lookup(bs, cfg, &tt_combined, aligned_addr); > + cached_entry = smmu_iotlb_lookup(bs, cfg, &tt_combined, addr); > if (cached_entry) { > if ((flag & IOMMU_WO) && !(cached_entry->entry.perm & IOMMU_WO)) { > info->type = SMMU_PTW_ERR_PERMISSION; > @@ -616,7 +638,7 @@ SMMUTLBEntry *smmu_translate(SMMUState *bs, SMMUTransCfg *cfg, dma_addr_t addr, > } > > cached_entry = g_new0(SMMUTLBEntry, 1); > - status = smmu_ptw(cfg, aligned_addr, flag, cached_entry, info); > + status = smmu_ptw(cfg, addr, flag, cached_entry, info); > if (status) { > g_free(cached_entry); > return NULL;