* [PATCH 1/4] ppc/pnv: quad xscom callbacks are P9 specific
2023-06-30 3:55 [PATCH 0/4] ppc/pnv: Extend "quad" model for p10 Joel Stanley
@ 2023-06-30 3:55 ` Joel Stanley
2023-06-30 5:23 ` Cédric Le Goater
2023-06-30 3:55 ` [PATCH 2/4] ppc/pnv: Subclass quad xscom callbacks Joel Stanley
` (3 subsequent siblings)
4 siblings, 1 reply; 15+ messages in thread
From: Joel Stanley @ 2023-06-30 3:55 UTC (permalink / raw)
To: Cédric Le Goater, Nicholas Piggin, Frédéric Barrat
Cc: qemu-devel, qemu-ppc
Rename the to include P9 in the name in preparation for adding P10
versions.
Signed-off-by: Joel Stanley <joel@jms.id.au>
---
hw/ppc/pnv_core.c | 17 +++++++++--------
1 file changed, 9 insertions(+), 8 deletions(-)
diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c
index 0bc3ad41c81c..0b1c3cccfebc 100644
--- a/hw/ppc/pnv_core.c
+++ b/hw/ppc/pnv_core.c
@@ -360,8 +360,8 @@ DEFINE_TYPES(pnv_core_infos)
#define P9X_EX_NCU_SPEC_BAR 0x11010
-static uint64_t pnv_quad_xscom_read(void *opaque, hwaddr addr,
- unsigned int width)
+static uint64_t pnv_quad_power9_xscom_read(void *opaque, hwaddr addr,
+ unsigned int width)
{
uint32_t offset = addr >> 3;
uint64_t val = -1;
@@ -379,8 +379,8 @@ static uint64_t pnv_quad_xscom_read(void *opaque, hwaddr addr,
return val;
}
-static void pnv_quad_xscom_write(void *opaque, hwaddr addr, uint64_t val,
- unsigned int width)
+static void pnv_quad_power9_xscom_write(void *opaque, hwaddr addr, uint64_t val,
+ unsigned int width)
{
uint32_t offset = addr >> 3;
@@ -394,9 +394,9 @@ static void pnv_quad_xscom_write(void *opaque, hwaddr addr, uint64_t val,
}
}
-static const MemoryRegionOps pnv_quad_xscom_ops = {
- .read = pnv_quad_xscom_read,
- .write = pnv_quad_xscom_write,
+static const MemoryRegionOps pnv_quad_power9_xscom_ops = {
+ .read = pnv_quad_power9_xscom_read,
+ .write = pnv_quad_power9_xscom_write,
.valid.min_access_size = 8,
.valid.max_access_size = 8,
.impl.min_access_size = 8,
@@ -410,7 +410,8 @@ static void pnv_quad_realize(DeviceState *dev, Error **errp)
char name[32];
snprintf(name, sizeof(name), "xscom-quad.%d", eq->quad_id);
- pnv_xscom_region_init(&eq->xscom_regs, OBJECT(dev), &pnv_quad_xscom_ops,
+ pnv_xscom_region_init(&eq->xscom_regs, OBJECT(dev),
+ &pnv_quad_power9_xscom_ops,
eq, name, PNV9_XSCOM_EQ_SIZE);
}
--
2.40.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [PATCH 1/4] ppc/pnv: quad xscom callbacks are P9 specific
2023-06-30 3:55 ` [PATCH 1/4] ppc/pnv: quad xscom callbacks are P9 specific Joel Stanley
@ 2023-06-30 5:23 ` Cédric Le Goater
0 siblings, 0 replies; 15+ messages in thread
From: Cédric Le Goater @ 2023-06-30 5:23 UTC (permalink / raw)
To: Joel Stanley, Nicholas Piggin, Frédéric Barrat
Cc: qemu-devel, qemu-ppc
On 6/30/23 05:55, Joel Stanley wrote:
> Rename the to include P9 in the name in preparation for adding P10
> versions.
>
> Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Thanks,
C.
> ---
> hw/ppc/pnv_core.c | 17 +++++++++--------
> 1 file changed, 9 insertions(+), 8 deletions(-)
>
> diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c
> index 0bc3ad41c81c..0b1c3cccfebc 100644
> --- a/hw/ppc/pnv_core.c
> +++ b/hw/ppc/pnv_core.c
> @@ -360,8 +360,8 @@ DEFINE_TYPES(pnv_core_infos)
>
> #define P9X_EX_NCU_SPEC_BAR 0x11010
>
> -static uint64_t pnv_quad_xscom_read(void *opaque, hwaddr addr,
> - unsigned int width)
> +static uint64_t pnv_quad_power9_xscom_read(void *opaque, hwaddr addr,
> + unsigned int width)
> {
> uint32_t offset = addr >> 3;
> uint64_t val = -1;
> @@ -379,8 +379,8 @@ static uint64_t pnv_quad_xscom_read(void *opaque, hwaddr addr,
> return val;
> }
>
> -static void pnv_quad_xscom_write(void *opaque, hwaddr addr, uint64_t val,
> - unsigned int width)
> +static void pnv_quad_power9_xscom_write(void *opaque, hwaddr addr, uint64_t val,
> + unsigned int width)
> {
> uint32_t offset = addr >> 3;
>
> @@ -394,9 +394,9 @@ static void pnv_quad_xscom_write(void *opaque, hwaddr addr, uint64_t val,
> }
> }
>
> -static const MemoryRegionOps pnv_quad_xscom_ops = {
> - .read = pnv_quad_xscom_read,
> - .write = pnv_quad_xscom_write,
> +static const MemoryRegionOps pnv_quad_power9_xscom_ops = {
> + .read = pnv_quad_power9_xscom_read,
> + .write = pnv_quad_power9_xscom_write,
> .valid.min_access_size = 8,
> .valid.max_access_size = 8,
> .impl.min_access_size = 8,
> @@ -410,7 +410,8 @@ static void pnv_quad_realize(DeviceState *dev, Error **errp)
> char name[32];
>
> snprintf(name, sizeof(name), "xscom-quad.%d", eq->quad_id);
> - pnv_xscom_region_init(&eq->xscom_regs, OBJECT(dev), &pnv_quad_xscom_ops,
> + pnv_xscom_region_init(&eq->xscom_regs, OBJECT(dev),
> + &pnv_quad_power9_xscom_ops,
> eq, name, PNV9_XSCOM_EQ_SIZE);
> }
>
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 2/4] ppc/pnv: Subclass quad xscom callbacks
2023-06-30 3:55 [PATCH 0/4] ppc/pnv: Extend "quad" model for p10 Joel Stanley
2023-06-30 3:55 ` [PATCH 1/4] ppc/pnv: quad xscom callbacks are P9 specific Joel Stanley
@ 2023-06-30 3:55 ` Joel Stanley
2023-06-30 5:24 ` Cédric Le Goater
2023-06-30 3:55 ` [PATCH 3/4] ppc/pnv: Add P10 quad ops Joel Stanley
` (2 subsequent siblings)
4 siblings, 1 reply; 15+ messages in thread
From: Joel Stanley @ 2023-06-30 3:55 UTC (permalink / raw)
To: Cédric Le Goater, Nicholas Piggin, Frédéric Barrat
Cc: qemu-devel, qemu-ppc
Make the existing pnv_quad_xscom_read/write be P9 specific, in
preparation for a different P10 callback.
Signed-off-by: Joel Stanley <joel@jms.id.au>
---
include/hw/ppc/pnv_core.h | 12 +++++++++++-
hw/ppc/pnv.c | 11 +++++++----
hw/ppc/pnv_core.c | 36 ++++++++++++++++++++++++------------
3 files changed, 42 insertions(+), 17 deletions(-)
diff --git a/include/hw/ppc/pnv_core.h b/include/hw/ppc/pnv_core.h
index 3d75706e95da..ab3f6d6c2843 100644
--- a/include/hw/ppc/pnv_core.h
+++ b/include/hw/ppc/pnv_core.h
@@ -60,8 +60,18 @@ static inline PnvCPUState *pnv_cpu_state(PowerPCCPU *cpu)
return (PnvCPUState *)cpu->machine_data;
}
+struct PnvQuadClass {
+ DeviceClass parent_class;
+
+ const MemoryRegionOps *xscom_ops;
+};
+
#define TYPE_PNV_QUAD "powernv-cpu-quad"
-OBJECT_DECLARE_SIMPLE_TYPE(PnvQuad, PNV_QUAD)
+
+#define PNV_QUAD_TYPE_SUFFIX "-" TYPE_PNV_QUAD
+#define PNV_QUAD_TYPE_NAME(cpu_model) cpu_model PNV_QUAD_TYPE_SUFFIX
+
+OBJECT_DECLARE_TYPE(PnvQuad, PnvQuadClass, PNV_QUAD)
struct PnvQuad {
DeviceState parent_obj;
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index fc083173f346..c77fdb6747a4 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -1429,14 +1429,15 @@ static void pnv_chip_power9_instance_init(Object *obj)
}
static void pnv_chip_quad_realize_one(PnvChip *chip, PnvQuad *eq,
- PnvCore *pnv_core)
+ PnvCore *pnv_core,
+ const char *type)
{
char eq_name[32];
int core_id = CPU_CORE(pnv_core)->core_id;
snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id);
object_initialize_child_with_props(OBJECT(chip), eq_name, eq,
- sizeof(*eq), TYPE_PNV_QUAD,
+ sizeof(*eq), type,
&error_fatal, NULL);
object_property_set_int(OBJECT(eq), "quad-id", core_id, &error_fatal);
@@ -1454,7 +1455,8 @@ static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp)
for (i = 0; i < chip9->nr_quads; i++) {
PnvQuad *eq = &chip9->quads[i];
- pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4]);
+ pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4],
+ PNV_QUAD_TYPE_NAME("power9"));
pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->quad_id),
&eq->xscom_regs);
@@ -1666,7 +1668,8 @@ static void pnv_chip_power10_quad_realize(Pnv10Chip *chip10, Error **errp)
for (i = 0; i < chip10->nr_quads; i++) {
PnvQuad *eq = &chip10->quads[i];
- pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4]);
+ pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4],
+ PNV_QUAD_TYPE_NAME("power9"));
pnv_xscom_add_subregion(chip, PNV10_XSCOM_EQ_BASE(eq->quad_id),
&eq->xscom_regs);
diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c
index 0b1c3cccfebc..b9a57463aec4 100644
--- a/hw/ppc/pnv_core.c
+++ b/hw/ppc/pnv_core.c
@@ -407,11 +407,12 @@ static const MemoryRegionOps pnv_quad_power9_xscom_ops = {
static void pnv_quad_realize(DeviceState *dev, Error **errp)
{
PnvQuad *eq = PNV_QUAD(dev);
+ PnvQuadClass *pqc = PNV_QUAD_GET_CLASS(eq);
char name[32];
snprintf(name, sizeof(name), "xscom-quad.%d", eq->quad_id);
pnv_xscom_region_init(&eq->xscom_regs, OBJECT(dev),
- &pnv_quad_power9_xscom_ops,
+ pqc->xscom_ops,
eq, name, PNV9_XSCOM_EQ_SIZE);
}
@@ -420,6 +421,13 @@ static Property pnv_quad_properties[] = {
DEFINE_PROP_END_OF_LIST(),
};
+static void pnv_quad_power9_class_init(ObjectClass *oc, void *data)
+{
+ PnvQuadClass *pqc = PNV_QUAD_CLASS(oc);
+
+ pqc->xscom_ops = &pnv_quad_power9_xscom_ops;
+}
+
static void pnv_quad_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
@@ -429,16 +437,20 @@ static void pnv_quad_class_init(ObjectClass *oc, void *data)
dc->user_creatable = false;
}
-static const TypeInfo pnv_quad_info = {
- .name = TYPE_PNV_QUAD,
- .parent = TYPE_DEVICE,
- .instance_size = sizeof(PnvQuad),
- .class_init = pnv_quad_class_init,
+static const TypeInfo pnv_quad_infos[] = {
+ {
+ .name = TYPE_PNV_QUAD,
+ .parent = TYPE_DEVICE,
+ .instance_size = sizeof(PnvQuad),
+ .class_size = sizeof(PnvQuadClass),
+ .class_init = pnv_quad_class_init,
+ .abstract = true,
+ },
+ {
+ .parent = TYPE_PNV_QUAD,
+ .name = PNV_QUAD_TYPE_NAME("power9"),
+ .class_init = pnv_quad_power9_class_init,
+ },
};
-static void pnv_core_register_types(void)
-{
- type_register_static(&pnv_quad_info);
-}
-
-type_init(pnv_core_register_types)
+DEFINE_TYPES(pnv_quad_infos);
--
2.40.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [PATCH 2/4] ppc/pnv: Subclass quad xscom callbacks
2023-06-30 3:55 ` [PATCH 2/4] ppc/pnv: Subclass quad xscom callbacks Joel Stanley
@ 2023-06-30 5:24 ` Cédric Le Goater
0 siblings, 0 replies; 15+ messages in thread
From: Cédric Le Goater @ 2023-06-30 5:24 UTC (permalink / raw)
To: Joel Stanley, Nicholas Piggin, Frédéric Barrat
Cc: qemu-devel, qemu-ppc
On 6/30/23 05:55, Joel Stanley wrote:
> Make the existing pnv_quad_xscom_read/write be P9 specific, in
> preparation for a different P10 callback.
>
> Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Thanks,
C.
> ---
> include/hw/ppc/pnv_core.h | 12 +++++++++++-
> hw/ppc/pnv.c | 11 +++++++----
> hw/ppc/pnv_core.c | 36 ++++++++++++++++++++++++------------
> 3 files changed, 42 insertions(+), 17 deletions(-)
>
> diff --git a/include/hw/ppc/pnv_core.h b/include/hw/ppc/pnv_core.h
> index 3d75706e95da..ab3f6d6c2843 100644
> --- a/include/hw/ppc/pnv_core.h
> +++ b/include/hw/ppc/pnv_core.h
> @@ -60,8 +60,18 @@ static inline PnvCPUState *pnv_cpu_state(PowerPCCPU *cpu)
> return (PnvCPUState *)cpu->machine_data;
> }
>
> +struct PnvQuadClass {
> + DeviceClass parent_class;
> +
> + const MemoryRegionOps *xscom_ops;
> +};
> +
> #define TYPE_PNV_QUAD "powernv-cpu-quad"
> -OBJECT_DECLARE_SIMPLE_TYPE(PnvQuad, PNV_QUAD)
> +
> +#define PNV_QUAD_TYPE_SUFFIX "-" TYPE_PNV_QUAD
> +#define PNV_QUAD_TYPE_NAME(cpu_model) cpu_model PNV_QUAD_TYPE_SUFFIX
> +
> +OBJECT_DECLARE_TYPE(PnvQuad, PnvQuadClass, PNV_QUAD)
>
> struct PnvQuad {
> DeviceState parent_obj;
> diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
> index fc083173f346..c77fdb6747a4 100644
> --- a/hw/ppc/pnv.c
> +++ b/hw/ppc/pnv.c
> @@ -1429,14 +1429,15 @@ static void pnv_chip_power9_instance_init(Object *obj)
> }
>
> static void pnv_chip_quad_realize_one(PnvChip *chip, PnvQuad *eq,
> - PnvCore *pnv_core)
> + PnvCore *pnv_core,
> + const char *type)
> {
> char eq_name[32];
> int core_id = CPU_CORE(pnv_core)->core_id;
>
> snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id);
> object_initialize_child_with_props(OBJECT(chip), eq_name, eq,
> - sizeof(*eq), TYPE_PNV_QUAD,
> + sizeof(*eq), type,
> &error_fatal, NULL);
>
> object_property_set_int(OBJECT(eq), "quad-id", core_id, &error_fatal);
> @@ -1454,7 +1455,8 @@ static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp)
> for (i = 0; i < chip9->nr_quads; i++) {
> PnvQuad *eq = &chip9->quads[i];
>
> - pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4]);
> + pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4],
> + PNV_QUAD_TYPE_NAME("power9"));
>
> pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->quad_id),
> &eq->xscom_regs);
> @@ -1666,7 +1668,8 @@ static void pnv_chip_power10_quad_realize(Pnv10Chip *chip10, Error **errp)
> for (i = 0; i < chip10->nr_quads; i++) {
> PnvQuad *eq = &chip10->quads[i];
>
> - pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4]);
> + pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4],
> + PNV_QUAD_TYPE_NAME("power9"));
>
> pnv_xscom_add_subregion(chip, PNV10_XSCOM_EQ_BASE(eq->quad_id),
> &eq->xscom_regs);
> diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c
> index 0b1c3cccfebc..b9a57463aec4 100644
> --- a/hw/ppc/pnv_core.c
> +++ b/hw/ppc/pnv_core.c
> @@ -407,11 +407,12 @@ static const MemoryRegionOps pnv_quad_power9_xscom_ops = {
> static void pnv_quad_realize(DeviceState *dev, Error **errp)
> {
> PnvQuad *eq = PNV_QUAD(dev);
> + PnvQuadClass *pqc = PNV_QUAD_GET_CLASS(eq);
> char name[32];
>
> snprintf(name, sizeof(name), "xscom-quad.%d", eq->quad_id);
> pnv_xscom_region_init(&eq->xscom_regs, OBJECT(dev),
> - &pnv_quad_power9_xscom_ops,
> + pqc->xscom_ops,
> eq, name, PNV9_XSCOM_EQ_SIZE);
> }
>
> @@ -420,6 +421,13 @@ static Property pnv_quad_properties[] = {
> DEFINE_PROP_END_OF_LIST(),
> };
>
> +static void pnv_quad_power9_class_init(ObjectClass *oc, void *data)
> +{
> + PnvQuadClass *pqc = PNV_QUAD_CLASS(oc);
> +
> + pqc->xscom_ops = &pnv_quad_power9_xscom_ops;
> +}
> +
> static void pnv_quad_class_init(ObjectClass *oc, void *data)
> {
> DeviceClass *dc = DEVICE_CLASS(oc);
> @@ -429,16 +437,20 @@ static void pnv_quad_class_init(ObjectClass *oc, void *data)
> dc->user_creatable = false;
> }
>
> -static const TypeInfo pnv_quad_info = {
> - .name = TYPE_PNV_QUAD,
> - .parent = TYPE_DEVICE,
> - .instance_size = sizeof(PnvQuad),
> - .class_init = pnv_quad_class_init,
> +static const TypeInfo pnv_quad_infos[] = {
> + {
> + .name = TYPE_PNV_QUAD,
> + .parent = TYPE_DEVICE,
> + .instance_size = sizeof(PnvQuad),
> + .class_size = sizeof(PnvQuadClass),
> + .class_init = pnv_quad_class_init,
> + .abstract = true,
> + },
> + {
> + .parent = TYPE_PNV_QUAD,
> + .name = PNV_QUAD_TYPE_NAME("power9"),
> + .class_init = pnv_quad_power9_class_init,
> + },
> };
>
> -static void pnv_core_register_types(void)
> -{
> - type_register_static(&pnv_quad_info);
> -}
> -
> -type_init(pnv_core_register_types)
> +DEFINE_TYPES(pnv_quad_infos);
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 3/4] ppc/pnv: Add P10 quad ops
2023-06-30 3:55 [PATCH 0/4] ppc/pnv: Extend "quad" model for p10 Joel Stanley
2023-06-30 3:55 ` [PATCH 1/4] ppc/pnv: quad xscom callbacks are P9 specific Joel Stanley
2023-06-30 3:55 ` [PATCH 2/4] ppc/pnv: Subclass quad xscom callbacks Joel Stanley
@ 2023-06-30 3:55 ` Joel Stanley
2023-06-30 5:24 ` Cédric Le Goater
2023-06-30 7:30 ` Frederic Barrat
2023-06-30 3:55 ` [PATCH 4/4] ppc/pnv: Return zero for core thread state xscom Joel Stanley
2023-07-01 10:10 ` [PATCH 0/4] ppc/pnv: Extend "quad" model for p10 Nicholas Piggin
4 siblings, 2 replies; 15+ messages in thread
From: Joel Stanley @ 2023-06-30 3:55 UTC (permalink / raw)
To: Cédric Le Goater, Nicholas Piggin, Frédéric Barrat
Cc: qemu-devel, qemu-ppc
Add a PnvQuad class for the P10 powernv machine. No xscoms are
implemented yet, but this allows them to be added.
Signed-off-by: Joel Stanley <joel@jms.id.au>
---
hw/ppc/pnv.c | 2 +-
hw/ppc/pnv_core.c | 53 +++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 54 insertions(+), 1 deletion(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index c77fdb6747a4..5f25fe985ab2 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -1669,7 +1669,7 @@ static void pnv_chip_power10_quad_realize(Pnv10Chip *chip10, Error **errp)
PnvQuad *eq = &chip10->quads[i];
pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4],
- PNV_QUAD_TYPE_NAME("power9"));
+ PNV_QUAD_TYPE_NAME("power10"));
pnv_xscom_add_subregion(chip, PNV10_XSCOM_EQ_BASE(eq->quad_id),
&eq->xscom_regs);
diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c
index b9a57463aec4..7fff2fd9e298 100644
--- a/hw/ppc/pnv_core.c
+++ b/hw/ppc/pnv_core.c
@@ -404,6 +404,47 @@ static const MemoryRegionOps pnv_quad_power9_xscom_ops = {
.endianness = DEVICE_BIG_ENDIAN,
};
+/*
+ * POWER10 Quads
+ */
+
+static uint64_t pnv_quad_power10_xscom_read(void *opaque, hwaddr addr,
+ unsigned int width)
+{
+ uint32_t offset = addr >> 3;
+ uint64_t val = -1;
+
+ switch (offset) {
+ default:
+ qemu_log_mask(LOG_UNIMP, "%s: writing @0x%08x\n", __func__,
+ offset);
+ }
+
+ return val;
+}
+
+static void pnv_quad_power10_xscom_write(void *opaque, hwaddr addr, uint64_t val,
+ unsigned int width)
+{
+ uint32_t offset = addr >> 3;
+
+ switch (offset) {
+ default:
+ qemu_log_mask(LOG_UNIMP, "%s: writing @0x%08x\n", __func__,
+ offset);
+ }
+}
+
+static const MemoryRegionOps pnv_quad_power10_xscom_ops = {
+ .read = pnv_quad_power10_xscom_read,
+ .write = pnv_quad_power10_xscom_write,
+ .valid.min_access_size = 8,
+ .valid.max_access_size = 8,
+ .impl.min_access_size = 8,
+ .impl.max_access_size = 8,
+ .endianness = DEVICE_BIG_ENDIAN,
+};
+
static void pnv_quad_realize(DeviceState *dev, Error **errp)
{
PnvQuad *eq = PNV_QUAD(dev);
@@ -428,6 +469,13 @@ static void pnv_quad_power9_class_init(ObjectClass *oc, void *data)
pqc->xscom_ops = &pnv_quad_power9_xscom_ops;
}
+static void pnv_quad_power10_class_init(ObjectClass *oc, void *data)
+{
+ PnvQuadClass *pqc = PNV_QUAD_CLASS(oc);
+
+ pqc->xscom_ops = &pnv_quad_power10_xscom_ops;
+}
+
static void pnv_quad_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
@@ -451,6 +499,11 @@ static const TypeInfo pnv_quad_infos[] = {
.name = PNV_QUAD_TYPE_NAME("power9"),
.class_init = pnv_quad_power9_class_init,
},
+ {
+ .parent = TYPE_PNV_QUAD,
+ .name = PNV_QUAD_TYPE_NAME("power10"),
+ .class_init = pnv_quad_power10_class_init,
+ },
};
DEFINE_TYPES(pnv_quad_infos);
--
2.40.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [PATCH 3/4] ppc/pnv: Add P10 quad ops
2023-06-30 3:55 ` [PATCH 3/4] ppc/pnv: Add P10 quad ops Joel Stanley
@ 2023-06-30 5:24 ` Cédric Le Goater
2023-06-30 7:30 ` Frederic Barrat
1 sibling, 0 replies; 15+ messages in thread
From: Cédric Le Goater @ 2023-06-30 5:24 UTC (permalink / raw)
To: Joel Stanley, Nicholas Piggin, Frédéric Barrat
Cc: qemu-devel, qemu-ppc
On 6/30/23 05:55, Joel Stanley wrote:
> Add a PnvQuad class for the P10 powernv machine. No xscoms are
> implemented yet, but this allows them to be added.
>
> Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Thanks,
C.
> ---
> hw/ppc/pnv.c | 2 +-
> hw/ppc/pnv_core.c | 53 +++++++++++++++++++++++++++++++++++++++++++++++
> 2 files changed, 54 insertions(+), 1 deletion(-)
>
> diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
> index c77fdb6747a4..5f25fe985ab2 100644
> --- a/hw/ppc/pnv.c
> +++ b/hw/ppc/pnv.c
> @@ -1669,7 +1669,7 @@ static void pnv_chip_power10_quad_realize(Pnv10Chip *chip10, Error **errp)
> PnvQuad *eq = &chip10->quads[i];
>
> pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4],
> - PNV_QUAD_TYPE_NAME("power9"));
> + PNV_QUAD_TYPE_NAME("power10"));
>
> pnv_xscom_add_subregion(chip, PNV10_XSCOM_EQ_BASE(eq->quad_id),
> &eq->xscom_regs);
> diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c
> index b9a57463aec4..7fff2fd9e298 100644
> --- a/hw/ppc/pnv_core.c
> +++ b/hw/ppc/pnv_core.c
> @@ -404,6 +404,47 @@ static const MemoryRegionOps pnv_quad_power9_xscom_ops = {
> .endianness = DEVICE_BIG_ENDIAN,
> };
>
> +/*
> + * POWER10 Quads
> + */
> +
> +static uint64_t pnv_quad_power10_xscom_read(void *opaque, hwaddr addr,
> + unsigned int width)
> +{
> + uint32_t offset = addr >> 3;
> + uint64_t val = -1;
> +
> + switch (offset) {
> + default:
> + qemu_log_mask(LOG_UNIMP, "%s: writing @0x%08x\n", __func__,
> + offset);
> + }
> +
> + return val;
> +}
> +
> +static void pnv_quad_power10_xscom_write(void *opaque, hwaddr addr, uint64_t val,
> + unsigned int width)
> +{
> + uint32_t offset = addr >> 3;
> +
> + switch (offset) {
> + default:
> + qemu_log_mask(LOG_UNIMP, "%s: writing @0x%08x\n", __func__,
> + offset);
> + }
> +}
> +
> +static const MemoryRegionOps pnv_quad_power10_xscom_ops = {
> + .read = pnv_quad_power10_xscom_read,
> + .write = pnv_quad_power10_xscom_write,
> + .valid.min_access_size = 8,
> + .valid.max_access_size = 8,
> + .impl.min_access_size = 8,
> + .impl.max_access_size = 8,
> + .endianness = DEVICE_BIG_ENDIAN,
> +};
> +
> static void pnv_quad_realize(DeviceState *dev, Error **errp)
> {
> PnvQuad *eq = PNV_QUAD(dev);
> @@ -428,6 +469,13 @@ static void pnv_quad_power9_class_init(ObjectClass *oc, void *data)
> pqc->xscom_ops = &pnv_quad_power9_xscom_ops;
> }
>
> +static void pnv_quad_power10_class_init(ObjectClass *oc, void *data)
> +{
> + PnvQuadClass *pqc = PNV_QUAD_CLASS(oc);
> +
> + pqc->xscom_ops = &pnv_quad_power10_xscom_ops;
> +}
> +
> static void pnv_quad_class_init(ObjectClass *oc, void *data)
> {
> DeviceClass *dc = DEVICE_CLASS(oc);
> @@ -451,6 +499,11 @@ static const TypeInfo pnv_quad_infos[] = {
> .name = PNV_QUAD_TYPE_NAME("power9"),
> .class_init = pnv_quad_power9_class_init,
> },
> + {
> + .parent = TYPE_PNV_QUAD,
> + .name = PNV_QUAD_TYPE_NAME("power10"),
> + .class_init = pnv_quad_power10_class_init,
> + },
> };
>
> DEFINE_TYPES(pnv_quad_infos);
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [PATCH 3/4] ppc/pnv: Add P10 quad ops
2023-06-30 3:55 ` [PATCH 3/4] ppc/pnv: Add P10 quad ops Joel Stanley
2023-06-30 5:24 ` Cédric Le Goater
@ 2023-06-30 7:30 ` Frederic Barrat
2023-06-30 7:35 ` Joel Stanley
1 sibling, 1 reply; 15+ messages in thread
From: Frederic Barrat @ 2023-06-30 7:30 UTC (permalink / raw)
To: Joel Stanley, Cédric Le Goater, Nicholas Piggin; +Cc: qemu-devel, qemu-ppc
On 30/06/2023 05:55, Joel Stanley wrote:
> diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c
> index b9a57463aec4..7fff2fd9e298 100644
> --- a/hw/ppc/pnv_core.c
> +++ b/hw/ppc/pnv_core.c
> +static uint64_t pnv_quad_power10_xscom_read(void *opaque, hwaddr addr,
...
> + qemu_log_mask(LOG_UNIMP, "%s: writing @0x%08x\n", __func__,
^^^ reading
I'm guessing we'll need to flush out that function pretty soon, so not
worth resending.
Fred
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [PATCH 3/4] ppc/pnv: Add P10 quad ops
2023-06-30 7:30 ` Frederic Barrat
@ 2023-06-30 7:35 ` Joel Stanley
2023-06-30 7:44 ` Cédric Le Goater
0 siblings, 1 reply; 15+ messages in thread
From: Joel Stanley @ 2023-06-30 7:35 UTC (permalink / raw)
To: Frederic Barrat
Cc: Cédric Le Goater, Nicholas Piggin, qemu-devel, qemu-ppc
On Fri, 30 Jun 2023 at 07:30, Frederic Barrat <fbarrat@linux.ibm.com> wrote:
>
>
>
> On 30/06/2023 05:55, Joel Stanley wrote:
> > diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c
> > index b9a57463aec4..7fff2fd9e298 100644
> > --- a/hw/ppc/pnv_core.c
> > +++ b/hw/ppc/pnv_core.c
>
> > +static uint64_t pnv_quad_power10_xscom_read(void *opaque, hwaddr addr,
> ...
> > + qemu_log_mask(LOG_UNIMP, "%s: writing @0x%08x\n", __func__,
>
> ^^^ reading
>
> I'm guessing we'll need to flush out that function pretty soon, so not
> worth resending.
Thanks, good catch. It's incorrect in the p9 callback too.
I had it fixed locally along with a re-wording to make it clear the
message was for unimplemented operations, but decided not to send
that.
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 3/4] ppc/pnv: Add P10 quad ops
2023-06-30 7:35 ` Joel Stanley
@ 2023-06-30 7:44 ` Cédric Le Goater
2023-06-30 13:47 ` Daniel Henrique Barboza
0 siblings, 1 reply; 15+ messages in thread
From: Cédric Le Goater @ 2023-06-30 7:44 UTC (permalink / raw)
To: Joel Stanley, Frederic Barrat; +Cc: Nicholas Piggin, qemu-devel, qemu-ppc
On 6/30/23 09:35, Joel Stanley wrote:
> On Fri, 30 Jun 2023 at 07:30, Frederic Barrat <fbarrat@linux.ibm.com> wrote:
>>
>>
>>
>> On 30/06/2023 05:55, Joel Stanley wrote:
>>> diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c
>>> index b9a57463aec4..7fff2fd9e298 100644
>>> --- a/hw/ppc/pnv_core.c
>>> +++ b/hw/ppc/pnv_core.c
>>
>>> +static uint64_t pnv_quad_power10_xscom_read(void *opaque, hwaddr addr,
>> ...
>>> + qemu_log_mask(LOG_UNIMP, "%s: writing @0x%08x\n", __func__,
>>
>> ^^^ reading
>>
>> I'm guessing we'll need to flush out that function pretty soon, so not
>> worth resending.
>
> Thanks, good catch. It's incorrect in the p9 callback too.
>
> I had it fixed locally along with a re-wording to make it clear the
> message was for unimplemented operations, but decided not to send
> that.
There is still time for a v2 ! Please keep the R-b.
Thanks,
C.
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 3/4] ppc/pnv: Add P10 quad ops
2023-06-30 7:44 ` Cédric Le Goater
@ 2023-06-30 13:47 ` Daniel Henrique Barboza
0 siblings, 0 replies; 15+ messages in thread
From: Daniel Henrique Barboza @ 2023-06-30 13:47 UTC (permalink / raw)
To: Cédric Le Goater, Joel Stanley, Frederic Barrat
Cc: Nicholas Piggin, qemu-devel, qemu-ppc
On 6/30/23 04:44, Cédric Le Goater wrote:
> On 6/30/23 09:35, Joel Stanley wrote:
>> On Fri, 30 Jun 2023 at 07:30, Frederic Barrat <fbarrat@linux.ibm.com> wrote:
>>>
>>>
>>>
>>> On 30/06/2023 05:55, Joel Stanley wrote:
>>>> diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c
>>>> index b9a57463aec4..7fff2fd9e298 100644
>>>> --- a/hw/ppc/pnv_core.c
>>>> +++ b/hw/ppc/pnv_core.c
>>>
>>>> +static uint64_t pnv_quad_power10_xscom_read(void *opaque, hwaddr addr,
>>> ...
>>>> + qemu_log_mask(LOG_UNIMP, "%s: writing @0x%08x\n", __func__,
>>>
>>> ^^^ reading
>>>
>>> I'm guessing we'll need to flush out that function pretty soon, so not
>>> worth resending.
>>
>> Thanks, good catch. It's incorrect in the p9 callback too.
>>
>> I had it fixed locally along with a re-wording to make it clear the
>> message was for unimplemented operations, but decided not to send
>> that.
>
>
> There is still time for a v2 ! Please keep the R-b.
Since you're sending a v2 please fix the 80+ char line in patch 4 to make
checkpatch.pl happy:
-static void pnv_quad_power10_xscom_write(void *opaque, hwaddr addr, uint64_t val,
- unsigned int width)
+static void pnv_quad_power10_xscom_write(void *opaque, hwaddr addr,
+ uint64_t val, unsigned int width)
I'll not queue the series for now.
Daniel
>
> Thanks,
>
> C.
>
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 4/4] ppc/pnv: Return zero for core thread state xscom
2023-06-30 3:55 [PATCH 0/4] ppc/pnv: Extend "quad" model for p10 Joel Stanley
` (2 preceding siblings ...)
2023-06-30 3:55 ` [PATCH 3/4] ppc/pnv: Add P10 quad ops Joel Stanley
@ 2023-06-30 3:55 ` Joel Stanley
2023-06-30 5:24 ` Cédric Le Goater
2023-07-01 10:22 ` Nicholas Piggin
2023-07-01 10:10 ` [PATCH 0/4] ppc/pnv: Extend "quad" model for p10 Nicholas Piggin
4 siblings, 2 replies; 15+ messages in thread
From: Joel Stanley @ 2023-06-30 3:55 UTC (permalink / raw)
To: Cédric Le Goater, Nicholas Piggin, Frédéric Barrat
Cc: qemu-devel, qemu-ppc
Firmware now warns if booting in LPAR per core mode (PPC bit 62). So
this warning doesn't trigger report the core thread state is 0.
Signed-off-by: Joel Stanley <joel@jms.id.au>
---
hw/ppc/pnv_core.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c
index 7fff2fd9e298..98356d7f6538 100644
--- a/hw/ppc/pnv_core.c
+++ b/hw/ppc/pnv_core.c
@@ -116,6 +116,8 @@ static const MemoryRegionOps pnv_core_power8_xscom_ops = {
#define PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_HYP 0xf010d
#define PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_OTR 0xf010a
+#define PNV9_XSCOM_EC_CORE_THREAD_STATE 0x10ab3
+
static uint64_t pnv_core_power9_xscom_read(void *opaque, hwaddr addr,
unsigned int width)
{
@@ -134,6 +136,9 @@ static uint64_t pnv_core_power9_xscom_read(void *opaque, hwaddr addr,
case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_OTR:
val = 0x0;
break;
+ case PNV9_XSCOM_EC_CORE_THREAD_STATE:
+ val = 0;
+ break;
default:
qemu_log_mask(LOG_UNIMP, "Warning: reading reg=0x%" HWADDR_PRIx "\n",
addr);
@@ -408,6 +413,8 @@ static const MemoryRegionOps pnv_quad_power9_xscom_ops = {
* POWER10 Quads
*/
+#define PNV10_XSCOM_EC_PC_PMC_CORE_THREAD_STATE 0x28412
+
static uint64_t pnv_quad_power10_xscom_read(void *opaque, hwaddr addr,
unsigned int width)
{
@@ -415,6 +422,9 @@ static uint64_t pnv_quad_power10_xscom_read(void *opaque, hwaddr addr,
uint64_t val = -1;
switch (offset) {
+ case PNV10_XSCOM_EC_PC_PMC_CORE_THREAD_STATE:
+ val = 0;
+ break;
default:
qemu_log_mask(LOG_UNIMP, "%s: writing @0x%08x\n", __func__,
offset);
--
2.40.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [PATCH 4/4] ppc/pnv: Return zero for core thread state xscom
2023-06-30 3:55 ` [PATCH 4/4] ppc/pnv: Return zero for core thread state xscom Joel Stanley
@ 2023-06-30 5:24 ` Cédric Le Goater
2023-07-01 10:22 ` Nicholas Piggin
1 sibling, 0 replies; 15+ messages in thread
From: Cédric Le Goater @ 2023-06-30 5:24 UTC (permalink / raw)
To: Joel Stanley, Nicholas Piggin, Frédéric Barrat
Cc: qemu-devel, qemu-ppc
On 6/30/23 05:55, Joel Stanley wrote:
> Firmware now warns if booting in LPAR per core mode (PPC bit 62). So
> this warning doesn't trigger report the core thread state is 0.
>
> Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Thanks,
C.
> ---
> hw/ppc/pnv_core.c | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c
> index 7fff2fd9e298..98356d7f6538 100644
> --- a/hw/ppc/pnv_core.c
> +++ b/hw/ppc/pnv_core.c
> @@ -116,6 +116,8 @@ static const MemoryRegionOps pnv_core_power8_xscom_ops = {
> #define PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_HYP 0xf010d
> #define PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_OTR 0xf010a
>
> +#define PNV9_XSCOM_EC_CORE_THREAD_STATE 0x10ab3
> +
> static uint64_t pnv_core_power9_xscom_read(void *opaque, hwaddr addr,
> unsigned int width)
> {
> @@ -134,6 +136,9 @@ static uint64_t pnv_core_power9_xscom_read(void *opaque, hwaddr addr,
> case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_OTR:
> val = 0x0;
> break;
> + case PNV9_XSCOM_EC_CORE_THREAD_STATE:
> + val = 0;
> + break;
> default:
> qemu_log_mask(LOG_UNIMP, "Warning: reading reg=0x%" HWADDR_PRIx "\n",
> addr);
> @@ -408,6 +413,8 @@ static const MemoryRegionOps pnv_quad_power9_xscom_ops = {
> * POWER10 Quads
> */
>
> +#define PNV10_XSCOM_EC_PC_PMC_CORE_THREAD_STATE 0x28412
> +
> static uint64_t pnv_quad_power10_xscom_read(void *opaque, hwaddr addr,
> unsigned int width)
> {
> @@ -415,6 +422,9 @@ static uint64_t pnv_quad_power10_xscom_read(void *opaque, hwaddr addr,
> uint64_t val = -1;
>
> switch (offset) {
> + case PNV10_XSCOM_EC_PC_PMC_CORE_THREAD_STATE:
> + val = 0;
> + break;
> default:
> qemu_log_mask(LOG_UNIMP, "%s: writing @0x%08x\n", __func__,
> offset);
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [PATCH 4/4] ppc/pnv: Return zero for core thread state xscom
2023-06-30 3:55 ` [PATCH 4/4] ppc/pnv: Return zero for core thread state xscom Joel Stanley
2023-06-30 5:24 ` Cédric Le Goater
@ 2023-07-01 10:22 ` Nicholas Piggin
1 sibling, 0 replies; 15+ messages in thread
From: Nicholas Piggin @ 2023-07-01 10:22 UTC (permalink / raw)
To: Joel Stanley, Cédric Le Goater, Frédéric Barrat
Cc: qemu-devel, qemu-ppc
On Fri Jun 30, 2023 at 1:55 PM AEST, Joel Stanley wrote:
> Firmware now warns if booting in LPAR per core mode (PPC bit 62). So
> this warning doesn't trigger report the core thread state is 0.
>
> Signed-off-by: Joel Stanley <joel@jms.id.au>
> ---
> hw/ppc/pnv_core.c | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c
> index 7fff2fd9e298..98356d7f6538 100644
> --- a/hw/ppc/pnv_core.c
> +++ b/hw/ppc/pnv_core.c
> @@ -116,6 +116,8 @@ static const MemoryRegionOps pnv_core_power8_xscom_ops = {
> #define PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_HYP 0xf010d
> #define PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_OTR 0xf010a
>
> +#define PNV9_XSCOM_EC_CORE_THREAD_STATE 0x10ab3
> +
> static uint64_t pnv_core_power9_xscom_read(void *opaque, hwaddr addr,
> unsigned int width)
> {
> @@ -134,6 +136,9 @@ static uint64_t pnv_core_power9_xscom_read(void *opaque, hwaddr addr,
> case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_OTR:
> val = 0x0;
> break;
> + case PNV9_XSCOM_EC_CORE_THREAD_STATE:
> + val = 0;
> + break;
> default:
> qemu_log_mask(LOG_UNIMP, "Warning: reading reg=0x%" HWADDR_PRIx "\n",
> addr);
> @@ -408,6 +413,8 @@ static const MemoryRegionOps pnv_quad_power9_xscom_ops = {
> * POWER10 Quads
> */
>
> +#define PNV10_XSCOM_EC_PC_PMC_CORE_THREAD_STATE 0x28412
> +
> static uint64_t pnv_quad_power10_xscom_read(void *opaque, hwaddr addr,
> unsigned int width)
> {
> @@ -415,6 +422,9 @@ static uint64_t pnv_quad_power10_xscom_read(void *opaque, hwaddr addr,
> uint64_t val = -1;
>
> switch (offset) {
> + case PNV10_XSCOM_EC_PC_PMC_CORE_THREAD_STATE:
> + val = 0;
> + break;
> default:
> qemu_log_mask(LOG_UNIMP, "%s: writing @0x%08x\n", __func__,
> offset);
Yeah this is the problem, this is just addressing one core in the quad.
AFAIKS P9 may have the same problem though so I don't blame the
confusion.
The other patches seem good because we'll want a P10 quad too I think.
Thanks,
Nick
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 0/4] ppc/pnv: Extend "quad" model for p10
2023-06-30 3:55 [PATCH 0/4] ppc/pnv: Extend "quad" model for p10 Joel Stanley
` (3 preceding siblings ...)
2023-06-30 3:55 ` [PATCH 4/4] ppc/pnv: Return zero for core thread state xscom Joel Stanley
@ 2023-07-01 10:10 ` Nicholas Piggin
4 siblings, 0 replies; 15+ messages in thread
From: Nicholas Piggin @ 2023-07-01 10:10 UTC (permalink / raw)
To: Joel Stanley, Cédric Le Goater, Frédéric Barrat
Cc: qemu-devel, qemu-ppc
On Fri Jun 30, 2023 at 1:55 PM AEST, Joel Stanley wrote:
> The quad model implements the EC xscoms for the p9 machine, reusing the
> same model for p10 which isn't quite correct. This series adds a PnvQuad
> class and subclasses it for P9 and P10. Implement the core thread state
> xscom as an example. I expect more function to be implemented in future
> patches.
>
> There's one outstanding question. Skiboot has this for the p10 scom:
>
> #define P10_EC_CORE_THREAD_STATE 0x412
>
> However the read that comes is for 0x28412. I suspect the upper 0x28000
> are addressing bits, so we're really reporting the core thread state for
> the given core. Should the model instead wired so one is created for
> each chiplet? Or should we report the value for all possible cores, like
> the P9 code does for P9X_EX_NCU_SPEC_BAR?
>
> switch (offset) {
> case P9X_EX_NCU_SPEC_BAR:
> case P9X_EX_NCU_SPEC_BAR + 0x400: /* Second EX */
Yes you're right, 0x28000 is addressing within the quad. The 0x2 selects
core/cache/NCU/etc and the 8 is a one-hot encoding to select the core.
So this access should actually be redirected to the pnv core scoms. I
think to make that work, those regions have to be a subregion of the
quad, right now they seem to overlap (the sizes are a bit wrong too,
they end up overlapping).
0x412 is then a register in a particular core's "PC" unit. I assume PC
is probably 0x800 or 0x1000 in size.
The quad itself has a QME engine, so you might address that with the
quad registers.
IIRC the actual topology is something like
EQ +--- EX +--- ECL2 +--- EC
| +--- L3 +--- L2
+--- QME +--- NCU
+--- maybe some scom and sensor stuff
No point modeling all that of course, just per-core and per-quad regions
like it already has for now. But if for example we wanted to model some
registers in the L2, it would not be contiguous with the core addresses
so we'd have to add it.
Thanks,
Nick
>
> Joel Stanley (4):
> ppc/pnv: quad xscom callbacks are P9 specific
> ppc/pnv: Subclass quad xscom callbacks
> ppc/pnv: Add P10 quad ops
> ppc/pnv: Return zero for core thread state xscom
>
> include/hw/ppc/pnv_core.h | 12 +++-
> hw/ppc/pnv.c | 11 ++--
> hw/ppc/pnv_core.c | 114 +++++++++++++++++++++++++++++++-------
> 3 files changed, 113 insertions(+), 24 deletions(-)
^ permalink raw reply [flat|nested] 15+ messages in thread