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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id y13sm13721145pfb.48.2019.08.20.16.54.56 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 20 Aug 2019 16:54:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org References: <20190820210720.18976-1-richard.henderson@linaro.org> Openpgp: preference=signencrypt Message-ID: Date: Tue, 20 Aug 2019 16:54:54 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.8.0 MIME-Version: 1.0 In-Reply-To: <20190820210720.18976-1-richard.henderson@linaro.org> Content-Type: multipart/mixed; boundary="------------5233F652544173C873D1DD62" Content-Language: en-US X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::644 Subject: Re: [Qemu-devel] [PATCH v5 00/17] target/arm: Reduce overhead of cpu_get_tb_cpu_state X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" This is a multi-part message in MIME format. --------------5233F652544173C873D1DD62 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit On 8/20/19 2:07 PM, Richard Henderson wrote: > Changes since v4: > * Split patch 1 into 15 smaller patches. > * Cache the new DEBUG_TARGET_EL field. > * Split out m-profile hflags separately from a-profile 32-bit. > * Move around non-cached tb flags as well, avoiding repetitive > checks for m-profile or other mutually exclusive conditions. Just after I posted this, I started rebasing my VHE patch set on top, and I found that the new DEBUG_TARGET_EL field has used The Last Bit, so that I could not add the one bit that I need for VHE. However, while working on this patch set, I noticed that we have a lot of unnecessary overlap between A- and M- profile in the TBFLAGs. Thus point 4 above and the completely separate rebuild_hflags_m32(). If we rearrange things like the appended, then we recover 4 bits. Thoughts? r~ --------------5233F652544173C873D1DD62 Content-Type: text/x-patch; name="m-tbflag.patch" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename="m-tbflag.patch" diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 91a54662c3..0c2803baa1 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3183,38 +3183,50 @@ FIELD(TBFLAG_ANY, BE_DATA, 23, 1) */ FIELD(TBFLAG_ANY, DEBUG_TARGET_EL, 21, 2) -/* Bit usage when in AArch32 state: */ -FIELD(TBFLAG_A32, THUMB, 0, 1) /* Not cached. */ -FIELD(TBFLAG_A32, VECLEN, 1, 3) /* Not cached. */ -FIELD(TBFLAG_A32, VECSTRIDE, 4, 2) /* Not cached. */ +/* + * Bit usage when in AArch32 state, both A- and M-profile. + */ +FIELD(TBFLAG_AM32, CONDEXEC, 0, 8) /* Not cached. */ + +/* + * Bit usage when in AArch32 state, for A-profile only. + */ +FIELD(TBFLAG_A32, THUMB, 8, 1) /* Not cached. */ +FIELD(TBFLAG_A32, VECLEN, 9, 3) /* Not cached. */ +FIELD(TBFLAG_A32, VECSTRIDE, 12, 2) /* Not cached. */ /* * We store the bottom two bits of the CPAR as TB flags and handle * checks on the other bits at runtime. This shares the same bits as * VECSTRIDE, which is OK as no XScale CPU has VFP. * Not cached, because VECLEN+VECSTRIDE are not cached. */ -FIELD(TBFLAG_A32, XSCALE_CPAR, 4, 2) +FIELD(TBFLAG_A32, XSCALE_CPAR, 12, 2) +FIELD(TBFLAG_A32, VFPEN, 14, 1) /* Partially cached, minus FPEXC. */ +FIELD(TBFLAG_A32, SCTLR_B, 15, 1) /* * Indicates whether cp register reads and writes by guest code should access * the secure or nonsecure bank of banked registers; note that this is not * the same thing as the current security state of the processor! */ -FIELD(TBFLAG_A32, NS, 6, 1) -FIELD(TBFLAG_A32, VFPEN, 7, 1) /* Partially cached, minus FPEXC. */ -FIELD(TBFLAG_A32, CONDEXEC, 8, 8) /* Not cached. */ -FIELD(TBFLAG_A32, SCTLR_B, 16, 1) -/* For M profile only, set if FPCCR.LSPACT is set */ -FIELD(TBFLAG_A32, LSPACT, 18, 1) /* Not cached. */ -/* For M profile only, set if we must create a new FP context */ -FIELD(TBFLAG_A32, NEW_FP_CTXT_NEEDED, 19, 1) /* Not cached. */ -/* For M profile only, set if FPCCR.S does not match current security state */ -FIELD(TBFLAG_A32, FPCCR_S_WRONG, 20, 1) /* Not cached. */ -/* For M profile only, Handler (ie not Thread) mode */ -FIELD(TBFLAG_A32, HANDLER, 21, 1) -/* For M profile only, whether we should generate stack-limit checks */ -FIELD(TBFLAG_A32, STACKCHECK, 22, 1) +FIELD(TBFLAG_A32, NS, 16, 1) -/* Bit usage when in AArch64 state */ +/* + * Bit usage when in AArch32 state, for M-profile only. + */ +/* Set if FPCCR.LSPACT is set */ +FIELD(TBFLAG_M32, LSPACT, 8, 1) /* Not cached. */ +/* Set if we must create a new FP context */ +FIELD(TBFLAG_M32, NEW_FP_CTXT_NEEDED, 9, 1) /* Not cached. */ +/* Set if FPCCR.S does not match current security state */ +FIELD(TBFLAG_M32, FPCCR_S_WRONG, 10, 1) /* Not cached. */ +/* Handler (ie not Thread) mode */ +FIELD(TBFLAG_A32, HANDLER, 11, 1) +/* Whether we should generate stack-limit checks */ +FIELD(TBFLAG_A32, STACKCHECK, 12, 1) + +/* + * Bit usage when in AArch64 state + */ FIELD(TBFLAG_A64, TBII, 0, 2) FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2) FIELD(TBFLAG_A64, ZCR_LEN, 4, 4) --------------5233F652544173C873D1DD62--