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[97.126.123.70]) by smtp.gmail.com with ESMTPSA id p1sm20760144pfq.114.2020.03.14.00.35.18 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 14 Mar 2020 00:35:19 -0700 (PDT) Subject: Re: [PATCH v5 22/60] target/riscv: vector integer merge and move instructions To: LIU Zhiwei , alistair23@gmail.com, chihmin.chao@sifive.com, palmer@dabbelt.com References: <20200312145900.2054-1-zhiwei_liu@c-sky.com> <20200312145900.2054-23-zhiwei_liu@c-sky.com> From: Richard Henderson Message-ID: Date: Sat, 14 Mar 2020 00:27:55 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.4.1 MIME-Version: 1.0 In-Reply-To: <20200312145900.2054-23-zhiwei_liu@c-sky.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::441 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: guoren@linux.alibaba.com, wenmeng_zhang@c-sky.com, qemu-riscv@nongnu.org, qemu-devel@nongnu.org, wxy194768@alibaba-inc.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 3/12/20 7:58 AM, LIU Zhiwei wrote: > +/* Vector Integer Merge and Move Instructions */ > +static bool opivv_vmerge_check(DisasContext *s, arg_rmrr *a) > +{ > + return (vext_check_isa_ill(s, RVV) && > + vext_check_overlap_mask(s, a->rd, a->vm, false) && > + vext_check_reg(s, a->rd, false) && > + vext_check_reg(s, a->rs2, false) && > + vext_check_reg(s, a->rs1, false) && > + ((a->vm == 0) || (a->rs2 == 0))); > +} > +GEN_OPIVV_TRANS(vmerge_vvm, opivv_vmerge_check) > + > +static bool opivx_vmerge_check(DisasContext *s, arg_rmrr *a) > +{ > + return (vext_check_isa_ill(s, RVV) && > + vext_check_overlap_mask(s, a->rd, a->vm, false) && > + vext_check_reg(s, a->rd, false) && > + vext_check_reg(s, a->rs2, false) && > + ((a->vm == 0) || (a->rs2 == 0))); > +} > +GEN_OPIVX_TRANS(vmerge_vxm, opivx_vmerge_check) > + > +GEN_OPIVI_TRANS(vmerge_vim, 0, vmerge_vxm, opivx_vmerge_check) I think you need to special case these. The unmasked instructions are the canonical move instructions: vmv.v.*. You definitely want to use tcg_gen_gvec_mov (vv), tcg_gen_gvec_dup_i{32,64} (vx) and tcg_gen_gvec_dup{8,16,32,64}i (vi). > + if (!vm && !vext_elem_mask(v0, mlen, i)) { \ > + ETYPE s2 = *((ETYPE *)vs2 + H(i)); \ > + *((ETYPE *)vd + H1(i)) = s2; \ > + } else { \ > + ETYPE s1 = *((ETYPE *)vs1 + H(i)); \ > + *((ETYPE *)vd + H(i)) = s1; \ > + } \ Perhaps better as ETYPE *vt = (!vm && !vext_elem_mask(v0, mlen, i) ? vs2 : vs1); *((ETYPE *)vd + H(i)) = *((ETYPE *)vt + H(i)); > + if (!vm && !vext_elem_mask(v0, mlen, i)) { \ > + ETYPE s2 = *((ETYPE *)vs2 + H(i)); \ > + *((ETYPE *)vd + H1(i)) = s2; \ > + } else { \ > + *((ETYPE *)vd + H(i)) = (ETYPE)(target_long)s1; \ > + } \ Perhaps better as ETYPE s2 = *((ETYPE *)vs2 + H(i)); ETYPE d = (!vm && !vext_elem_mask(v0, mlen, i) ? s2 : (ETYPE)(target_long)s1); *((ETYPE *)vd + H(i)) = d; as most host platforms have a conditional reg-reg move, but not a conditional load. r~