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From: Luc Michel <luc.michel@greensocs.com>
To: "Lukas Jünger" <lukas.juenger@greensocs.com>, qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, bin.meng@windriver.com,
	mark.burton@greensocs.com, marcandre.lureau@redhat.com,
	palmer@dabbelt.com, pbonzini@redhat.com,
	alistair.francis@wdc.com
Subject: Re: [PATCH 2/2] QOMify sifive_uart model
Date: Tue, 11 May 2021 13:39:29 +0200	[thread overview]
Message-ID: <db034556-100d-7856-13b0-ea451d6fb1cb@greensocs.com> (raw)
In-Reply-To: <20210504153456.927083-3-lukas.juenger@greensocs.com>

On 5/4/21 5:34 PM, Lukas Jünger wrote:
> Signed-off-by: Lukas Jünger <lukas.juenger@greensocs.com>

Reviewed-by: Luc Michel <luc.michel@greensocs.com>

> ---
>   include/hw/char/sifive_uart.h |  6 +--
>   hw/char/sifive_uart.c         | 72 ++++++++++++++++++++++++++++++-----
>   2 files changed, 65 insertions(+), 13 deletions(-)
> 
> diff --git a/include/hw/char/sifive_uart.h b/include/hw/char/sifive_uart.h
> index 3e962be659..45d66b1db5 100644
> --- a/include/hw/char/sifive_uart.h
> +++ b/include/hw/char/sifive_uart.h
> @@ -21,6 +21,7 @@
>   #define HW_SIFIVE_UART_H
>   
>   #include "chardev/char-fe.h"
> +#include "hw/qdev-properties.h"
>   #include "hw/sysbus.h"
>   #include "qom/object.h"
>   
> @@ -51,10 +52,7 @@ enum {
>   #define SIFIVE_UART_GET_RXCNT(rxctrl)   ((rxctrl >> 16) & 0x7)
>   
>   #define TYPE_SIFIVE_UART "riscv.sifive.uart"
> -
> -typedef struct SiFiveUARTState SiFiveUARTState;
> -DECLARE_INSTANCE_CHECKER(SiFiveUARTState, SIFIVE_UART,
> -                         TYPE_SIFIVE_UART)
> +OBJECT_DECLARE_SIMPLE_TYPE(SiFiveUARTState, SIFIVE_UART)
>   
>   struct SiFiveUARTState {
>       /*< private >*/
> diff --git a/hw/char/sifive_uart.c b/hw/char/sifive_uart.c
> index cb70374ead..0307568d0a 100644
> --- a/hw/char/sifive_uart.c
> +++ b/hw/char/sifive_uart.c
> @@ -25,6 +25,7 @@
>   #include "hw/hw.h"
>   #include "hw/irq.h"
>   #include "hw/char/sifive_uart.h"
> +#include "hw/qdev-properties-system.h"
>   
>   /*
>    * Not yet implemented:
> @@ -176,19 +177,72 @@ static int uart_be_change(void *opaque)
>       return 0;
>   }
>   
> +static Property sifive_uart_properties[] = {
> +    DEFINE_PROP_CHR("chardev", SiFiveUARTState, chr),
> +    DEFINE_PROP_END_OF_LIST(),
> +};
> +
> +static void sifive_uart_init(Object *obj)
> +{
> +    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
> +    SiFiveUARTState *s = SIFIVE_UART(obj);
> +
> +    memory_region_init_io(&s->mmio, OBJECT(s), &sifive_uart_ops, s,
> +                          TYPE_SIFIVE_UART, SIFIVE_UART_MAX);
> +    sysbus_init_mmio(sbd, &s->mmio);
> +    sysbus_init_irq(sbd, &s->irq);
> +}
> +
> +static void sifive_uart_realize(DeviceState *dev, Error **errp)
> +{
> +    SiFiveUARTState *s = SIFIVE_UART(dev);
> +
> +    qemu_chr_fe_set_handlers(&s->chr, uart_can_rx, uart_rx, uart_event,
> +                             uart_be_change, s, NULL, true);
> +
> +}
> +
> +static void sifive_uart_class_init(ObjectClass *oc, void *data)
> +{
> +    DeviceClass *dc = DEVICE_CLASS(oc);
> +
> +    dc->realize = sifive_uart_realize;
> +    device_class_set_props(dc, sifive_uart_properties);
> +}
> +
> +static const TypeInfo sifive_uart_info = {
> +    .name          = TYPE_SIFIVE_UART,
> +    .parent        = TYPE_SYS_BUS_DEVICE,
> +    .instance_size = sizeof(SiFiveUARTState),
> +    .instance_init = sifive_uart_init,
> +    .class_init    = sifive_uart_class_init,
> +};
> +
> +static void sifive_uart_register_types(void)
> +{
> +    type_register_static(&sifive_uart_info);
> +}
> +
> +type_init(sifive_uart_register_types)
> +
>   /*
>    * Create UART device.
>    */
>   SiFiveUARTState *sifive_uart_create(MemoryRegion *address_space, hwaddr base,
>       Chardev *chr, qemu_irq irq)
>   {
> -    SiFiveUARTState *s = g_malloc0(sizeof(SiFiveUARTState));
> -    s->irq = irq;
> -    qemu_chr_fe_init(&s->chr, chr, &error_abort);
> -    qemu_chr_fe_set_handlers(&s->chr, uart_can_rx, uart_rx, uart_event,
> -        uart_be_change, s, NULL, true);
> -    memory_region_init_io(&s->mmio, NULL, &sifive_uart_ops, s,
> -                          TYPE_SIFIVE_UART, SIFIVE_UART_MAX);
> -    memory_region_add_subregion(address_space, base, &s->mmio);
> -    return s;
> +    DeviceState *dev;
> +    SysBusDevice *s;
> +    SiFiveUARTState *r;
> +
> +    dev = qdev_new("riscv.sifive.uart");
> +    s = SYS_BUS_DEVICE(dev);
> +    qdev_prop_set_chr(dev, "chardev", chr);
> +    sysbus_realize_and_unref(s, &error_fatal);
> +    memory_region_add_subregion(address_space, base,
> +                                sysbus_mmio_get_region(s, 0));
> +    sysbus_connect_irq(s, 0, irq);
> +
> +    r = SIFIVE_UART(dev);
> +    return r;
>   }
> 


  reply	other threads:[~2021-05-11 11:44 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-05-04 15:34 [PATCH 0/2] QOMify Sifive UART model Lukas Jünger
2021-05-04 15:34 ` [PATCH 1/2] Consistent function names for sifive uart read and write function Lukas Jünger
2021-05-06  2:12   ` Alistair Francis
2021-05-11 11:38   ` Luc Michel
2021-05-11 13:06   ` Bin Meng
2021-05-04 15:34 ` [PATCH 2/2] QOMify sifive_uart model Lukas Jünger
2021-05-11 11:39   ` Luc Michel [this message]
2021-05-11 12:26   ` Philippe Mathieu-Daudé
2021-05-16 11:13     ` Lukas Jünger

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