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Mon, 1 Jul 2024 02:57:45 -0400 (EDT) X-Mailer: MessagingEngine.com Webmail Interface User-Agent: Cyrus-JMAP/3.11.0-alpha0-566-g3812ddbbc-fm-20240627.001-g3812ddbb MIME-Version: 1.0 Message-Id: In-Reply-To: <20240530064941.1289573-2-maobibo@loongson.cn> References: <20240530064941.1289573-1-maobibo@loongson.cn> <20240530064941.1289573-2-maobibo@loongson.cn> Date: Mon, 01 Jul 2024 07:57:31 +0100 From: "Jiaxun Yang" To: "Bibo Mao" , "Song Gao" , =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= Cc: "QEMU devel" Subject: Re: [RFC v3 1/2] target/loongarch: Add loongson binary translation feature Content-Type: text/plain;charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=103.168.172.149; envelope-from=jiaxun.yang@flygoat.com; helo=fout6-smtp.messagingengine.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org =E5=9C=A82024=E5=B9=B45=E6=9C=8830=E6=97=A5=E4=BA=94=E6=9C=88 =E4=B8=8A=E5= =8D=887:49=EF=BC=8CBibo Mao=E5=86=99=E9=81=93=EF=BC=9A > Loongson Binary Translation (LBT) is used to accelerate binary > translation, which contains 4 scratch registers (scr0 to scr3), x86/ARM > eflags (eflags) and x87 fpu stack pointer (ftop). > > Now LBT feature is added in kvm mode, not supported in TCG mode since > it is not emulated. Feature variable lbt is added with OnOffAuto type, > If lbt feature is not supported with KVM host, it reports error if the= re > is lbt=3Don command line. > > If there is no any command line about lbt parameter, it checks whether > KVM host supports lbt feature and set the corresponding value in cpucf= g. > > Signed-off-by: Bibo Mao Hi Bibo, I was going across recent LoongArch changes and this comes into my atten= tion:=20 > --- > target/loongarch/cpu.c | 53 +++++++++++++++++++++++++++ > target/loongarch/cpu.h | 6 +++ > target/loongarch/kvm/kvm.c | 26 +++++++++++++ > target/loongarch/kvm/kvm_loongarch.h | 16 ++++++++ > target/loongarch/loongarch-qmp-cmds.c | 2 +- > 5 files changed, 102 insertions(+), 1 deletion(-) > > diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c > index b5c1ec94af..14265b6667 100644 > --- a/target/loongarch/cpu.c > +++ b/target/loongarch/cpu.c > @@ -571,6 +571,30 @@ static void loongarch_cpu_disas_set_info(CPUState=20 > *s, disassemble_info *info) > info->print_insn =3D print_insn_loongarch; > } >=20 > +static void loongarch_cpu_check_lbt(CPUState *cs, Error **errp) > +{ > + CPULoongArchState *env =3D cpu_env(cs); > + LoongArchCPU *cpu =3D LOONGARCH_CPU(cs); > + bool kvm_supported; > + > + kvm_supported =3D kvm_feature_supported(cs, LOONGARCH_FEATURE_LBT= ); IMHO if there is no global states that should be saved/restored VM wise, this should be handled at per CPU level, preferably with CPUCFG flags hi= nt. We should minimize non-privilege KVM feature bits to prevent hindering asymmetry ISA system. Thanks - Jiaxun --=20 - Jiaxun