From: Richard Henderson <richard.henderson@linaro.org>
To: Stephen Long <steplong@quicinc.com>, qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org, apazos@quicinc.com
Subject: Re: [PATCH RFC 0/3] target/arm: Implement SVE2 fp conversion
Date: Tue, 16 Jun 2020 12:00:06 -0700 [thread overview]
Message-ID: <db57c0a3-634f-caef-cab6-8b692a22e661@linaro.org> (raw)
In-Reply-To: <20200428174332.17162-1-steplong@quicinc.com>
On 4/28/20 10:43 AM, Stephen Long wrote:
> The only insn left in this category is BFCVTNT. I couldn't find any
> helper functions for bfloats so I'm not sure how to approach this insn.
>
> Also, for insn FCVTXNT, I'm not sure if it is ok to set the status rounding
> mode to odd like that.
>
> Stephen Long (3):
> target/arm: Implement SVE2 FCVTNT
> target/arm: Implement SVE2 FCVTLT
> target/arm: Implement SVE2 FCVTXNT
Queued, with the change to the third patch as mentioned.
r~
prev parent reply other threads:[~2020-06-16 19:02 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-28 17:43 [PATCH RFC 0/3] target/arm: Implement SVE2 fp conversion Stephen Long
2020-04-28 17:43 ` [PATCH RFC 1/3] target/arm: Implement SVE2 FCVTNT Stephen Long
2020-04-28 17:43 ` [PATCH RFC 2/3] target/arm: Implement SVE2 FCVTLT Stephen Long
2020-04-28 17:43 ` [PATCH RFC 3/3] target/arm: Implement SVE2 FCVTXNT Stephen Long
2020-06-16 18:59 ` Richard Henderson
2020-06-16 19:00 ` Richard Henderson [this message]
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