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([2602:47:d49d:ec01:986f:cb56:6709:4057]) by smtp.gmail.com with ESMTPSA id mh17-20020a17090b4ad100b0020322204672sm2441730pjb.38.2022.09.28.21.30.16 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 28 Sep 2022 21:30:17 -0700 (PDT) Message-ID: Date: Wed, 28 Sep 2022 21:30:15 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.11.0 Subject: Re: [PATCH v4 9/9] target/arm: Enable TARGET_TB_PCREL Content-Language: en-US To: Peter Maydell Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org References: <20220906100528.343244-1-richard.henderson@linaro.org> <20220906100528.343244-10-richard.henderson@linaro.org> From: Richard Henderson In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-2.319, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 9/22/22 07:07, Peter Maydell wrote: >> + /* >> + * For TARGET_TB_PCREL, the value relative to pc_curr against which >> + * offsets must be computed for cpu_pc. -1 if unknown due to jump. >> + */ > > I'm not really sure what this comment is trying to tell me. Could > you expand it a bit ? After the effect of an indirect jump is applied, pc_save is set to -1, so that we can assert that we don't attempt to use cpu_pc again. >> void arm_cpu_synchronize_from_tb(CPUState *cs, >> const TranslationBlock *tb) >> { >> - ARMCPU *cpu = ARM_CPU(cs); >> - CPUARMState *env = &cpu->env; >> - >> - /* >> - * It's OK to look at env for the current mode here, because it's >> - * never possible for an AArch64 TB to chain to an AArch32 TB. >> - */ >> - if (is_a64(env)) { >> - env->pc = tb_pc(tb); >> - } else { >> - env->regs[15] = tb_pc(tb); >> + /* The program counter is always up to date with TARGET_TB_PCREL. */ > > Is it? At TranslationBlock boundaries, yes. > Is there some documentation in one of the other patchsets about > how TARGET_TB_PCREL works in general and what targets need to do to > support it? I tried to do so in the generic TARGET_TB_PCREL support patch. (1) PC must be up-to-date on all TB boundaries, (2) translation is given a full virtual address, for the benefit of the (nested) call to cpu_ld*_code, but should otherwise only consider the page offset portion of that address. (a) unwind info is a page offset, (1) restore_state_to_opc must use a deposit, and (2) arch_tr_insn_start must mask the translation pc. (b) pass a complete virtual address to translator_use_goto_tb, which will compare that to the translation pc to decide if we've crossed a page boundary. (3) Relative updates to PC should use runtime rather than translation time arithmetic. r~