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Fri, 08 Aug 2025 09:52:10 -0700 (PDT) Received: from [192.168.1.87] ([38.41.223.211]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-76bccfbcea9sm20908232b3a.61.2025.08.08.09.52.09 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 08 Aug 2025 09:52:09 -0700 (PDT) Message-ID: Date: Fri, 8 Aug 2025 09:52:09 -0700 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 7/9] contrib/plugins/uftrace: implement x64 support Content-Language: en-US To: Manos Pitsidianakis , qemu-devel@nongnu.org Cc: Mahmoud Mandour , =?UTF-8?Q?Philippe_Mathieu-Daud_=C3=A9?= , rowan Hart , Gustavo Romero , =?UTF-8?Q?Alex_Benn_=C3=A9_e?= , Alexandre Iooss , Peter Maydell , Richard Henderson References: <20250808020702.410109-1-pierrick.bouvier@linaro.org> <20250808020702.410109-8-pierrick.bouvier@linaro.org> From: Pierrick Bouvier In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::429; envelope-from=pierrick.bouvier@linaro.org; helo=mail-pf1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 8/8/25 2:42 AM, Manos Pitsidianakis wrote: > On Fri, 08 Aug 2025 05:07, Pierrick Bouvier wrote: >> It's trivial to implement x64 support, as it's the same stack layout >> than aarch64. > > s/than/as > >> >> Signed-off-by: Pierrick Bouvier >> --- >> contrib/plugins/uftrace.c | 85 +++++++++++++++++++++++++++++++++++++++ >> 1 file changed, 85 insertions(+) >> >> diff --git a/contrib/plugins/uftrace.c b/contrib/plugins/uftrace.c >> index 6628b4256fd..f10172eed10 100644 >> --- a/contrib/plugins/uftrace.c >> +++ b/contrib/plugins/uftrace.c >> @@ -79,6 +79,20 @@ typedef struct { >> struct qemu_plugin_register *reg_scr_el3; >> } Aarch64Cpu; >> >> +typedef enum { >> + X64_RING0, >> + X64_RING1, >> + X64_RING2, >> + X64_RING3, >> + X64_REAL_MODE, >> +} X64PrivilegeLevel; >> + >> +typedef struct { >> + struct qemu_plugin_register *reg_rbp; >> + struct qemu_plugin_register *reg_cs; >> + struct qemu_plugin_register *reg_cr0; >> +} X64Cpu; >> + >> typedef struct { >> uint64_t timestamp; >> uint64_t data; >> @@ -565,6 +579,75 @@ static CpuOps aarch64_ops = { >> .does_insn_modify_frame_pointer = aarch64_does_insn_modify_frame_pointer, >> }; >> >> +static uint8_t x64_num_privilege_levels(void) >> +{ >> + return X64_REAL_MODE + 1; >> +} >> + >> +static const char *x64_get_privilege_level_name(uint8_t pl) >> +{ >> + switch (pl) { >> + case X64_RING0: return "Ring0"; >> + case X64_RING1: return "Ring1"; >> + case X64_RING2: return "Ring2"; >> + case X64_RING3: return "Ring3"; >> + case X64_REAL_MODE: return "RealMode"; >> + default: >> + g_assert_not_reached(); >> + } >> +} >> + >> +static uint8_t x64_get_privilege_level(Cpu *cpu_) >> +{ >> + X64Cpu *cpu = cpu_->arch; >> + uint64_t cr0 = cpu_read_register64(cpu_, cpu->reg_cr0); >> + uint64_t protected_mode = (cr0 >> 0) & 0b1; >> + if (!protected_mode) { >> + return X64_REAL_MODE; >> + } >> + uint32_t cs = cpu_read_register32(cpu_, cpu->reg_cs); >> + uint32_t ring_level = (cs >> 0) & 0b11; >> + return ring_level; >> +} >> + >> +static uint64_t x64_get_frame_pointer(Cpu *cpu_) >> +{ >> + X64Cpu *cpu = cpu_->arch; >> + return cpu_read_register64(cpu_, cpu->reg_rbp); >> +} >> + >> +static void x64_init(Cpu *cpu_) >> +{ >> + X64Cpu *cpu = g_new0(X64Cpu, 1); >> + cpu_->arch = cpu; >> + cpu->reg_rbp = plugin_find_register("rbp"); >> + g_assert(cpu->reg_rbp); >> + cpu->reg_cs = plugin_find_register("cs"); >> + g_assert(cpu->reg_cs); >> + cpu->reg_cr0 = plugin_find_register("cr0"); >> + g_assert(cpu->reg_cr0); >> +} >> + >> +static void x64_end(Cpu *cpu) >> +{ >> + g_free(cpu->arch); >> +} >> + >> +static bool x64_does_insn_modify_frame_pointer(const char *disas) >> +{ >> + return strstr(disas, "rbp"); >> +} >> + >> +static CpuOps x64_ops = { >> + .init = x64_init, >> + .end = x64_end, >> + .get_frame_pointer = x64_get_frame_pointer, >> + .get_privilege_level = x64_get_privilege_level, >> + .num_privilege_levels = x64_num_privilege_levels, >> + .get_privilege_level_name = x64_get_privilege_level_name, >> + .does_insn_modify_frame_pointer = x64_does_insn_modify_frame_pointer, >> +}; >> + >> static void track_privilege_change(unsigned int cpu_index, void *udata) >> { >> Cpu *cpu = qemu_plugin_scoreboard_find(score, cpu_index); >> @@ -771,6 +854,8 @@ QEMU_PLUGIN_EXPORT int qemu_plugin_install(qemu_plugin_id_t id, >> >> if (!strcmp(info->target_name, "aarch64")) { >> arch_ops = aarch64_ops; >> + } else if (!strcmp(info->target_name, "x86_64")) { >> + arch_ops = x64_ops; >> } else { >> fprintf(stderr, "plugin uftrace: %s target is not supported\n", >> info->target_name); >> -- >> 2.47.2 >> > > No idea about x86 assembly tbh but this looks correct to me. > > Reviewed-by: Manos Pitsidianakis Funny enough, I tried to implement that for risv64 also, just to realize the utter mess this architecture did with frame pointer, hiding it on the other side of the stack frame. Thus, it's not possible to easily walk frame pointers on this arch, and you need to disassemble prologue to find how big your stack frame is. It's crazy architects didn't learn their lesson from the past issues on other arch regarding frame pointers.