From: Richard Henderson <richard.henderson@linaro.org>
To: Alistair Francis <alistair.francis@wdc.com>,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: alistair23@gmail.com, bmeng.cn@gmail.com, palmer@dabbelt.com
Subject: Re: [PATCH v1 2/5] target/riscv: Use the RiscVException enum for CSR predicates
Date: Wed, 17 Mar 2021 13:44:03 -0600 [thread overview]
Message-ID: <db7bdc63-2c9b-40fc-f36c-230d32810970@linaro.org> (raw)
In-Reply-To: <9c0fa7d4f191d83ac2e70e830d141f4f4105e061.1616002766.git.alistair.francis@wdc.com>
On 3/17/21 11:39 AM, Alistair Francis wrote:
> @@ -1312,8 +1320,8 @@ int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
> return -RISCV_EXCP_ILLEGAL_INST;
> }
> ret = csr_ops[csrno].predicate(env, csrno);
> - if (ret < 0) {
> - return ret;
> + if (ret > 0) {
> + return -ret;
> }
I think you want
if (ret != RISCV_EXCP_NONE) {
return -ret;
}
here. But of course this outer interface is still confused until patches 4+5.
So perhaps it doesn't matter.
r~
next prev parent reply other threads:[~2021-03-17 19:45 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-17 17:39 [PATCH v1 0/5] RISC-V: Convert the CSR access functions to use Alistair Francis
2021-03-17 17:39 ` [PATCH v1 1/5] target/riscv: Convert the RISC-V exceptions to an enum Alistair Francis
2021-03-18 1:58 ` Bin Meng
2021-03-19 13:19 ` Alistair Francis
2021-03-17 17:39 ` [PATCH v1 2/5] target/riscv: Use the RiscVException enum for CSR predicates Alistair Francis
2021-03-17 19:44 ` Richard Henderson [this message]
2021-03-19 13:17 ` Alistair Francis
2021-03-17 17:39 ` [PATCH v1 3/5] target/riscv: Fix 32-bit HS mode access permissions Alistair Francis
2021-03-17 17:39 ` [PATCH v1 4/5] target/riscv: Use the RiscVException enum for CSR operations Alistair Francis
2021-03-17 17:40 ` [PATCH v1 5/5] target/riscv: Use RiscVException enum for CSR access Alistair Francis
2021-03-18 13:25 ` Richard Henderson
2021-03-19 13:19 ` Alistair Francis
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