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[216.71.219.44]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-29ee9d397b2sm33341725ad.41.2025.12.11.14.12.54 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 11 Dec 2025 14:12:54 -0800 (PST) Content-Type: multipart/mixed; boundary="------------xZGNGqi6EYefL7Xf0V2J4q0Y" Message-ID: Date: Thu, 11 Dec 2025 14:12:53 -0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [RFC v3 08/21] hw/arm/smmuv3: Add separate address space for secure SMMU accesses Content-Language: en-US To: Tao Tang , Eric Auger , Peter Maydell Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org, Chen Baozi , =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= , Jean-Philippe Brucker , Mostafa Saleh , Richard Henderson , =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= References: <20251012150701.4127034-1-tangtao1634@phytium.com.cn> <20251012150701.4127034-9-tangtao1634@phytium.com.cn> From: Pierrick Bouvier In-Reply-To: <20251012150701.4127034-9-tangtao1634@phytium.com.cn> Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=pierrick.bouvier@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org This is a multi-part message in MIME format. --------------xZGNGqi6EYefL7Xf0V2J4q0Y Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Hi Tao, On 10/12/25 8:06 AM, Tao Tang wrote: > According to the Arm architecture, SMMU-originated memory accesses, > such as fetching commands or writing events for a secure stream, must > target the Secure Physical Address (PA) space. The existing model sends > all DMA to the global non-secure address_space_memory. > > This patch introduces the infrastructure to differentiate between secure > and non-secure memory accesses. Firstly, SMMU_SEC_SID_S is added in > SMMUSecSID enum to represent the secure context. Then a weak global > symbol, arm_secure_address_space, is added, which can be provided by the > machine model to represent the Secure PA space. > > A new helper, smmu_get_address_space(), selects the target address > space based on SEC_SID. All internal DMA calls > (dma_memory_read/write) will be updated to use this helper in follow-up > patches. > > Signed-off-by: Tao Tang > --- > hw/arm/smmu-common.c | 8 ++++++++ > hw/arm/virt.c | 5 +++++ > include/hw/arm/smmu-common.h | 27 +++++++++++++++++++++++++++ > 3 files changed, 40 insertions(+) > > diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c > index 62a7612184..24db448683 100644 > --- a/hw/arm/smmu-common.c > +++ b/hw/arm/smmu-common.c > @@ -30,6 +30,14 @@ > #include "hw/arm/smmu-common.h" > #include "smmu-internal.h" > > +/* Global state for secure address space availability */ > +bool arm_secure_as_available; > + > +void smmu_enable_secure_address_space(void) > +{ > + arm_secure_as_available = true; > +} > + > /* IOTLB Management */ > > static guint smmu_iotlb_key_hash(gconstpointer v) > diff --git a/hw/arm/virt.c b/hw/arm/virt.c > index 175023897a..83dc62a095 100644 > --- a/hw/arm/virt.c > +++ b/hw/arm/virt.c > @@ -92,6 +92,8 @@ > #include "hw/cxl/cxl_host.h" > #include "qemu/guest-random.h" > > +AddressSpace arm_secure_address_space; > + > static GlobalProperty arm_virt_compat[] = { > { TYPE_VIRTIO_IOMMU_PCI, "aw-bits", "48" }, > }; > @@ -2257,6 +2259,9 @@ static void machvirt_init(MachineState *machine) > memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory", > UINT64_MAX); > memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1); > + address_space_init(&arm_secure_address_space, secure_sysmem, > + "secure-memory-space"); > + smmu_enable_secure_address_space(); > } > > firmware_loaded = virt_firmware_init(vms, sysmem, > diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h > index b0dae18a62..d54558f94b 100644 > --- a/include/hw/arm/smmu-common.h > +++ b/include/hw/arm/smmu-common.h > @@ -43,9 +43,36 @@ > /* StreamID Security state */ > typedef enum SMMUSecSID { > SMMU_SEC_SID_NS = 0, > + SMMU_SEC_SID_S, > SMMU_SEC_SID_NUM, > } SMMUSecSID; > > +extern AddressSpace __attribute__((weak)) arm_secure_address_space; > +extern bool arm_secure_as_available; > +void smmu_enable_secure_address_space(void); > + > +/* > + * Return the address space corresponding to the SEC_SID. > + * If SEC_SID is Secure, but secure address space is not available, > + * return NULL and print a warning message. > + */ > +static inline AddressSpace *smmu_get_address_space(SMMUSecSID sec_sid) > +{ > + switch (sec_sid) { > + case SMMU_SEC_SID_NS: > + return &address_space_memory; > + case SMMU_SEC_SID_S: > + if (!arm_secure_as_available || arm_secure_address_space.root == NULL) { > + printf("Secure address space requested but not available"); > + return NULL; > + } > + return &arm_secure_address_space; > + default: > + printf("Unknown SEC_SID value %d", sec_sid); > + return NULL; > + } > +} > + > /* > * Page table walk error types > */ I ran into the same issue, when adding Granule Protection Check to the SMMU, for RME support. It requires access to secure memory, where Granule Protection Table is kept, and thus, access secure address space. After talking with Richard and Philippe, I have been suggested a better way. Similar to how arm cpus handle this, boards (virt & sbsa-ref) are simply passing pointers to MemoryRegion for global and secure memory. Then, the SMMU can create its own address spaces, based on those regions. It's clean, does not require any weak variable, and mimic what is already done for cpus. Please see the two patches attached. First one define properties, and pass memory regions from boards to SMMU. Second one replace global address spaces with SMMU ones. I'll send patch 1 as it's own series, and you can take inspiration from patch 2 for this series. SMMU unit tests will need to be modified to be passed the memory regions also. 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