From: Richard Henderson <richard.henderson@linaro.org>
To: LIU Zhiwei <zhiwei_liu@c-sky.com>,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: palmer@dabbelt.com, wenmeng_zhang@c-sky.com,
Alistair.Francis@wdc.com, wxy194768@alibaba-inc.com
Subject: Re: [PATCH 1/2] tcg/tcg-op: Fix nonatomic_op load with MO_SIGN
Date: Tue, 30 Jun 2020 07:56:10 -0700 [thread overview]
Message-ID: <db9e632e-4fcc-2374-590f-4ea35d1adda6@linaro.org> (raw)
In-Reply-To: <20200629130731.1080-2-zhiwei_liu@c-sky.com>
On 6/29/20 6:07 AM, LIU Zhiwei wrote:
> @@ -3189,7 +3189,7 @@ static void do_nonatomic_op_i32(TCGv_i32 ret, TCGv addr, TCGv_i32 val,
>
> memop = tcg_canonicalize_memop(memop, 0, 0);
>
> - tcg_gen_qemu_ld_i32(t1, addr, idx, memop & ~MO_SIGN);
> + tcg_gen_qemu_ld_i32(t1, addr, idx, memop);
> gen(t2, t1, val);
> tcg_gen_qemu_st_i32(t2, addr, idx, memop);
>
> @@ -3232,7 +3232,7 @@ static void do_nonatomic_op_i64(TCGv_i64 ret, TCGv addr, TCGv_i64 val,
>
> memop = tcg_canonicalize_memop(memop, 1, 0);
>
> - tcg_gen_qemu_ld_i64(t1, addr, idx, memop & ~MO_SIGN);
> + tcg_gen_qemu_ld_i64(t1, addr, idx, memop);
> gen(t2, t1, val);
> tcg_gen_qemu_st_i64(t2, addr, idx, memop);
This is insufficient for smin/smax -- we also need to extend the "val" input.
r~
next prev parent reply other threads:[~2020-06-30 14:57 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-29 13:07 [PATCH 0/2] target/riscv: fixup atomic implementation LIU Zhiwei
2020-06-29 13:07 ` [PATCH 1/2] tcg/tcg-op: Fix nonatomic_op load with MO_SIGN LIU Zhiwei
2020-06-30 14:56 ` Richard Henderson [this message]
2020-06-30 15:22 ` LIU Zhiwei
2020-06-29 13:07 ` [PATCH 2/2] target/riscv: Do amo*.w insns operate with 32 bits LIU Zhiwei
2020-06-30 15:00 ` Richard Henderson
2020-06-30 15:38 ` LIU Zhiwei
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