* [PATCH v2 1/5] hw/arm/aspeed: Remove dead code
2024-01-23 22:48 [PATCH v2 0/5] hw/arm/aspeed: Check for CPU types in machine_run_board_init() Philippe Mathieu-Daudé
@ 2024-01-23 22:48 ` Philippe Mathieu-Daudé
2024-01-24 6:50 ` Cédric Le Goater
` (2 more replies)
2024-01-23 22:48 ` [PATCH v2 2/5] hw/arm/aspeed: Set default CPU count using aspeed_soc_num_cpus() Philippe Mathieu-Daudé
` (4 subsequent siblings)
5 siblings, 3 replies; 22+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-01-23 22:48 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, qemu-arm, Joel Stanley, Andrew Jeffery,
Cédric Le Goater, Philippe Mathieu-Daudé
Remove copy/paste typo from commit 6c323aba40 ("hw/arm/aspeed:
Adding new machine Tiogapass in QEMU").
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
hw/arm/aspeed.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index cc59176563..4bc292ff84 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -1301,7 +1301,6 @@ static void aspeed_machine_tiogapass_class_init(ObjectClass *oc, void *data)
mc->default_ram_size = 1 * GiB;
mc->default_cpus = mc->min_cpus = mc->max_cpus =
aspeed_soc_num_cpus(amc->soc_name);
- aspeed_soc_num_cpus(amc->soc_name);
};
static void aspeed_machine_sonorapass_class_init(ObjectClass *oc, void *data)
--
2.41.0
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH v2 1/5] hw/arm/aspeed: Remove dead code
2024-01-23 22:48 ` [PATCH v2 1/5] hw/arm/aspeed: Remove dead code Philippe Mathieu-Daudé
@ 2024-01-24 6:50 ` Cédric Le Goater
2024-01-24 23:12 ` Richard Henderson
2024-01-25 2:21 ` Gavin Shan
2 siblings, 0 replies; 22+ messages in thread
From: Cédric Le Goater @ 2024-01-24 6:50 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Peter Maydell, qemu-arm, Joel Stanley, Andrew Jeffery
On 1/23/24 23:48, Philippe Mathieu-Daudé wrote:
> Remove copy/paste typo from commit 6c323aba40 ("hw/arm/aspeed:
> Adding new machine Tiogapass in QEMU").
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Thanks,
C.
> ---
> hw/arm/aspeed.c | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
> index cc59176563..4bc292ff84 100644
> --- a/hw/arm/aspeed.c
> +++ b/hw/arm/aspeed.c
> @@ -1301,7 +1301,6 @@ static void aspeed_machine_tiogapass_class_init(ObjectClass *oc, void *data)
> mc->default_ram_size = 1 * GiB;
> mc->default_cpus = mc->min_cpus = mc->max_cpus =
> aspeed_soc_num_cpus(amc->soc_name);
> - aspeed_soc_num_cpus(amc->soc_name);
> };
>
> static void aspeed_machine_sonorapass_class_init(ObjectClass *oc, void *data)
^ permalink raw reply [flat|nested] 22+ messages in thread* Re: [PATCH v2 1/5] hw/arm/aspeed: Remove dead code
2024-01-23 22:48 ` [PATCH v2 1/5] hw/arm/aspeed: Remove dead code Philippe Mathieu-Daudé
2024-01-24 6:50 ` Cédric Le Goater
@ 2024-01-24 23:12 ` Richard Henderson
2024-01-25 2:21 ` Gavin Shan
2 siblings, 0 replies; 22+ messages in thread
From: Richard Henderson @ 2024-01-24 23:12 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Peter Maydell, qemu-arm, Joel Stanley, Andrew Jeffery,
Cédric Le Goater
On 1/24/24 08:48, Philippe Mathieu-Daudé wrote:
> Remove copy/paste typo from commit 6c323aba40 ("hw/arm/aspeed:
> Adding new machine Tiogapass in QEMU").
>
> Signed-off-by: Philippe Mathieu-Daudé<philmd@linaro.org>
> ---
> hw/arm/aspeed.c | 1 -
> 1 file changed, 1 deletion(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 22+ messages in thread* Re: [PATCH v2 1/5] hw/arm/aspeed: Remove dead code
2024-01-23 22:48 ` [PATCH v2 1/5] hw/arm/aspeed: Remove dead code Philippe Mathieu-Daudé
2024-01-24 6:50 ` Cédric Le Goater
2024-01-24 23:12 ` Richard Henderson
@ 2024-01-25 2:21 ` Gavin Shan
2 siblings, 0 replies; 22+ messages in thread
From: Gavin Shan @ 2024-01-25 2:21 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Peter Maydell, qemu-arm, Joel Stanley, Andrew Jeffery,
Cédric Le Goater
On 1/24/24 08:48, Philippe Mathieu-Daudé wrote:
> Remove copy/paste typo from commit 6c323aba40 ("hw/arm/aspeed:
> Adding new machine Tiogapass in QEMU").
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
> hw/arm/aspeed.c | 1 -
> 1 file changed, 1 deletion(-)
>
Reviewed-by: Gavin Shan <gshan@redhat.com>
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH v2 2/5] hw/arm/aspeed: Set default CPU count using aspeed_soc_num_cpus()
2024-01-23 22:48 [PATCH v2 0/5] hw/arm/aspeed: Check for CPU types in machine_run_board_init() Philippe Mathieu-Daudé
2024-01-23 22:48 ` [PATCH v2 1/5] hw/arm/aspeed: Remove dead code Philippe Mathieu-Daudé
@ 2024-01-23 22:48 ` Philippe Mathieu-Daudé
2024-01-24 6:52 ` Cédric Le Goater
2024-01-25 2:23 ` Gavin Shan
2024-01-23 22:48 ` [PATCH v2 3/5] hw/arm/aspeed: Init CPU defaults in a common helper Philippe Mathieu-Daudé
` (3 subsequent siblings)
5 siblings, 2 replies; 22+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-01-23 22:48 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, qemu-arm, Joel Stanley, Andrew Jeffery,
Cédric Le Goater, Philippe Mathieu-Daudé
Since commit b7f1a0cb76 ("arm/aspeed: Compute the number
of CPUs from the SoC definition") Aspeed machines use the
aspeed_soc_num_cpus() helper to set the number of CPUs.
Use it for the ast1030-evb (commit 356b230ed1 "aspeed/soc:
Add AST1030 support") and supermicrox11-bmc (commit 40a38df55e
"hw/arm/aspeed: Add board model for Supermicro X11 BMC") machines.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
hw/arm/aspeed.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index 4bc292ff84..5b01a4dd28 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -1212,6 +1212,8 @@ static void aspeed_machine_supermicrox11_bmc_class_init(ObjectClass *oc,
amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
amc->i2c_init = palmetto_bmc_i2c_init;
mc->default_ram_size = 256 * MiB;
+ mc->default_cpus = mc->min_cpus = mc->max_cpus =
+ aspeed_soc_num_cpus(amc->soc_name);
}
static void aspeed_machine_supermicro_x11spi_bmc_class_init(ObjectClass *oc,
@@ -1586,11 +1588,12 @@ static void aspeed_minibmc_machine_ast1030_evb_class_init(ObjectClass *oc,
mc->init = aspeed_minibmc_machine_init;
amc->i2c_init = ast1030_evb_i2c_init;
mc->default_ram_size = 0;
- mc->default_cpus = mc->min_cpus = mc->max_cpus = 1;
amc->fmc_model = "sst25vf032b";
amc->spi_model = "sst25vf032b";
amc->num_cs = 2;
amc->macs_mask = 0;
+ mc->default_cpus = mc->min_cpus = mc->max_cpus =
+ aspeed_soc_num_cpus(amc->soc_name);
}
static void aspeed_machine_qcom_dc_scm_v1_class_init(ObjectClass *oc,
--
2.41.0
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH v2 2/5] hw/arm/aspeed: Set default CPU count using aspeed_soc_num_cpus()
2024-01-23 22:48 ` [PATCH v2 2/5] hw/arm/aspeed: Set default CPU count using aspeed_soc_num_cpus() Philippe Mathieu-Daudé
@ 2024-01-24 6:52 ` Cédric Le Goater
2024-01-25 2:23 ` Gavin Shan
1 sibling, 0 replies; 22+ messages in thread
From: Cédric Le Goater @ 2024-01-24 6:52 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Peter Maydell, qemu-arm, Joel Stanley, Andrew Jeffery
On 1/23/24 23:48, Philippe Mathieu-Daudé wrote:
> Since commit b7f1a0cb76 ("arm/aspeed: Compute the number
> of CPUs from the SoC definition") Aspeed machines use the
> aspeed_soc_num_cpus() helper to set the number of CPUs.
>
> Use it for the ast1030-evb (commit 356b230ed1 "aspeed/soc:
> Add AST1030 support") and supermicrox11-bmc (commit 40a38df55e
> "hw/arm/aspeed: Add board model for Supermicro X11 BMC") machines.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Thanks,
C.
> ---
> hw/arm/aspeed.c | 5 ++++-
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
> index 4bc292ff84..5b01a4dd28 100644
> --- a/hw/arm/aspeed.c
> +++ b/hw/arm/aspeed.c
> @@ -1212,6 +1212,8 @@ static void aspeed_machine_supermicrox11_bmc_class_init(ObjectClass *oc,
> amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
> amc->i2c_init = palmetto_bmc_i2c_init;
> mc->default_ram_size = 256 * MiB;
> + mc->default_cpus = mc->min_cpus = mc->max_cpus =
> + aspeed_soc_num_cpus(amc->soc_name);
> }
>
> static void aspeed_machine_supermicro_x11spi_bmc_class_init(ObjectClass *oc,
> @@ -1586,11 +1588,12 @@ static void aspeed_minibmc_machine_ast1030_evb_class_init(ObjectClass *oc,
> mc->init = aspeed_minibmc_machine_init;
> amc->i2c_init = ast1030_evb_i2c_init;
> mc->default_ram_size = 0;
> - mc->default_cpus = mc->min_cpus = mc->max_cpus = 1;
> amc->fmc_model = "sst25vf032b";
> amc->spi_model = "sst25vf032b";
> amc->num_cs = 2;
> amc->macs_mask = 0;
> + mc->default_cpus = mc->min_cpus = mc->max_cpus =
> + aspeed_soc_num_cpus(amc->soc_name);
> }
>
> static void aspeed_machine_qcom_dc_scm_v1_class_init(ObjectClass *oc,
^ permalink raw reply [flat|nested] 22+ messages in thread* Re: [PATCH v2 2/5] hw/arm/aspeed: Set default CPU count using aspeed_soc_num_cpus()
2024-01-23 22:48 ` [PATCH v2 2/5] hw/arm/aspeed: Set default CPU count using aspeed_soc_num_cpus() Philippe Mathieu-Daudé
2024-01-24 6:52 ` Cédric Le Goater
@ 2024-01-25 2:23 ` Gavin Shan
1 sibling, 0 replies; 22+ messages in thread
From: Gavin Shan @ 2024-01-25 2:23 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Peter Maydell, qemu-arm, Joel Stanley, Andrew Jeffery,
Cédric Le Goater
On 1/24/24 08:48, Philippe Mathieu-Daudé wrote:
> Since commit b7f1a0cb76 ("arm/aspeed: Compute the number
> of CPUs from the SoC definition") Aspeed machines use the
> aspeed_soc_num_cpus() helper to set the number of CPUs.
>
> Use it for the ast1030-evb (commit 356b230ed1 "aspeed/soc:
> Add AST1030 support") and supermicrox11-bmc (commit 40a38df55e
> "hw/arm/aspeed: Add board model for Supermicro X11 BMC") machines.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
> hw/arm/aspeed.c | 5 ++++-
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
Reviewed-by: Gavin Shan <gshan@redhat.com>
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH v2 3/5] hw/arm/aspeed: Init CPU defaults in a common helper
2024-01-23 22:48 [PATCH v2 0/5] hw/arm/aspeed: Check for CPU types in machine_run_board_init() Philippe Mathieu-Daudé
2024-01-23 22:48 ` [PATCH v2 1/5] hw/arm/aspeed: Remove dead code Philippe Mathieu-Daudé
2024-01-23 22:48 ` [PATCH v2 2/5] hw/arm/aspeed: Set default CPU count using aspeed_soc_num_cpus() Philippe Mathieu-Daudé
@ 2024-01-23 22:48 ` Philippe Mathieu-Daudé
2024-01-24 6:58 ` Cédric Le Goater
` (2 more replies)
2024-01-23 22:48 ` [PATCH v2 4/5] hw/arm/aspeed: Introduce aspeed_soc_cpu_type() helper Philippe Mathieu-Daudé
` (2 subsequent siblings)
5 siblings, 3 replies; 22+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-01-23 22:48 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, qemu-arm, Joel Stanley, Andrew Jeffery,
Cédric Le Goater, Philippe Mathieu-Daudé
Rework aspeed_soc_num_cpus() as a new init_cpus_defaults()
helper to reduce code duplication.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
hw/arm/aspeed.c | 71 +++++++++++++++++++------------------------------
1 file changed, 28 insertions(+), 43 deletions(-)
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index 5b01a4dd28..636a6269aa 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -1141,10 +1141,14 @@ static void aspeed_machine_class_props_init(ObjectClass *oc)
"Change the SPI Flash model");
}
-static int aspeed_soc_num_cpus(const char *soc_name)
+static void aspeed_machine_class_init_cpus_defaults(MachineClass *mc)
{
- AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(soc_name));
- return sc->num_cpus;
+ AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(mc);
+ AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(amc->soc_name));
+
+ mc->default_cpus = mc->min_cpus
+ = mc->max_cpus
+ = sc->num_cpus;
}
static void aspeed_machine_class_init(ObjectClass *oc, void *data)
@@ -1176,8 +1180,7 @@ static void aspeed_machine_palmetto_class_init(ObjectClass *oc, void *data)
amc->num_cs = 1;
amc->i2c_init = palmetto_bmc_i2c_init;
mc->default_ram_size = 256 * MiB;
- mc->default_cpus = mc->min_cpus = mc->max_cpus =
- aspeed_soc_num_cpus(amc->soc_name);
+ aspeed_machine_class_init_cpus_defaults(mc);
};
static void aspeed_machine_quanta_q71l_class_init(ObjectClass *oc, void *data)
@@ -1193,8 +1196,7 @@ static void aspeed_machine_quanta_q71l_class_init(ObjectClass *oc, void *data)
amc->num_cs = 1;
amc->i2c_init = quanta_q71l_bmc_i2c_init;
mc->default_ram_size = 128 * MiB;
- mc->default_cpus = mc->min_cpus = mc->max_cpus =
- aspeed_soc_num_cpus(amc->soc_name);
+ aspeed_machine_class_init_cpus_defaults(mc);
}
static void aspeed_machine_supermicrox11_bmc_class_init(ObjectClass *oc,
@@ -1212,8 +1214,7 @@ static void aspeed_machine_supermicrox11_bmc_class_init(ObjectClass *oc,
amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
amc->i2c_init = palmetto_bmc_i2c_init;
mc->default_ram_size = 256 * MiB;
- mc->default_cpus = mc->min_cpus = mc->max_cpus =
- aspeed_soc_num_cpus(amc->soc_name);
+ aspeed_machine_class_init_cpus_defaults(mc);
}
static void aspeed_machine_supermicro_x11spi_bmc_class_init(ObjectClass *oc,
@@ -1231,8 +1232,7 @@ static void aspeed_machine_supermicro_x11spi_bmc_class_init(ObjectClass *oc,
amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
amc->i2c_init = palmetto_bmc_i2c_init;
mc->default_ram_size = 512 * MiB;
- mc->default_cpus = mc->min_cpus = mc->max_cpus =
- aspeed_soc_num_cpus(amc->soc_name);
+ aspeed_machine_class_init_cpus_defaults(mc);
}
static void aspeed_machine_ast2500_evb_class_init(ObjectClass *oc, void *data)
@@ -1248,8 +1248,7 @@ static void aspeed_machine_ast2500_evb_class_init(ObjectClass *oc, void *data)
amc->num_cs = 1;
amc->i2c_init = ast2500_evb_i2c_init;
mc->default_ram_size = 512 * MiB;
- mc->default_cpus = mc->min_cpus = mc->max_cpus =
- aspeed_soc_num_cpus(amc->soc_name);
+ aspeed_machine_class_init_cpus_defaults(mc);
};
static void aspeed_machine_yosemitev2_class_init(ObjectClass *oc, void *data)
@@ -1266,8 +1265,7 @@ static void aspeed_machine_yosemitev2_class_init(ObjectClass *oc, void *data)
amc->num_cs = 2;
amc->i2c_init = yosemitev2_bmc_i2c_init;
mc->default_ram_size = 512 * MiB;
- mc->default_cpus = mc->min_cpus = mc->max_cpus =
- aspeed_soc_num_cpus(amc->soc_name);
+ aspeed_machine_class_init_cpus_defaults(mc);
};
static void aspeed_machine_romulus_class_init(ObjectClass *oc, void *data)
@@ -1283,8 +1281,7 @@ static void aspeed_machine_romulus_class_init(ObjectClass *oc, void *data)
amc->num_cs = 2;
amc->i2c_init = romulus_bmc_i2c_init;
mc->default_ram_size = 512 * MiB;
- mc->default_cpus = mc->min_cpus = mc->max_cpus =
- aspeed_soc_num_cpus(amc->soc_name);
+ aspeed_machine_class_init_cpus_defaults(mc);
};
static void aspeed_machine_tiogapass_class_init(ObjectClass *oc, void *data)
@@ -1301,8 +1298,7 @@ static void aspeed_machine_tiogapass_class_init(ObjectClass *oc, void *data)
amc->num_cs = 2;
amc->i2c_init = tiogapass_bmc_i2c_init;
mc->default_ram_size = 1 * GiB;
- mc->default_cpus = mc->min_cpus = mc->max_cpus =
- aspeed_soc_num_cpus(amc->soc_name);
+ aspeed_machine_class_init_cpus_defaults(mc);
};
static void aspeed_machine_sonorapass_class_init(ObjectClass *oc, void *data)
@@ -1318,8 +1314,7 @@ static void aspeed_machine_sonorapass_class_init(ObjectClass *oc, void *data)
amc->num_cs = 2;
amc->i2c_init = sonorapass_bmc_i2c_init;
mc->default_ram_size = 512 * MiB;
- mc->default_cpus = mc->min_cpus = mc->max_cpus =
- aspeed_soc_num_cpus(amc->soc_name);
+ aspeed_machine_class_init_cpus_defaults(mc);
};
static void aspeed_machine_witherspoon_class_init(ObjectClass *oc, void *data)
@@ -1335,8 +1330,7 @@ static void aspeed_machine_witherspoon_class_init(ObjectClass *oc, void *data)
amc->num_cs = 2;
amc->i2c_init = witherspoon_bmc_i2c_init;
mc->default_ram_size = 512 * MiB;
- mc->default_cpus = mc->min_cpus = mc->max_cpus =
- aspeed_soc_num_cpus(amc->soc_name);
+ aspeed_machine_class_init_cpus_defaults(mc);
};
static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, void *data)
@@ -1355,8 +1349,7 @@ static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, void *data)
ASPEED_MAC3_ON;
amc->i2c_init = ast2600_evb_i2c_init;
mc->default_ram_size = 1 * GiB;
- mc->default_cpus = mc->min_cpus = mc->max_cpus =
- aspeed_soc_num_cpus(amc->soc_name);
+ aspeed_machine_class_init_cpus_defaults(mc);
};
static void aspeed_machine_tacoma_class_init(ObjectClass *oc, void *data)
@@ -1374,8 +1367,7 @@ static void aspeed_machine_tacoma_class_init(ObjectClass *oc, void *data)
amc->macs_mask = ASPEED_MAC2_ON;
amc->i2c_init = witherspoon_bmc_i2c_init; /* Same board layout */
mc->default_ram_size = 1 * GiB;
- mc->default_cpus = mc->min_cpus = mc->max_cpus =
- aspeed_soc_num_cpus(amc->soc_name);
+ aspeed_machine_class_init_cpus_defaults(mc);
};
static void aspeed_machine_g220a_class_init(ObjectClass *oc, void *data)
@@ -1392,8 +1384,7 @@ static void aspeed_machine_g220a_class_init(ObjectClass *oc, void *data)
amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
amc->i2c_init = g220a_bmc_i2c_init;
mc->default_ram_size = 1024 * MiB;
- mc->default_cpus = mc->min_cpus = mc->max_cpus =
- aspeed_soc_num_cpus(amc->soc_name);
+ aspeed_machine_class_init_cpus_defaults(mc);
};
static void aspeed_machine_fp5280g2_class_init(ObjectClass *oc, void *data)
@@ -1410,8 +1401,7 @@ static void aspeed_machine_fp5280g2_class_init(ObjectClass *oc, void *data)
amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
amc->i2c_init = fp5280g2_bmc_i2c_init;
mc->default_ram_size = 512 * MiB;
- mc->default_cpus = mc->min_cpus = mc->max_cpus =
- aspeed_soc_num_cpus(amc->soc_name);
+ aspeed_machine_class_init_cpus_defaults(mc);
};
static void aspeed_machine_rainier_class_init(ObjectClass *oc, void *data)
@@ -1429,8 +1419,7 @@ static void aspeed_machine_rainier_class_init(ObjectClass *oc, void *data)
amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON;
amc->i2c_init = rainier_bmc_i2c_init;
mc->default_ram_size = 1 * GiB;
- mc->default_cpus = mc->min_cpus = mc->max_cpus =
- aspeed_soc_num_cpus(amc->soc_name);
+ aspeed_machine_class_init_cpus_defaults(mc);
};
#define FUJI_BMC_RAM_SIZE ASPEED_RAM_SIZE(2 * GiB)
@@ -1451,8 +1440,7 @@ static void aspeed_machine_fuji_class_init(ObjectClass *oc, void *data)
amc->i2c_init = fuji_bmc_i2c_init;
amc->uart_default = ASPEED_DEV_UART1;
mc->default_ram_size = FUJI_BMC_RAM_SIZE;
- mc->default_cpus = mc->min_cpus = mc->max_cpus =
- aspeed_soc_num_cpus(amc->soc_name);
+ aspeed_machine_class_init_cpus_defaults(mc);
};
#define BLETCHLEY_BMC_RAM_SIZE ASPEED_RAM_SIZE(2 * GiB)
@@ -1472,8 +1460,7 @@ static void aspeed_machine_bletchley_class_init(ObjectClass *oc, void *data)
amc->macs_mask = ASPEED_MAC2_ON;
amc->i2c_init = bletchley_bmc_i2c_init;
mc->default_ram_size = BLETCHLEY_BMC_RAM_SIZE;
- mc->default_cpus = mc->min_cpus = mc->max_cpus =
- aspeed_soc_num_cpus(amc->soc_name);
+ aspeed_machine_class_init_cpus_defaults(mc);
}
static void fby35_reset(MachineState *state, ShutdownCause reason)
@@ -1515,6 +1502,7 @@ static void aspeed_machine_fby35_class_init(ObjectClass *oc, void *data)
amc->i2c_init = fby35_i2c_init;
/* FIXME: Replace this macro with something more general */
mc->default_ram_size = FUJI_BMC_RAM_SIZE;
+ aspeed_machine_class_init_cpus_defaults(mc); //
}
#define AST1030_INTERNAL_FLASH_SIZE (1024 * 1024)
@@ -1592,8 +1580,7 @@ static void aspeed_minibmc_machine_ast1030_evb_class_init(ObjectClass *oc,
amc->spi_model = "sst25vf032b";
amc->num_cs = 2;
amc->macs_mask = 0;
- mc->default_cpus = mc->min_cpus = mc->max_cpus =
- aspeed_soc_num_cpus(amc->soc_name);
+ aspeed_machine_class_init_cpus_defaults(mc);
}
static void aspeed_machine_qcom_dc_scm_v1_class_init(ObjectClass *oc,
@@ -1612,8 +1599,7 @@ static void aspeed_machine_qcom_dc_scm_v1_class_init(ObjectClass *oc,
amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON;
amc->i2c_init = qcom_dc_scm_bmc_i2c_init;
mc->default_ram_size = 1 * GiB;
- mc->default_cpus = mc->min_cpus = mc->max_cpus =
- aspeed_soc_num_cpus(amc->soc_name);
+ aspeed_machine_class_init_cpus_defaults(mc);
};
static void aspeed_machine_qcom_firework_class_init(ObjectClass *oc,
@@ -1632,8 +1618,7 @@ static void aspeed_machine_qcom_firework_class_init(ObjectClass *oc,
amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON;
amc->i2c_init = qcom_dc_scm_firework_i2c_init;
mc->default_ram_size = 1 * GiB;
- mc->default_cpus = mc->min_cpus = mc->max_cpus =
- aspeed_soc_num_cpus(amc->soc_name);
+ aspeed_machine_class_init_cpus_defaults(mc);
};
static const TypeInfo aspeed_machine_types[] = {
--
2.41.0
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH v2 3/5] hw/arm/aspeed: Init CPU defaults in a common helper
2024-01-23 22:48 ` [PATCH v2 3/5] hw/arm/aspeed: Init CPU defaults in a common helper Philippe Mathieu-Daudé
@ 2024-01-24 6:58 ` Cédric Le Goater
2024-01-24 23:15 ` Richard Henderson
2024-01-25 2:26 ` Gavin Shan
2 siblings, 0 replies; 22+ messages in thread
From: Cédric Le Goater @ 2024-01-24 6:58 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Peter Maydell, qemu-arm, Joel Stanley, Andrew Jeffery
On 1/23/24 23:48, Philippe Mathieu-Daudé wrote:
> Rework aspeed_soc_num_cpus() as a new init_cpus_defaults()
> helper to reduce code duplication.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
> hw/arm/aspeed.c | 71 +++++++++++++++++++------------------------------
> 1 file changed, 28 insertions(+), 43 deletions(-)
>
> diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
> index 5b01a4dd28..636a6269aa 100644
> --- a/hw/arm/aspeed.c
> +++ b/hw/arm/aspeed.c
> @@ -1141,10 +1141,14 @@ static void aspeed_machine_class_props_init(ObjectClass *oc)
> "Change the SPI Flash model");
> }
>
> -static int aspeed_soc_num_cpus(const char *soc_name)
> +static void aspeed_machine_class_init_cpus_defaults(MachineClass *mc)
>
> {
> - AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(soc_name));
> - return sc->num_cpus;
> + AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(mc);
> + AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(amc->soc_name));
> +
> + mc->default_cpus = mc->min_cpus
> + = mc->max_cpus
> + = sc->num_cpus;
> }
>
> static void aspeed_machine_class_init(ObjectClass *oc, void *data)
> @@ -1176,8 +1180,7 @@ static void aspeed_machine_palmetto_class_init(ObjectClass *oc, void *data)
> amc->num_cs = 1;
> amc->i2c_init = palmetto_bmc_i2c_init;
> mc->default_ram_size = 256 * MiB;
> - mc->default_cpus = mc->min_cpus = mc->max_cpus =
> - aspeed_soc_num_cpus(amc->soc_name);
> + aspeed_machine_class_init_cpus_defaults(mc);
> };
>
> static void aspeed_machine_quanta_q71l_class_init(ObjectClass *oc, void *data)
> @@ -1193,8 +1196,7 @@ static void aspeed_machine_quanta_q71l_class_init(ObjectClass *oc, void *data)
> amc->num_cs = 1;
> amc->i2c_init = quanta_q71l_bmc_i2c_init;
> mc->default_ram_size = 128 * MiB;
> - mc->default_cpus = mc->min_cpus = mc->max_cpus =
> - aspeed_soc_num_cpus(amc->soc_name);
> + aspeed_machine_class_init_cpus_defaults(mc);
> }
>
> static void aspeed_machine_supermicrox11_bmc_class_init(ObjectClass *oc,
> @@ -1212,8 +1214,7 @@ static void aspeed_machine_supermicrox11_bmc_class_init(ObjectClass *oc,
> amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
> amc->i2c_init = palmetto_bmc_i2c_init;
> mc->default_ram_size = 256 * MiB;
> - mc->default_cpus = mc->min_cpus = mc->max_cpus =
> - aspeed_soc_num_cpus(amc->soc_name);
> + aspeed_machine_class_init_cpus_defaults(mc);
> }
>
> static void aspeed_machine_supermicro_x11spi_bmc_class_init(ObjectClass *oc,
> @@ -1231,8 +1232,7 @@ static void aspeed_machine_supermicro_x11spi_bmc_class_init(ObjectClass *oc,
> amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
> amc->i2c_init = palmetto_bmc_i2c_init;
> mc->default_ram_size = 512 * MiB;
> - mc->default_cpus = mc->min_cpus = mc->max_cpus =
> - aspeed_soc_num_cpus(amc->soc_name);
> + aspeed_machine_class_init_cpus_defaults(mc);
> }
>
> static void aspeed_machine_ast2500_evb_class_init(ObjectClass *oc, void *data)
> @@ -1248,8 +1248,7 @@ static void aspeed_machine_ast2500_evb_class_init(ObjectClass *oc, void *data)
> amc->num_cs = 1;
> amc->i2c_init = ast2500_evb_i2c_init;
> mc->default_ram_size = 512 * MiB;
> - mc->default_cpus = mc->min_cpus = mc->max_cpus =
> - aspeed_soc_num_cpus(amc->soc_name);
> + aspeed_machine_class_init_cpus_defaults(mc);
> };
>
> static void aspeed_machine_yosemitev2_class_init(ObjectClass *oc, void *data)
> @@ -1266,8 +1265,7 @@ static void aspeed_machine_yosemitev2_class_init(ObjectClass *oc, void *data)
> amc->num_cs = 2;
> amc->i2c_init = yosemitev2_bmc_i2c_init;
> mc->default_ram_size = 512 * MiB;
> - mc->default_cpus = mc->min_cpus = mc->max_cpus =
> - aspeed_soc_num_cpus(amc->soc_name);
> + aspeed_machine_class_init_cpus_defaults(mc);
> };
>
> static void aspeed_machine_romulus_class_init(ObjectClass *oc, void *data)
> @@ -1283,8 +1281,7 @@ static void aspeed_machine_romulus_class_init(ObjectClass *oc, void *data)
> amc->num_cs = 2;
> amc->i2c_init = romulus_bmc_i2c_init;
> mc->default_ram_size = 512 * MiB;
> - mc->default_cpus = mc->min_cpus = mc->max_cpus =
> - aspeed_soc_num_cpus(amc->soc_name);
> + aspeed_machine_class_init_cpus_defaults(mc);
> };
>
> static void aspeed_machine_tiogapass_class_init(ObjectClass *oc, void *data)
> @@ -1301,8 +1298,7 @@ static void aspeed_machine_tiogapass_class_init(ObjectClass *oc, void *data)
> amc->num_cs = 2;
> amc->i2c_init = tiogapass_bmc_i2c_init;
> mc->default_ram_size = 1 * GiB;
> - mc->default_cpus = mc->min_cpus = mc->max_cpus =
> - aspeed_soc_num_cpus(amc->soc_name);
> + aspeed_machine_class_init_cpus_defaults(mc);
> };
>
> static void aspeed_machine_sonorapass_class_init(ObjectClass *oc, void *data)
> @@ -1318,8 +1314,7 @@ static void aspeed_machine_sonorapass_class_init(ObjectClass *oc, void *data)
> amc->num_cs = 2;
> amc->i2c_init = sonorapass_bmc_i2c_init;
> mc->default_ram_size = 512 * MiB;
> - mc->default_cpus = mc->min_cpus = mc->max_cpus =
> - aspeed_soc_num_cpus(amc->soc_name);
> + aspeed_machine_class_init_cpus_defaults(mc);
> };
>
> static void aspeed_machine_witherspoon_class_init(ObjectClass *oc, void *data)
> @@ -1335,8 +1330,7 @@ static void aspeed_machine_witherspoon_class_init(ObjectClass *oc, void *data)
> amc->num_cs = 2;
> amc->i2c_init = witherspoon_bmc_i2c_init;
> mc->default_ram_size = 512 * MiB;
> - mc->default_cpus = mc->min_cpus = mc->max_cpus =
> - aspeed_soc_num_cpus(amc->soc_name);
> + aspeed_machine_class_init_cpus_defaults(mc);
> };
>
> static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, void *data)
> @@ -1355,8 +1349,7 @@ static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, void *data)
> ASPEED_MAC3_ON;
> amc->i2c_init = ast2600_evb_i2c_init;
> mc->default_ram_size = 1 * GiB;
> - mc->default_cpus = mc->min_cpus = mc->max_cpus =
> - aspeed_soc_num_cpus(amc->soc_name);
> + aspeed_machine_class_init_cpus_defaults(mc);
> };
>
> static void aspeed_machine_tacoma_class_init(ObjectClass *oc, void *data)
> @@ -1374,8 +1367,7 @@ static void aspeed_machine_tacoma_class_init(ObjectClass *oc, void *data)
> amc->macs_mask = ASPEED_MAC2_ON;
> amc->i2c_init = witherspoon_bmc_i2c_init; /* Same board layout */
> mc->default_ram_size = 1 * GiB;
> - mc->default_cpus = mc->min_cpus = mc->max_cpus =
> - aspeed_soc_num_cpus(amc->soc_name);
> + aspeed_machine_class_init_cpus_defaults(mc);
> };
>
> static void aspeed_machine_g220a_class_init(ObjectClass *oc, void *data)
> @@ -1392,8 +1384,7 @@ static void aspeed_machine_g220a_class_init(ObjectClass *oc, void *data)
> amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
> amc->i2c_init = g220a_bmc_i2c_init;
> mc->default_ram_size = 1024 * MiB;
> - mc->default_cpus = mc->min_cpus = mc->max_cpus =
> - aspeed_soc_num_cpus(amc->soc_name);
> + aspeed_machine_class_init_cpus_defaults(mc);
> };
>
> static void aspeed_machine_fp5280g2_class_init(ObjectClass *oc, void *data)
> @@ -1410,8 +1401,7 @@ static void aspeed_machine_fp5280g2_class_init(ObjectClass *oc, void *data)
> amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
> amc->i2c_init = fp5280g2_bmc_i2c_init;
> mc->default_ram_size = 512 * MiB;
> - mc->default_cpus = mc->min_cpus = mc->max_cpus =
> - aspeed_soc_num_cpus(amc->soc_name);
> + aspeed_machine_class_init_cpus_defaults(mc);
> };
>
> static void aspeed_machine_rainier_class_init(ObjectClass *oc, void *data)
> @@ -1429,8 +1419,7 @@ static void aspeed_machine_rainier_class_init(ObjectClass *oc, void *data)
> amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON;
> amc->i2c_init = rainier_bmc_i2c_init;
> mc->default_ram_size = 1 * GiB;
> - mc->default_cpus = mc->min_cpus = mc->max_cpus =
> - aspeed_soc_num_cpus(amc->soc_name);
> + aspeed_machine_class_init_cpus_defaults(mc);
> };
>
> #define FUJI_BMC_RAM_SIZE ASPEED_RAM_SIZE(2 * GiB)
> @@ -1451,8 +1440,7 @@ static void aspeed_machine_fuji_class_init(ObjectClass *oc, void *data)
> amc->i2c_init = fuji_bmc_i2c_init;
> amc->uart_default = ASPEED_DEV_UART1;
> mc->default_ram_size = FUJI_BMC_RAM_SIZE;
> - mc->default_cpus = mc->min_cpus = mc->max_cpus =
> - aspeed_soc_num_cpus(amc->soc_name);
> + aspeed_machine_class_init_cpus_defaults(mc);
> };
>
> #define BLETCHLEY_BMC_RAM_SIZE ASPEED_RAM_SIZE(2 * GiB)
> @@ -1472,8 +1460,7 @@ static void aspeed_machine_bletchley_class_init(ObjectClass *oc, void *data)
> amc->macs_mask = ASPEED_MAC2_ON;
> amc->i2c_init = bletchley_bmc_i2c_init;
> mc->default_ram_size = BLETCHLEY_BMC_RAM_SIZE;
> - mc->default_cpus = mc->min_cpus = mc->max_cpus =
> - aspeed_soc_num_cpus(amc->soc_name);
> + aspeed_machine_class_init_cpus_defaults(mc);
> }
>
> static void fby35_reset(MachineState *state, ShutdownCause reason)
> @@ -1515,6 +1502,7 @@ static void aspeed_machine_fby35_class_init(ObjectClass *oc, void *data)
> amc->i2c_init = fby35_i2c_init;
> /* FIXME: Replace this macro with something more general */
> mc->default_ram_size = FUJI_BMC_RAM_SIZE;
> + aspeed_machine_class_init_cpus_defaults(mc); //
please remove the extra //, with that
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Thanks,
C.
> }
>
> #define AST1030_INTERNAL_FLASH_SIZE (1024 * 1024)
> @@ -1592,8 +1580,7 @@ static void aspeed_minibmc_machine_ast1030_evb_class_init(ObjectClass *oc,
> amc->spi_model = "sst25vf032b";
> amc->num_cs = 2;
> amc->macs_mask = 0;
> - mc->default_cpus = mc->min_cpus = mc->max_cpus =
> - aspeed_soc_num_cpus(amc->soc_name);
> + aspeed_machine_class_init_cpus_defaults(mc);
> }
>
> static void aspeed_machine_qcom_dc_scm_v1_class_init(ObjectClass *oc,
> @@ -1612,8 +1599,7 @@ static void aspeed_machine_qcom_dc_scm_v1_class_init(ObjectClass *oc,
> amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON;
> amc->i2c_init = qcom_dc_scm_bmc_i2c_init;
> mc->default_ram_size = 1 * GiB;
> - mc->default_cpus = mc->min_cpus = mc->max_cpus =
> - aspeed_soc_num_cpus(amc->soc_name);
> + aspeed_machine_class_init_cpus_defaults(mc);
> };
>
> static void aspeed_machine_qcom_firework_class_init(ObjectClass *oc,
> @@ -1632,8 +1618,7 @@ static void aspeed_machine_qcom_firework_class_init(ObjectClass *oc,
> amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON;
> amc->i2c_init = qcom_dc_scm_firework_i2c_init;
> mc->default_ram_size = 1 * GiB;
> - mc->default_cpus = mc->min_cpus = mc->max_cpus =
> - aspeed_soc_num_cpus(amc->soc_name);
> + aspeed_machine_class_init_cpus_defaults(mc);
> };
>
> static const TypeInfo aspeed_machine_types[] = {
^ permalink raw reply [flat|nested] 22+ messages in thread* Re: [PATCH v2 3/5] hw/arm/aspeed: Init CPU defaults in a common helper
2024-01-23 22:48 ` [PATCH v2 3/5] hw/arm/aspeed: Init CPU defaults in a common helper Philippe Mathieu-Daudé
2024-01-24 6:58 ` Cédric Le Goater
@ 2024-01-24 23:15 ` Richard Henderson
2024-01-25 2:26 ` Gavin Shan
2 siblings, 0 replies; 22+ messages in thread
From: Richard Henderson @ 2024-01-24 23:15 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Peter Maydell, qemu-arm, Joel Stanley, Andrew Jeffery,
Cédric Le Goater
On 1/24/24 08:48, Philippe Mathieu-Daudé wrote:
> Rework aspeed_soc_num_cpus() as a new init_cpus_defaults()
> helper to reduce code duplication.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
> hw/arm/aspeed.c | 71 +++++++++++++++++++------------------------------
> 1 file changed, 28 insertions(+), 43 deletions(-)
>
> diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
> index 5b01a4dd28..636a6269aa 100644
> --- a/hw/arm/aspeed.c
> +++ b/hw/arm/aspeed.c
> @@ -1141,10 +1141,14 @@ static void aspeed_machine_class_props_init(ObjectClass *oc)
> "Change the SPI Flash model");
> }
>
> -static int aspeed_soc_num_cpus(const char *soc_name)
> +static void aspeed_machine_class_init_cpus_defaults(MachineClass *mc)
> {
> - AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(soc_name));
> - return sc->num_cpus;
> + AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(mc);
> + AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(amc->soc_name));
> +
> + mc->default_cpus = mc->min_cpus
> + = mc->max_cpus
> + = sc->num_cpus;
Not keen on that layout. If you don't want to repeat sc->num_cpus, maybe just pull out
int n = sc->num_cpus;
at the top.
Otherwise,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 22+ messages in thread* Re: [PATCH v2 3/5] hw/arm/aspeed: Init CPU defaults in a common helper
2024-01-23 22:48 ` [PATCH v2 3/5] hw/arm/aspeed: Init CPU defaults in a common helper Philippe Mathieu-Daudé
2024-01-24 6:58 ` Cédric Le Goater
2024-01-24 23:15 ` Richard Henderson
@ 2024-01-25 2:26 ` Gavin Shan
2024-01-25 4:50 ` Philippe Mathieu-Daudé
2 siblings, 1 reply; 22+ messages in thread
From: Gavin Shan @ 2024-01-25 2:26 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Peter Maydell, qemu-arm, Joel Stanley, Andrew Jeffery,
Cédric Le Goater
Hi Phil,
On 1/24/24 08:48, Philippe Mathieu-Daudé wrote:
> Rework aspeed_soc_num_cpus() as a new init_cpus_defaults()
> helper to reduce code duplication.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
> hw/arm/aspeed.c | 71 +++++++++++++++++++------------------------------
> 1 file changed, 28 insertions(+), 43 deletions(-)
>
One nit needs to be addressed:
Reviewed-by: Gavin Shan <gshan@redhat.com>
> diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
> index 5b01a4dd28..636a6269aa 100644
> --- a/hw/arm/aspeed.c
> +++ b/hw/arm/aspeed.c
> @@ -1141,10 +1141,14 @@ static void aspeed_machine_class_props_init(ObjectClass *oc)
> "Change the SPI Flash model");
> }
>
> -static int aspeed_soc_num_cpus(const char *soc_name)
> +static void aspeed_machine_class_init_cpus_defaults(MachineClass *mc)
> {
> - AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(soc_name));
> - return sc->num_cpus;
> + AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(mc);
> + AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(amc->soc_name));
> +
> + mc->default_cpus = mc->min_cpus
> + = mc->max_cpus
> + = sc->num_cpus;
> }
>
> static void aspeed_machine_class_init(ObjectClass *oc, void *data)
> @@ -1176,8 +1180,7 @@ static void aspeed_machine_palmetto_class_init(ObjectClass *oc, void *data)
> amc->num_cs = 1;
> amc->i2c_init = palmetto_bmc_i2c_init;
> mc->default_ram_size = 256 * MiB;
> - mc->default_cpus = mc->min_cpus = mc->max_cpus =
> - aspeed_soc_num_cpus(amc->soc_name);
> + aspeed_machine_class_init_cpus_defaults(mc);
> };
>
> static void aspeed_machine_quanta_q71l_class_init(ObjectClass *oc, void *data)
> @@ -1193,8 +1196,7 @@ static void aspeed_machine_quanta_q71l_class_init(ObjectClass *oc, void *data)
> amc->num_cs = 1;
> amc->i2c_init = quanta_q71l_bmc_i2c_init;
> mc->default_ram_size = 128 * MiB;
> - mc->default_cpus = mc->min_cpus = mc->max_cpus =
> - aspeed_soc_num_cpus(amc->soc_name);
> + aspeed_machine_class_init_cpus_defaults(mc);
> }
>
> static void aspeed_machine_supermicrox11_bmc_class_init(ObjectClass *oc,
> @@ -1212,8 +1214,7 @@ static void aspeed_machine_supermicrox11_bmc_class_init(ObjectClass *oc,
> amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
> amc->i2c_init = palmetto_bmc_i2c_init;
> mc->default_ram_size = 256 * MiB;
> - mc->default_cpus = mc->min_cpus = mc->max_cpus =
> - aspeed_soc_num_cpus(amc->soc_name);
> + aspeed_machine_class_init_cpus_defaults(mc);
> }
>
> static void aspeed_machine_supermicro_x11spi_bmc_class_init(ObjectClass *oc,
> @@ -1231,8 +1232,7 @@ static void aspeed_machine_supermicro_x11spi_bmc_class_init(ObjectClass *oc,
> amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
> amc->i2c_init = palmetto_bmc_i2c_init;
> mc->default_ram_size = 512 * MiB;
> - mc->default_cpus = mc->min_cpus = mc->max_cpus =
> - aspeed_soc_num_cpus(amc->soc_name);
> + aspeed_machine_class_init_cpus_defaults(mc);
> }
>
> static void aspeed_machine_ast2500_evb_class_init(ObjectClass *oc, void *data)
> @@ -1248,8 +1248,7 @@ static void aspeed_machine_ast2500_evb_class_init(ObjectClass *oc, void *data)
> amc->num_cs = 1;
> amc->i2c_init = ast2500_evb_i2c_init;
> mc->default_ram_size = 512 * MiB;
> - mc->default_cpus = mc->min_cpus = mc->max_cpus =
> - aspeed_soc_num_cpus(amc->soc_name);
> + aspeed_machine_class_init_cpus_defaults(mc);
> };
>
> static void aspeed_machine_yosemitev2_class_init(ObjectClass *oc, void *data)
> @@ -1266,8 +1265,7 @@ static void aspeed_machine_yosemitev2_class_init(ObjectClass *oc, void *data)
> amc->num_cs = 2;
> amc->i2c_init = yosemitev2_bmc_i2c_init;
> mc->default_ram_size = 512 * MiB;
> - mc->default_cpus = mc->min_cpus = mc->max_cpus =
> - aspeed_soc_num_cpus(amc->soc_name);
> + aspeed_machine_class_init_cpus_defaults(mc);
> };
>
> static void aspeed_machine_romulus_class_init(ObjectClass *oc, void *data)
> @@ -1283,8 +1281,7 @@ static void aspeed_machine_romulus_class_init(ObjectClass *oc, void *data)
> amc->num_cs = 2;
> amc->i2c_init = romulus_bmc_i2c_init;
> mc->default_ram_size = 512 * MiB;
> - mc->default_cpus = mc->min_cpus = mc->max_cpus =
> - aspeed_soc_num_cpus(amc->soc_name);
> + aspeed_machine_class_init_cpus_defaults(mc);
> };
>
> static void aspeed_machine_tiogapass_class_init(ObjectClass *oc, void *data)
> @@ -1301,8 +1298,7 @@ static void aspeed_machine_tiogapass_class_init(ObjectClass *oc, void *data)
> amc->num_cs = 2;
> amc->i2c_init = tiogapass_bmc_i2c_init;
> mc->default_ram_size = 1 * GiB;
> - mc->default_cpus = mc->min_cpus = mc->max_cpus =
> - aspeed_soc_num_cpus(amc->soc_name);
> + aspeed_machine_class_init_cpus_defaults(mc);
> };
>
> static void aspeed_machine_sonorapass_class_init(ObjectClass *oc, void *data)
> @@ -1318,8 +1314,7 @@ static void aspeed_machine_sonorapass_class_init(ObjectClass *oc, void *data)
> amc->num_cs = 2;
> amc->i2c_init = sonorapass_bmc_i2c_init;
> mc->default_ram_size = 512 * MiB;
> - mc->default_cpus = mc->min_cpus = mc->max_cpus =
> - aspeed_soc_num_cpus(amc->soc_name);
> + aspeed_machine_class_init_cpus_defaults(mc);
> };
>
> static void aspeed_machine_witherspoon_class_init(ObjectClass *oc, void *data)
> @@ -1335,8 +1330,7 @@ static void aspeed_machine_witherspoon_class_init(ObjectClass *oc, void *data)
> amc->num_cs = 2;
> amc->i2c_init = witherspoon_bmc_i2c_init;
> mc->default_ram_size = 512 * MiB;
> - mc->default_cpus = mc->min_cpus = mc->max_cpus =
> - aspeed_soc_num_cpus(amc->soc_name);
> + aspeed_machine_class_init_cpus_defaults(mc);
> };
>
> static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, void *data)
> @@ -1355,8 +1349,7 @@ static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, void *data)
> ASPEED_MAC3_ON;
> amc->i2c_init = ast2600_evb_i2c_init;
> mc->default_ram_size = 1 * GiB;
> - mc->default_cpus = mc->min_cpus = mc->max_cpus =
> - aspeed_soc_num_cpus(amc->soc_name);
> + aspeed_machine_class_init_cpus_defaults(mc);
> };
>
> static void aspeed_machine_tacoma_class_init(ObjectClass *oc, void *data)
> @@ -1374,8 +1367,7 @@ static void aspeed_machine_tacoma_class_init(ObjectClass *oc, void *data)
> amc->macs_mask = ASPEED_MAC2_ON;
> amc->i2c_init = witherspoon_bmc_i2c_init; /* Same board layout */
> mc->default_ram_size = 1 * GiB;
> - mc->default_cpus = mc->min_cpus = mc->max_cpus =
> - aspeed_soc_num_cpus(amc->soc_name);
> + aspeed_machine_class_init_cpus_defaults(mc);
> };
>
> static void aspeed_machine_g220a_class_init(ObjectClass *oc, void *data)
> @@ -1392,8 +1384,7 @@ static void aspeed_machine_g220a_class_init(ObjectClass *oc, void *data)
> amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
> amc->i2c_init = g220a_bmc_i2c_init;
> mc->default_ram_size = 1024 * MiB;
> - mc->default_cpus = mc->min_cpus = mc->max_cpus =
> - aspeed_soc_num_cpus(amc->soc_name);
> + aspeed_machine_class_init_cpus_defaults(mc);
> };
>
> static void aspeed_machine_fp5280g2_class_init(ObjectClass *oc, void *data)
> @@ -1410,8 +1401,7 @@ static void aspeed_machine_fp5280g2_class_init(ObjectClass *oc, void *data)
> amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
> amc->i2c_init = fp5280g2_bmc_i2c_init;
> mc->default_ram_size = 512 * MiB;
> - mc->default_cpus = mc->min_cpus = mc->max_cpus =
> - aspeed_soc_num_cpus(amc->soc_name);
> + aspeed_machine_class_init_cpus_defaults(mc);
> };
>
> static void aspeed_machine_rainier_class_init(ObjectClass *oc, void *data)
> @@ -1429,8 +1419,7 @@ static void aspeed_machine_rainier_class_init(ObjectClass *oc, void *data)
> amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON;
> amc->i2c_init = rainier_bmc_i2c_init;
> mc->default_ram_size = 1 * GiB;
> - mc->default_cpus = mc->min_cpus = mc->max_cpus =
> - aspeed_soc_num_cpus(amc->soc_name);
> + aspeed_machine_class_init_cpus_defaults(mc);
> };
>
> #define FUJI_BMC_RAM_SIZE ASPEED_RAM_SIZE(2 * GiB)
> @@ -1451,8 +1440,7 @@ static void aspeed_machine_fuji_class_init(ObjectClass *oc, void *data)
> amc->i2c_init = fuji_bmc_i2c_init;
> amc->uart_default = ASPEED_DEV_UART1;
> mc->default_ram_size = FUJI_BMC_RAM_SIZE;
> - mc->default_cpus = mc->min_cpus = mc->max_cpus =
> - aspeed_soc_num_cpus(amc->soc_name);
> + aspeed_machine_class_init_cpus_defaults(mc);
> };
>
> #define BLETCHLEY_BMC_RAM_SIZE ASPEED_RAM_SIZE(2 * GiB)
> @@ -1472,8 +1460,7 @@ static void aspeed_machine_bletchley_class_init(ObjectClass *oc, void *data)
> amc->macs_mask = ASPEED_MAC2_ON;
> amc->i2c_init = bletchley_bmc_i2c_init;
> mc->default_ram_size = BLETCHLEY_BMC_RAM_SIZE;
> - mc->default_cpus = mc->min_cpus = mc->max_cpus =
> - aspeed_soc_num_cpus(amc->soc_name);
> + aspeed_machine_class_init_cpus_defaults(mc);
> }
>
> static void fby35_reset(MachineState *state, ShutdownCause reason)
> @@ -1515,6 +1502,7 @@ static void aspeed_machine_fby35_class_init(ObjectClass *oc, void *data)
> amc->i2c_init = fby35_i2c_init;
> /* FIXME: Replace this macro with something more general */
> mc->default_ram_size = FUJI_BMC_RAM_SIZE;
> + aspeed_machine_class_init_cpus_defaults(mc); //
> }
>
Failure from './scripts/checkpatch.pl --strict'
ERROR: do not use C99 // comments
#216: FILE: hw/arm/aspeed.c:1505:
+ aspeed_machine_class_init_cpus_defaults(mc); //
> #define AST1030_INTERNAL_FLASH_SIZE (1024 * 1024)
> @@ -1592,8 +1580,7 @@ static void aspeed_minibmc_machine_ast1030_evb_class_init(ObjectClass *oc,
> amc->spi_model = "sst25vf032b";
> amc->num_cs = 2;
> amc->macs_mask = 0;
> - mc->default_cpus = mc->min_cpus = mc->max_cpus =
> - aspeed_soc_num_cpus(amc->soc_name);
> + aspeed_machine_class_init_cpus_defaults(mc);
> }
>
> static void aspeed_machine_qcom_dc_scm_v1_class_init(ObjectClass *oc,
> @@ -1612,8 +1599,7 @@ static void aspeed_machine_qcom_dc_scm_v1_class_init(ObjectClass *oc,
> amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON;
> amc->i2c_init = qcom_dc_scm_bmc_i2c_init;
> mc->default_ram_size = 1 * GiB;
> - mc->default_cpus = mc->min_cpus = mc->max_cpus =
> - aspeed_soc_num_cpus(amc->soc_name);
> + aspeed_machine_class_init_cpus_defaults(mc);
> };
>
> static void aspeed_machine_qcom_firework_class_init(ObjectClass *oc,
> @@ -1632,8 +1618,7 @@ static void aspeed_machine_qcom_firework_class_init(ObjectClass *oc,
> amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON;
> amc->i2c_init = qcom_dc_scm_firework_i2c_init;
> mc->default_ram_size = 1 * GiB;
> - mc->default_cpus = mc->min_cpus = mc->max_cpus =
> - aspeed_soc_num_cpus(amc->soc_name);
> + aspeed_machine_class_init_cpus_defaults(mc);
> };
>
> static const TypeInfo aspeed_machine_types[] = {
Thanks,
Gavin
^ permalink raw reply [flat|nested] 22+ messages in thread* Re: [PATCH v2 3/5] hw/arm/aspeed: Init CPU defaults in a common helper
2024-01-25 2:26 ` Gavin Shan
@ 2024-01-25 4:50 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 22+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-01-25 4:50 UTC (permalink / raw)
To: Gavin Shan, qemu-devel
Cc: Peter Maydell, qemu-arm, Joel Stanley, Andrew Jeffery,
Cédric Le Goater
On 25/1/24 03:26, Gavin Shan wrote:
> Hi Phil,
>
> On 1/24/24 08:48, Philippe Mathieu-Daudé wrote:
>> Rework aspeed_soc_num_cpus() as a new init_cpus_defaults()
>> helper to reduce code duplication.
>>
>> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
>> ---
>> hw/arm/aspeed.c | 71 +++++++++++++++++++------------------------------
>> 1 file changed, 28 insertions(+), 43 deletions(-)
>>
>
> One nit needs to be addressed:
>
> Reviewed-by: Gavin Shan <gshan@redhat.com>
> Failure from './scripts/checkpatch.pl --strict'
>
> ERROR: do not use C99 // comments
> #216: FILE: hw/arm/aspeed.c:1505:
> + aspeed_machine_class_init_cpus_defaults(mc); //
Oops, forgot to clean that =) Thanks!
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH v2 4/5] hw/arm/aspeed: Introduce aspeed_soc_cpu_type() helper
2024-01-23 22:48 [PATCH v2 0/5] hw/arm/aspeed: Check for CPU types in machine_run_board_init() Philippe Mathieu-Daudé
` (2 preceding siblings ...)
2024-01-23 22:48 ` [PATCH v2 3/5] hw/arm/aspeed: Init CPU defaults in a common helper Philippe Mathieu-Daudé
@ 2024-01-23 22:48 ` Philippe Mathieu-Daudé
2024-01-24 6:58 ` Cédric Le Goater
` (2 more replies)
2024-01-23 22:48 ` [PATCH v2 5/5] hw/arm/aspeed: Check for CPU types in machine_run_board_init() Philippe Mathieu-Daudé
2024-01-23 22:50 ` [PATCH v2 0/5] " Philippe Mathieu-Daudé
5 siblings, 3 replies; 22+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-01-23 22:48 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, qemu-arm, Joel Stanley, Andrew Jeffery,
Cédric Le Goater, Philippe Mathieu-Daudé
In order to alter AspeedSoCClass::cpu_type in the next
commit, introduce the aspeed_soc_cpu_type() helper to
retrieve the per-SoC CPU type from AspeedSoCClass.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
include/hw/arm/aspeed_soc.h | 1 +
hw/arm/aspeed_ast10x0.c | 2 +-
hw/arm/aspeed_ast2400.c | 3 ++-
hw/arm/aspeed_ast2600.c | 3 ++-
hw/arm/aspeed_soc_common.c | 5 +++++
5 files changed, 11 insertions(+), 3 deletions(-)
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index cb832bc1ee..a060a59918 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -143,6 +143,7 @@ struct AspeedSoCClass {
qemu_irq (*get_irq)(AspeedSoCState *s, int dev);
};
+const char *aspeed_soc_cpu_type(AspeedSoCClass *sc);
enum {
ASPEED_DEV_SPI_BOOT,
diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c
index 8becb146a8..dca601a3f9 100644
--- a/hw/arm/aspeed_ast10x0.c
+++ b/hw/arm/aspeed_ast10x0.c
@@ -211,7 +211,7 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
/* AST1030 CPU Core */
armv7m = DEVICE(&a->armv7m);
qdev_prop_set_uint32(armv7m, "num-irq", 256);
- qdev_prop_set_string(armv7m, "cpu-type", sc->cpu_type);
+ qdev_prop_set_string(armv7m, "cpu-type", aspeed_soc_cpu_type(sc));
qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk);
object_property_set_link(OBJECT(&a->armv7m), "memory",
OBJECT(s->memory), &error_abort);
diff --git a/hw/arm/aspeed_ast2400.c b/hw/arm/aspeed_ast2400.c
index ad76035528..3baf95916d 100644
--- a/hw/arm/aspeed_ast2400.c
+++ b/hw/arm/aspeed_ast2400.c
@@ -156,7 +156,8 @@ static void aspeed_ast2400_soc_init(Object *obj)
}
for (i = 0; i < sc->num_cpus; i++) {
- object_initialize_child(obj, "cpu[*]", &a->cpu[i], sc->cpu_type);
+ object_initialize_child(obj, "cpu[*]", &a->cpu[i],
+ aspeed_soc_cpu_type(sc));
}
snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname);
diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
index 386a88d4e0..b264433cf0 100644
--- a/hw/arm/aspeed_ast2600.c
+++ b/hw/arm/aspeed_ast2600.c
@@ -158,7 +158,8 @@ static void aspeed_soc_ast2600_init(Object *obj)
}
for (i = 0; i < sc->num_cpus; i++) {
- object_initialize_child(obj, "cpu[*]", &a->cpu[i], sc->cpu_type);
+ object_initialize_child(obj, "cpu[*]", &a->cpu[i],
+ aspeed_soc_cpu_type(sc));
}
snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname);
diff --git a/hw/arm/aspeed_soc_common.c b/hw/arm/aspeed_soc_common.c
index 828f61093b..36ca189ce9 100644
--- a/hw/arm/aspeed_soc_common.c
+++ b/hw/arm/aspeed_soc_common.c
@@ -18,6 +18,11 @@
#include "hw/char/serial.h"
+const char *aspeed_soc_cpu_type(AspeedSoCClass *sc)
+{
+ return sc->cpu_type;
+}
+
qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev)
{
return ASPEED_SOC_GET_CLASS(s)->get_irq(s, dev);
--
2.41.0
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH v2 4/5] hw/arm/aspeed: Introduce aspeed_soc_cpu_type() helper
2024-01-23 22:48 ` [PATCH v2 4/5] hw/arm/aspeed: Introduce aspeed_soc_cpu_type() helper Philippe Mathieu-Daudé
@ 2024-01-24 6:58 ` Cédric Le Goater
2024-01-24 23:17 ` Richard Henderson
2024-01-25 2:27 ` Gavin Shan
2 siblings, 0 replies; 22+ messages in thread
From: Cédric Le Goater @ 2024-01-24 6:58 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Peter Maydell, qemu-arm, Joel Stanley, Andrew Jeffery
On 1/23/24 23:48, Philippe Mathieu-Daudé wrote:
> In order to alter AspeedSoCClass::cpu_type in the next
> commit, introduce the aspeed_soc_cpu_type() helper to
> retrieve the per-SoC CPU type from AspeedSoCClass.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Thanks,
C.
> ---
> include/hw/arm/aspeed_soc.h | 1 +
> hw/arm/aspeed_ast10x0.c | 2 +-
> hw/arm/aspeed_ast2400.c | 3 ++-
> hw/arm/aspeed_ast2600.c | 3 ++-
> hw/arm/aspeed_soc_common.c | 5 +++++
> 5 files changed, 11 insertions(+), 3 deletions(-)
>
> diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
> index cb832bc1ee..a060a59918 100644
> --- a/include/hw/arm/aspeed_soc.h
> +++ b/include/hw/arm/aspeed_soc.h
> @@ -143,6 +143,7 @@ struct AspeedSoCClass {
> qemu_irq (*get_irq)(AspeedSoCState *s, int dev);
> };
>
> +const char *aspeed_soc_cpu_type(AspeedSoCClass *sc);
>
> enum {
> ASPEED_DEV_SPI_BOOT,
> diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c
> index 8becb146a8..dca601a3f9 100644
> --- a/hw/arm/aspeed_ast10x0.c
> +++ b/hw/arm/aspeed_ast10x0.c
> @@ -211,7 +211,7 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
> /* AST1030 CPU Core */
> armv7m = DEVICE(&a->armv7m);
> qdev_prop_set_uint32(armv7m, "num-irq", 256);
> - qdev_prop_set_string(armv7m, "cpu-type", sc->cpu_type);
> + qdev_prop_set_string(armv7m, "cpu-type", aspeed_soc_cpu_type(sc));
> qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk);
> object_property_set_link(OBJECT(&a->armv7m), "memory",
> OBJECT(s->memory), &error_abort);
> diff --git a/hw/arm/aspeed_ast2400.c b/hw/arm/aspeed_ast2400.c
> index ad76035528..3baf95916d 100644
> --- a/hw/arm/aspeed_ast2400.c
> +++ b/hw/arm/aspeed_ast2400.c
> @@ -156,7 +156,8 @@ static void aspeed_ast2400_soc_init(Object *obj)
> }
>
> for (i = 0; i < sc->num_cpus; i++) {
> - object_initialize_child(obj, "cpu[*]", &a->cpu[i], sc->cpu_type);
> + object_initialize_child(obj, "cpu[*]", &a->cpu[i],
> + aspeed_soc_cpu_type(sc));
> }
>
> snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname);
> diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
> index 386a88d4e0..b264433cf0 100644
> --- a/hw/arm/aspeed_ast2600.c
> +++ b/hw/arm/aspeed_ast2600.c
> @@ -158,7 +158,8 @@ static void aspeed_soc_ast2600_init(Object *obj)
> }
>
> for (i = 0; i < sc->num_cpus; i++) {
> - object_initialize_child(obj, "cpu[*]", &a->cpu[i], sc->cpu_type);
> + object_initialize_child(obj, "cpu[*]", &a->cpu[i],
> + aspeed_soc_cpu_type(sc));
> }
>
> snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname);
> diff --git a/hw/arm/aspeed_soc_common.c b/hw/arm/aspeed_soc_common.c
> index 828f61093b..36ca189ce9 100644
> --- a/hw/arm/aspeed_soc_common.c
> +++ b/hw/arm/aspeed_soc_common.c
> @@ -18,6 +18,11 @@
> #include "hw/char/serial.h"
>
>
> +const char *aspeed_soc_cpu_type(AspeedSoCClass *sc)
> +{
> + return sc->cpu_type;
> +}
> +
> qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev)
> {
> return ASPEED_SOC_GET_CLASS(s)->get_irq(s, dev);
^ permalink raw reply [flat|nested] 22+ messages in thread* Re: [PATCH v2 4/5] hw/arm/aspeed: Introduce aspeed_soc_cpu_type() helper
2024-01-23 22:48 ` [PATCH v2 4/5] hw/arm/aspeed: Introduce aspeed_soc_cpu_type() helper Philippe Mathieu-Daudé
2024-01-24 6:58 ` Cédric Le Goater
@ 2024-01-24 23:17 ` Richard Henderson
2024-01-25 2:27 ` Gavin Shan
2 siblings, 0 replies; 22+ messages in thread
From: Richard Henderson @ 2024-01-24 23:17 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Peter Maydell, qemu-arm, Joel Stanley, Andrew Jeffery,
Cédric Le Goater
On 1/24/24 08:48, Philippe Mathieu-Daudé wrote:
> In order to alter AspeedSoCClass::cpu_type in the next
> commit, introduce the aspeed_soc_cpu_type() helper to
> retrieve the per-SoC CPU type from AspeedSoCClass.
>
> Signed-off-by: Philippe Mathieu-Daudé<philmd@linaro.org>
> ---
> include/hw/arm/aspeed_soc.h | 1 +
> hw/arm/aspeed_ast10x0.c | 2 +-
> hw/arm/aspeed_ast2400.c | 3 ++-
> hw/arm/aspeed_ast2600.c | 3 ++-
> hw/arm/aspeed_soc_common.c | 5 +++++
> 5 files changed, 11 insertions(+), 3 deletions(-)
>
> diff --git a/inclu
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v2 4/5] hw/arm/aspeed: Introduce aspeed_soc_cpu_type() helper
2024-01-23 22:48 ` [PATCH v2 4/5] hw/arm/aspeed: Introduce aspeed_soc_cpu_type() helper Philippe Mathieu-Daudé
2024-01-24 6:58 ` Cédric Le Goater
2024-01-24 23:17 ` Richard Henderson
@ 2024-01-25 2:27 ` Gavin Shan
2 siblings, 0 replies; 22+ messages in thread
From: Gavin Shan @ 2024-01-25 2:27 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Peter Maydell, qemu-arm, Joel Stanley, Andrew Jeffery,
Cédric Le Goater
On 1/24/24 08:48, Philippe Mathieu-Daudé wrote:
> In order to alter AspeedSoCClass::cpu_type in the next
> commit, introduce the aspeed_soc_cpu_type() helper to
> retrieve the per-SoC CPU type from AspeedSoCClass.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
> include/hw/arm/aspeed_soc.h | 1 +
> hw/arm/aspeed_ast10x0.c | 2 +-
> hw/arm/aspeed_ast2400.c | 3 ++-
> hw/arm/aspeed_ast2600.c | 3 ++-
> hw/arm/aspeed_soc_common.c | 5 +++++
> 5 files changed, 11 insertions(+), 3 deletions(-)
>
Reviewed-by: Gavin Shan <gshan@redhat.com>
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH v2 5/5] hw/arm/aspeed: Check for CPU types in machine_run_board_init()
2024-01-23 22:48 [PATCH v2 0/5] hw/arm/aspeed: Check for CPU types in machine_run_board_init() Philippe Mathieu-Daudé
` (3 preceding siblings ...)
2024-01-23 22:48 ` [PATCH v2 4/5] hw/arm/aspeed: Introduce aspeed_soc_cpu_type() helper Philippe Mathieu-Daudé
@ 2024-01-23 22:48 ` Philippe Mathieu-Daudé
2024-01-24 6:59 ` Cédric Le Goater
` (2 more replies)
2024-01-23 22:50 ` [PATCH v2 0/5] " Philippe Mathieu-Daudé
5 siblings, 3 replies; 22+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-01-23 22:48 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, qemu-arm, Joel Stanley, Andrew Jeffery,
Cédric Le Goater, Philippe Mathieu-Daudé
Aspeed SoCs use a single CPU type (set as AspeedSoCClass::cpu_type).
Convert it to a NULL-terminated array (of a single non-NULL element).
Set MachineClass::valid_cpu_types[] to use the common machine code
to provide hints when the requested CPU is invalid (see commit
e702cbc19e ("machine: Improve is_cpu_type_supported()").
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
include/hw/arm/aspeed_soc.h | 3 ++-
hw/arm/aspeed.c | 1 +
hw/arm/aspeed_ast10x0.c | 6 +++++-
hw/arm/aspeed_ast2400.c | 12 ++++++++++--
hw/arm/aspeed_ast2600.c | 6 +++++-
hw/arm/aspeed_soc_common.c | 5 ++++-
6 files changed, 27 insertions(+), 6 deletions(-)
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index a060a59918..0db5a41e71 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -128,7 +128,8 @@ struct AspeedSoCClass {
DeviceClass parent_class;
const char *name;
- const char *cpu_type;
+ /** valid_cpu_types: NULL terminated array of a single CPU type. */
+ const char * const *valid_cpu_types;
uint32_t silicon_rev;
uint64_t sram_size;
uint64_t secsram_size;
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index 636a6269aa..1be3b6bcae 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -1149,6 +1149,7 @@ static void aspeed_machine_class_init_cpus_defaults(MachineClass *mc)
mc->default_cpus = mc->min_cpus
= mc->max_cpus
= sc->num_cpus;
+ mc->valid_cpu_types = sc->valid_cpu_types;
}
static void aspeed_machine_class_init(ObjectClass *oc, void *data)
diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c
index dca601a3f9..c3b5116a6a 100644
--- a/hw/arm/aspeed_ast10x0.c
+++ b/hw/arm/aspeed_ast10x0.c
@@ -417,13 +417,17 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
static void aspeed_soc_ast1030_class_init(ObjectClass *klass, void *data)
{
+ static const char * const valid_cpu_types[] = {
+ ARM_CPU_TYPE_NAME("cortex-m4"), /* TODO cortex-m4f */
+ NULL
+ };
DeviceClass *dc = DEVICE_CLASS(klass);
AspeedSoCClass *sc = ASPEED_SOC_CLASS(dc);
dc->realize = aspeed_soc_ast1030_realize;
sc->name = "ast1030-a1";
- sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-m4"); /* TODO cortex-m4f */
+ sc->valid_cpu_types = valid_cpu_types;
sc->silicon_rev = AST1030_A1_SILICON_REV;
sc->sram_size = 0xc0000;
sc->secsram_size = 0x40000; /* 256 * KiB */
diff --git a/hw/arm/aspeed_ast2400.c b/hw/arm/aspeed_ast2400.c
index 3baf95916d..8829561bb6 100644
--- a/hw/arm/aspeed_ast2400.c
+++ b/hw/arm/aspeed_ast2400.c
@@ -503,6 +503,10 @@ static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp)
static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data)
{
+ static const char * const valid_cpu_types[] = {
+ ARM_CPU_TYPE_NAME("arm926"),
+ NULL
+ };
AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
DeviceClass *dc = DEVICE_CLASS(oc);
@@ -511,7 +515,7 @@ static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data)
dc->user_creatable = false;
sc->name = "ast2400-a1";
- sc->cpu_type = ARM_CPU_TYPE_NAME("arm926");
+ sc->valid_cpu_types = valid_cpu_types;
sc->silicon_rev = AST2400_A1_SILICON_REV;
sc->sram_size = 0x8000;
sc->spis_num = 1;
@@ -527,6 +531,10 @@ static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data)
static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data)
{
+ static const char * const valid_cpu_types[] = {
+ ARM_CPU_TYPE_NAME("arm1176"),
+ NULL
+ };
AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
DeviceClass *dc = DEVICE_CLASS(oc);
@@ -535,7 +543,7 @@ static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data)
dc->user_creatable = false;
sc->name = "ast2500-a1";
- sc->cpu_type = ARM_CPU_TYPE_NAME("arm1176");
+ sc->valid_cpu_types = valid_cpu_types;
sc->silicon_rev = AST2500_A1_SILICON_REV;
sc->sram_size = 0x9000;
sc->spis_num = 2;
diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
index b264433cf0..46baba0e41 100644
--- a/hw/arm/aspeed_ast2600.c
+++ b/hw/arm/aspeed_ast2600.c
@@ -629,13 +629,17 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data)
{
+ static const char * const valid_cpu_types[] = {
+ ARM_CPU_TYPE_NAME("cortex-a7"),
+ NULL
+ };
DeviceClass *dc = DEVICE_CLASS(oc);
AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
dc->realize = aspeed_soc_ast2600_realize;
sc->name = "ast2600-a3";
- sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a7");
+ sc->valid_cpu_types = valid_cpu_types;
sc->silicon_rev = AST2600_A3_SILICON_REV;
sc->sram_size = 0x16400;
sc->spis_num = 2;
diff --git a/hw/arm/aspeed_soc_common.c b/hw/arm/aspeed_soc_common.c
index 36ca189ce9..123a0c432c 100644
--- a/hw/arm/aspeed_soc_common.c
+++ b/hw/arm/aspeed_soc_common.c
@@ -20,7 +20,10 @@
const char *aspeed_soc_cpu_type(AspeedSoCClass *sc)
{
- return sc->cpu_type;
+ assert(sc->valid_cpu_types);
+ assert(sc->valid_cpu_types[0]);
+ assert(!sc->valid_cpu_types[1]);
+ return sc->valid_cpu_types[0];
}
qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev)
--
2.41.0
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH v2 5/5] hw/arm/aspeed: Check for CPU types in machine_run_board_init()
2024-01-23 22:48 ` [PATCH v2 5/5] hw/arm/aspeed: Check for CPU types in machine_run_board_init() Philippe Mathieu-Daudé
@ 2024-01-24 6:59 ` Cédric Le Goater
2024-01-24 23:18 ` Richard Henderson
2024-01-25 2:28 ` Gavin Shan
2 siblings, 0 replies; 22+ messages in thread
From: Cédric Le Goater @ 2024-01-24 6:59 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Peter Maydell, qemu-arm, Joel Stanley, Andrew Jeffery
On 1/23/24 23:48, Philippe Mathieu-Daudé wrote:
> Aspeed SoCs use a single CPU type (set as AspeedSoCClass::cpu_type).
> Convert it to a NULL-terminated array (of a single non-NULL element).
>
> Set MachineClass::valid_cpu_types[] to use the common machine code
> to provide hints when the requested CPU is invalid (see commit
> e702cbc19e ("machine: Improve is_cpu_type_supported()").
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Thanks,
C.
> ---
> include/hw/arm/aspeed_soc.h | 3 ++-
> hw/arm/aspeed.c | 1 +
> hw/arm/aspeed_ast10x0.c | 6 +++++-
> hw/arm/aspeed_ast2400.c | 12 ++++++++++--
> hw/arm/aspeed_ast2600.c | 6 +++++-
> hw/arm/aspeed_soc_common.c | 5 ++++-
> 6 files changed, 27 insertions(+), 6 deletions(-)
>
> diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
> index a060a59918..0db5a41e71 100644
> --- a/include/hw/arm/aspeed_soc.h
> +++ b/include/hw/arm/aspeed_soc.h
> @@ -128,7 +128,8 @@ struct AspeedSoCClass {
> DeviceClass parent_class;
>
> const char *name;
> - const char *cpu_type;
> + /** valid_cpu_types: NULL terminated array of a single CPU type. */
> + const char * const *valid_cpu_types;
> uint32_t silicon_rev;
> uint64_t sram_size;
> uint64_t secsram_size;
> diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
> index 636a6269aa..1be3b6bcae 100644
> --- a/hw/arm/aspeed.c
> +++ b/hw/arm/aspeed.c
> @@ -1149,6 +1149,7 @@ static void aspeed_machine_class_init_cpus_defaults(MachineClass *mc)
> mc->default_cpus = mc->min_cpus
> = mc->max_cpus
> = sc->num_cpus;
> + mc->valid_cpu_types = sc->valid_cpu_types;
> }
>
> static void aspeed_machine_class_init(ObjectClass *oc, void *data)
> diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c
> index dca601a3f9..c3b5116a6a 100644
> --- a/hw/arm/aspeed_ast10x0.c
> +++ b/hw/arm/aspeed_ast10x0.c
> @@ -417,13 +417,17 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
>
> static void aspeed_soc_ast1030_class_init(ObjectClass *klass, void *data)
> {
> + static const char * const valid_cpu_types[] = {
> + ARM_CPU_TYPE_NAME("cortex-m4"), /* TODO cortex-m4f */
> + NULL
> + };
> DeviceClass *dc = DEVICE_CLASS(klass);
> AspeedSoCClass *sc = ASPEED_SOC_CLASS(dc);
>
> dc->realize = aspeed_soc_ast1030_realize;
>
> sc->name = "ast1030-a1";
> - sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-m4"); /* TODO cortex-m4f */
> + sc->valid_cpu_types = valid_cpu_types;
> sc->silicon_rev = AST1030_A1_SILICON_REV;
> sc->sram_size = 0xc0000;
> sc->secsram_size = 0x40000; /* 256 * KiB */
> diff --git a/hw/arm/aspeed_ast2400.c b/hw/arm/aspeed_ast2400.c
> index 3baf95916d..8829561bb6 100644
> --- a/hw/arm/aspeed_ast2400.c
> +++ b/hw/arm/aspeed_ast2400.c
> @@ -503,6 +503,10 @@ static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp)
>
> static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data)
> {
> + static const char * const valid_cpu_types[] = {
> + ARM_CPU_TYPE_NAME("arm926"),
> + NULL
> + };
> AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
> DeviceClass *dc = DEVICE_CLASS(oc);
>
> @@ -511,7 +515,7 @@ static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data)
> dc->user_creatable = false;
>
> sc->name = "ast2400-a1";
> - sc->cpu_type = ARM_CPU_TYPE_NAME("arm926");
> + sc->valid_cpu_types = valid_cpu_types;
> sc->silicon_rev = AST2400_A1_SILICON_REV;
> sc->sram_size = 0x8000;
> sc->spis_num = 1;
> @@ -527,6 +531,10 @@ static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data)
>
> static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data)
> {
> + static const char * const valid_cpu_types[] = {
> + ARM_CPU_TYPE_NAME("arm1176"),
> + NULL
> + };
> AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
> DeviceClass *dc = DEVICE_CLASS(oc);
>
> @@ -535,7 +543,7 @@ static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data)
> dc->user_creatable = false;
>
> sc->name = "ast2500-a1";
> - sc->cpu_type = ARM_CPU_TYPE_NAME("arm1176");
> + sc->valid_cpu_types = valid_cpu_types;
> sc->silicon_rev = AST2500_A1_SILICON_REV;
> sc->sram_size = 0x9000;
> sc->spis_num = 2;
> diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
> index b264433cf0..46baba0e41 100644
> --- a/hw/arm/aspeed_ast2600.c
> +++ b/hw/arm/aspeed_ast2600.c
> @@ -629,13 +629,17 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
>
> static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data)
> {
> + static const char * const valid_cpu_types[] = {
> + ARM_CPU_TYPE_NAME("cortex-a7"),
> + NULL
> + };
> DeviceClass *dc = DEVICE_CLASS(oc);
> AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
>
> dc->realize = aspeed_soc_ast2600_realize;
>
> sc->name = "ast2600-a3";
> - sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a7");
> + sc->valid_cpu_types = valid_cpu_types;
> sc->silicon_rev = AST2600_A3_SILICON_REV;
> sc->sram_size = 0x16400;
> sc->spis_num = 2;
> diff --git a/hw/arm/aspeed_soc_common.c b/hw/arm/aspeed_soc_common.c
> index 36ca189ce9..123a0c432c 100644
> --- a/hw/arm/aspeed_soc_common.c
> +++ b/hw/arm/aspeed_soc_common.c
> @@ -20,7 +20,10 @@
>
> const char *aspeed_soc_cpu_type(AspeedSoCClass *sc)
> {
> - return sc->cpu_type;
> + assert(sc->valid_cpu_types);
> + assert(sc->valid_cpu_types[0]);
> + assert(!sc->valid_cpu_types[1]);
> + return sc->valid_cpu_types[0];
> }
>
> qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev)
^ permalink raw reply [flat|nested] 22+ messages in thread* Re: [PATCH v2 5/5] hw/arm/aspeed: Check for CPU types in machine_run_board_init()
2024-01-23 22:48 ` [PATCH v2 5/5] hw/arm/aspeed: Check for CPU types in machine_run_board_init() Philippe Mathieu-Daudé
2024-01-24 6:59 ` Cédric Le Goater
@ 2024-01-24 23:18 ` Richard Henderson
2024-01-25 2:28 ` Gavin Shan
2 siblings, 0 replies; 22+ messages in thread
From: Richard Henderson @ 2024-01-24 23:18 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Peter Maydell, qemu-arm, Joel Stanley, Andrew Jeffery,
Cédric Le Goater
On 1/24/24 08:48, Philippe Mathieu-Daudé wrote:
> Aspeed SoCs use a single CPU type (set as AspeedSoCClass::cpu_type).
> Convert it to a NULL-terminated array (of a single non-NULL element).
>
> Set MachineClass::valid_cpu_types[] to use the common machine code
> to provide hints when the requested CPU is invalid (see commit
> e702cbc19e ("machine: Improve is_cpu_type_supported()").
>
> Signed-off-by: Philippe Mathieu-Daudé<philmd@linaro.org>
> ---
> include/hw/arm/aspeed_soc.h | 3 ++-
> hw/arm/aspeed.c | 1 +
> hw/arm/aspeed_ast10x0.c | 6 +++++-
> hw/arm/aspeed_ast2400.c | 12 ++++++++++--
> hw/arm/aspeed_ast2600.c | 6 +++++-
> hw/arm/aspeed_soc_common.c | 5 ++++-
> 6 files changed, 27 insertions(+), 6 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 22+ messages in thread* Re: [PATCH v2 5/5] hw/arm/aspeed: Check for CPU types in machine_run_board_init()
2024-01-23 22:48 ` [PATCH v2 5/5] hw/arm/aspeed: Check for CPU types in machine_run_board_init() Philippe Mathieu-Daudé
2024-01-24 6:59 ` Cédric Le Goater
2024-01-24 23:18 ` Richard Henderson
@ 2024-01-25 2:28 ` Gavin Shan
2 siblings, 0 replies; 22+ messages in thread
From: Gavin Shan @ 2024-01-25 2:28 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Peter Maydell, qemu-arm, Joel Stanley, Andrew Jeffery,
Cédric Le Goater
On 1/24/24 08:48, Philippe Mathieu-Daudé wrote:
> Aspeed SoCs use a single CPU type (set as AspeedSoCClass::cpu_type).
> Convert it to a NULL-terminated array (of a single non-NULL element).
>
> Set MachineClass::valid_cpu_types[] to use the common machine code
> to provide hints when the requested CPU is invalid (see commit
> e702cbc19e ("machine: Improve is_cpu_type_supported()").
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
> include/hw/arm/aspeed_soc.h | 3 ++-
> hw/arm/aspeed.c | 1 +
> hw/arm/aspeed_ast10x0.c | 6 +++++-
> hw/arm/aspeed_ast2400.c | 12 ++++++++++--
> hw/arm/aspeed_ast2600.c | 6 +++++-
> hw/arm/aspeed_soc_common.c | 5 ++++-
> 6 files changed, 27 insertions(+), 6 deletions(-)
>
Reviewed-by: Gavin Shan <gshan@redhat.com>
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v2 0/5] hw/arm/aspeed: Check for CPU types in machine_run_board_init()
2024-01-23 22:48 [PATCH v2 0/5] hw/arm/aspeed: Check for CPU types in machine_run_board_init() Philippe Mathieu-Daudé
` (4 preceding siblings ...)
2024-01-23 22:48 ` [PATCH v2 5/5] hw/arm/aspeed: Check for CPU types in machine_run_board_init() Philippe Mathieu-Daudé
@ 2024-01-23 22:50 ` Philippe Mathieu-Daudé
5 siblings, 0 replies; 22+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-01-23 22:50 UTC (permalink / raw)
To: qemu-devel, Gavin Shan
Cc: Peter Maydell, qemu-arm, Joel Stanley, Andrew Jeffery,
Cédric Le Goater
+Gavin
On 23/1/24 23:48, Philippe Mathieu-Daudé wrote:
> Since v1:
> - Follow suggestions from Cédric from [*]
>
> [*] https://lore.kernel.org/qemu-devel/e13c655b-7904-4e47-a673-4efd13c26b3d@kaod.org/
>
> Based-on: <20240123222508.13826-1-philmd@linaro.org>
>
> Philippe Mathieu-Daudé (5):
> hw/arm/aspeed: Remove dead code
> hw/arm/aspeed: Set default CPU count using aspeed_soc_num_cpus()
> hw/arm/aspeed: Init CPU defaults in a common helper
> hw/arm/aspeed: Introduce aspeed_soc_cpu_type() helper
> hw/arm/aspeed: Check for CPU types in machine_run_board_init()
>
> include/hw/arm/aspeed_soc.h | 4 ++-
> hw/arm/aspeed.c | 70 +++++++++++++++----------------------
> hw/arm/aspeed_ast10x0.c | 8 +++--
> hw/arm/aspeed_ast2400.c | 15 ++++++--
> hw/arm/aspeed_ast2600.c | 9 +++--
> hw/arm/aspeed_soc_common.c | 8 +++++
> 6 files changed, 65 insertions(+), 49 deletions(-)
>
^ permalink raw reply [flat|nested] 22+ messages in thread