* [PATCH RFC v3 1/3] target/arm: Implement SVE2 AESMC, AESIMC
2020-04-27 21:40 [PATCH RFC v3 0/3] target/arm: Implement SVE2 Crypto Extensions Stephen Long
@ 2020-04-27 21:40 ` Stephen Long
2020-04-27 21:40 ` [PATCH RFC v3 2/3] target/arm: Implement SVE2 AESE, AESD, SM4E Stephen Long
` (2 subsequent siblings)
3 siblings, 0 replies; 5+ messages in thread
From: Stephen Long @ 2020-04-27 21:40 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm, richard.henderson, apazos
Signed-off-by: Stephen Long <steplong@quicinc.com>
---
target/arm/crypto_helper.c | 36 +++++++++++++++++++++---------------
target/arm/sve.decode | 10 ++++++++++
target/arm/translate-sve.c | 20 ++++++++++++++++++++
3 files changed, 51 insertions(+), 15 deletions(-)
diff --git a/target/arm/crypto_helper.c b/target/arm/crypto_helper.c
index f800266727..ae2ea018af 100644
--- a/target/arm/crypto_helper.c
+++ b/target/arm/crypto_helper.c
@@ -14,6 +14,7 @@
#include "cpu.h"
#include "exec/helper-proto.h"
#include "crypto/aes.h"
+#include "tcg/tcg-gvec-desc.h"
union CRYPTO_STATE {
uint8_t bytes[16];
@@ -54,7 +55,7 @@ void HELPER(crypto_aese)(void *vd, void *vm, uint32_t decrypt)
rd[1] = st.l[1];
}
-void HELPER(crypto_aesmc)(void *vd, void *vm, uint32_t decrypt)
+void HELPER(crypto_aesmc)(void *vd, void *vm, uint32_t desc)
{
static uint32_t const mc[][256] = { {
/* MixColumns lookup table */
@@ -190,23 +191,28 @@ void HELPER(crypto_aesmc)(void *vd, void *vm, uint32_t decrypt)
0xbe805d9f, 0xb58d5491, 0xa89a4f83, 0xa397468d,
} };
- uint64_t *rd = vd;
- uint64_t *rm = vm;
- union CRYPTO_STATE st = { .l = { rm[0], rm[1] } };
- int i;
+ intptr_t i, opr_sz = simd_oprsz(desc);
+ intptr_t decrypt = simd_data(desc);
- assert(decrypt < 2);
+ for (i = 0; i < opr_sz; i += 16) {
+ uint64_t *rd = vd + i;
+ uint64_t *rm = vm + i;
+ union CRYPTO_STATE st = { .l = { rm[0], rm[1] } };
+ int i;
- for (i = 0; i < 16; i += 4) {
- CR_ST_WORD(st, i >> 2) =
- mc[decrypt][CR_ST_BYTE(st, i)] ^
- rol32(mc[decrypt][CR_ST_BYTE(st, i + 1)], 8) ^
- rol32(mc[decrypt][CR_ST_BYTE(st, i + 2)], 16) ^
- rol32(mc[decrypt][CR_ST_BYTE(st, i + 3)], 24);
- }
+ assert(decrypt < 2);
- rd[0] = st.l[0];
- rd[1] = st.l[1];
+ for (i = 0; i < 16; i += 4) {
+ CR_ST_WORD(st, i >> 2) =
+ mc[decrypt][CR_ST_BYTE(st, i)] ^
+ rol32(mc[decrypt][CR_ST_BYTE(st, i + 1)], 8) ^
+ rol32(mc[decrypt][CR_ST_BYTE(st, i + 2)], 16) ^
+ rol32(mc[decrypt][CR_ST_BYTE(st, i + 3)], 24);
+ }
+
+ rd[0] = st.l[0];
+ rd[1] = st.l[1];
+ }
}
/*
diff --git a/target/arm/sve.decode b/target/arm/sve.decode
index de3768c24a..f58eb04d11 100644
--- a/target/arm/sve.decode
+++ b/target/arm/sve.decode
@@ -92,6 +92,10 @@
# Named instruction formats. These are generally used to
# reduce the amount of duplication between instruction patterns.
+# One operand with unused vector element size
+@rdn_e0 ........ .. ........... . ..... rd:5 \
+ &rr_esz rn=%reg_movprfx esz=0
+
# Two operand with unused vector element size
@pd_pn_e0 ........ ........ ....... rn:4 . rd:4 &rr_esz esz=0
@@ -1419,3 +1423,9 @@ STNT1_zprz 1110010 .. 00 ..... 001 ... ..... ..... \
# SVE2 32-bit scatter non-temporal store (vector plus scalar)
STNT1_zprz 1110010 .. 10 ..... 001 ... ..... ..... \
@rprr_scatter_store xs=0 esz=2 scale=0
+
+#### SVE2 Crypto Extensions
+
+## SVE2 crypto unary operations
+AESMC 01000101 00 10000011100 0 00000 ..... @rdn_e0
+AESIMC 01000101 00 10000011100 1 00000 ..... @rdn_e0
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index 86c3d0ed11..6523621d21 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -7956,3 +7956,23 @@ static bool trans_SQRDCMLAH_zzzz(DisasContext *s, arg_CMLA_zzzz *a)
};
return do_sve2_zzzz_fn(s, a->rd, a->rn, a->rm, a->ra, fns[a->esz], a->rot);
}
+
+#define DO_SVE2_AES_CRYPTO(NAME, name, DECRYPT) \
+static bool trans_##NAME(DisasContext *s, arg_rr_esz *a) \
+{ \
+ if (!dc_isar_feature(aa64_sve2_aes, s)) { \
+ return false; \
+ } \
+ if (sve_access_check(s)) { \
+ unsigned vsz = vec_full_reg_size(s); \
+ tcg_gen_gvec_2_ool(vec_full_reg_offset(s, a->rd), \
+ vec_full_reg_offset(s, a->rn), \
+ vsz, vsz, DECRYPT, gen_helper_crypto_##name);\
+ } \
+ return true; \
+}
+
+DO_SVE2_AES_CRYPTO(AESMC, aesmc, 0)
+DO_SVE2_AES_CRYPTO(AESIMC, aesmc, 1)
+DO_SVE2_AES_CRYPTO(AESE, aese, 0)
+DO_SVE2_AES_CRYPTO(AESD, aese, 1)
--
2.17.1
^ permalink raw reply related [flat|nested] 5+ messages in thread* [PATCH RFC v3 2/3] target/arm: Implement SVE2 AESE, AESD, SM4E
2020-04-27 21:40 [PATCH RFC v3 0/3] target/arm: Implement SVE2 Crypto Extensions Stephen Long
2020-04-27 21:40 ` [PATCH RFC v3 1/3] target/arm: Implement SVE2 AESMC, AESIMC Stephen Long
@ 2020-04-27 21:40 ` Stephen Long
2020-04-27 21:40 ` [PATCH RFC v3 3/3] target/arm: Implement SVE2 SM4EKEY, RAX1 Stephen Long
2020-06-16 18:19 ` [PATCH RFC v3 0/3] target/arm: Implement SVE2 Crypto Extensions Richard Henderson
3 siblings, 0 replies; 5+ messages in thread
From: Stephen Long @ 2020-04-27 21:40 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm, richard.henderson, apazos
Signed-off-by: Stephen Long <steplong@quicinc.com>
---
target/arm/cpu.h | 5 +++++
target/arm/crypto_helper.c | 38 ++++++++++++++++++++++----------------
target/arm/helper-sve.h | 2 ++
target/arm/sve.decode | 6 ++++++
target/arm/sve_helper.c | 8 ++++++++
target/arm/translate-sve.c | 14 ++++++++++++++
6 files changed, 57 insertions(+), 16 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index d41c4a08c0..8b1dc38b9c 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3880,6 +3880,11 @@ static inline bool isar_feature_aa64_sve2_f64mm(const ARMISARegisters *id)
return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, F64MM) != 0;
}
+static inline bool isar_feature_aa64_sve2_sm4(const ARMISARegisters *id)
+{
+ return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SM4) != 0;
+}
+
/*
* Feature tests for "does this exist in either 32-bit or 64-bit?"
*/
diff --git a/target/arm/crypto_helper.c b/target/arm/crypto_helper.c
index ae2ea018af..45740c1bfd 100644
--- a/target/arm/crypto_helper.c
+++ b/target/arm/crypto_helper.c
@@ -30,29 +30,35 @@ union CRYPTO_STATE {
#define CR_ST_WORD(state, i) (state.words[i])
#endif
-void HELPER(crypto_aese)(void *vd, void *vm, uint32_t decrypt)
+void HELPER(crypto_aese)(void *vd, void *vm, uint32_t desc)
{
static uint8_t const * const sbox[2] = { AES_sbox, AES_isbox };
static uint8_t const * const shift[2] = { AES_shifts, AES_ishifts };
- uint64_t *rd = vd;
- uint64_t *rm = vm;
- union CRYPTO_STATE rk = { .l = { rm[0], rm[1] } };
- union CRYPTO_STATE st = { .l = { rd[0], rd[1] } };
- int i;
- assert(decrypt < 2);
+ intptr_t i, opr_sz = simd_oprsz(desc);
+ intptr_t decrypt = simd_data(desc);
- /* xor state vector with round key */
- rk.l[0] ^= st.l[0];
- rk.l[1] ^= st.l[1];
+ for (i = 0; i < opr_sz; i += 16) {
+ uint64_t *rd = vd + i;
+ uint64_t *rm = vm + i;
+ union CRYPTO_STATE rk = { .l = { rm[0], rm[1] } };
+ union CRYPTO_STATE st = { .l = { rd[0], rd[1] } };
+ int i;
- /* combine ShiftRows operation and sbox substitution */
- for (i = 0; i < 16; i++) {
- CR_ST_BYTE(st, i) = sbox[decrypt][CR_ST_BYTE(rk, shift[decrypt][i])];
- }
+ assert(decrypt < 2);
+
+ /* xor state vector with round key */
+ rk.l[0] ^= st.l[0];
+ rk.l[1] ^= st.l[1];
+
+ /* combine ShiftRows operation and sbox substitution */
+ for (i = 0; i < 16; i++) {
+ CR_ST_BYTE(st, i) = sbox[decrypt][CR_ST_BYTE(rk, shift[decrypt][i])];
+ }
- rd[0] = st.l[0];
- rd[1] = st.l[1];
+ rd[0] = st.l[0];
+ rd[1] = st.l[1];
+ }
}
void HELPER(crypto_aesmc)(void *vd, void *vm, uint32_t desc)
diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h
index 51ad60e5c3..7eef4eb476 100644
--- a/target/arm/helper-sve.h
+++ b/target/arm/helper-sve.h
@@ -2690,3 +2690,5 @@ DEF_HELPER_FLAGS_5(sve2_sqrdcmlah_zzzz_d, TCG_CALL_NO_RWG,
DEF_HELPER_FLAGS_6(fmmla_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_6(fmmla_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_3(sve2_sm4e, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
diff --git a/target/arm/sve.decode b/target/arm/sve.decode
index f58eb04d11..1cb5792bb1 100644
--- a/target/arm/sve.decode
+++ b/target/arm/sve.decode
@@ -98,6 +98,7 @@
# Two operand with unused vector element size
@pd_pn_e0 ........ ........ ....... rn:4 . rd:4 &rr_esz esz=0
+@pd5_pn5_e0 ........ ........ ...... rn:5 rd:5 &rr_esz esz=0
# Two operand
@pd_pn ........ esz:2 .. .... ....... rn:4 . rd:4 &rr_esz
@@ -1429,3 +1430,8 @@ STNT1_zprz 1110010 .. 10 ..... 001 ... ..... ..... \
## SVE2 crypto unary operations
AESMC 01000101 00 10000011100 0 00000 ..... @rdn_e0
AESIMC 01000101 00 10000011100 1 00000 ..... @rdn_e0
+
+## SVE2 crpyto destructive binary operations
+AESE 01000101 00 10001 0 11100 0 ..... ..... @pd5_pn5_e0
+AESD 01000101 00 10001 0 11100 1 ..... ..... @pd5_pn5_e0
+SM4E 01000101 00 10001 1 11100 0 ..... ..... @pd5_pn5_e0
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
index cd5c6f7fb0..b3a7594981 100644
--- a/target/arm/sve_helper.c
+++ b/target/arm/sve_helper.c
@@ -7516,3 +7516,11 @@ void HELPER(fmmla_d)(void *vd, void *va, void *vn, void *vm,
d[3] = float64_add(a[3], float64_add(p0, p1, status), status);
}
}
+
+void HELPER(sve2_sm4e)(void *vd, void *vn, uint32_t desc)
+{
+ intptr_t i, opr_sz = simd_oprsz(desc);
+ for (i = 0; i < opr_sz; i += 16) {
+ HELPER(crypto_sm4e)(vd + i, vn + i);
+ }
+}
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index 6523621d21..4253955471 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -7976,3 +7976,17 @@ DO_SVE2_AES_CRYPTO(AESMC, aesmc, 0)
DO_SVE2_AES_CRYPTO(AESIMC, aesmc, 1)
DO_SVE2_AES_CRYPTO(AESE, aese, 0)
DO_SVE2_AES_CRYPTO(AESD, aese, 1)
+
+static bool trans_SM4E(DisasContext *s, arg_rr_esz *a)
+{
+ if (!dc_isar_feature(aa64_sve2_sm4, s)) {
+ return false;
+ }
+ if (sve_access_check(s)) {
+ unsigned vsz = vec_full_reg_size(s);
+ tcg_gen_gvec_2_ool(vec_full_reg_offset(s, a->rd),
+ vec_full_reg_offset(s, a->rn),
+ vsz, vsz, 0, gen_helper_sve2_sm4e);
+ }
+ return true;
+}
--
2.17.1
^ permalink raw reply related [flat|nested] 5+ messages in thread* [PATCH RFC v3 3/3] target/arm: Implement SVE2 SM4EKEY, RAX1
2020-04-27 21:40 [PATCH RFC v3 0/3] target/arm: Implement SVE2 Crypto Extensions Stephen Long
2020-04-27 21:40 ` [PATCH RFC v3 1/3] target/arm: Implement SVE2 AESMC, AESIMC Stephen Long
2020-04-27 21:40 ` [PATCH RFC v3 2/3] target/arm: Implement SVE2 AESE, AESD, SM4E Stephen Long
@ 2020-04-27 21:40 ` Stephen Long
2020-06-16 18:19 ` [PATCH RFC v3 0/3] target/arm: Implement SVE2 Crypto Extensions Richard Henderson
3 siblings, 0 replies; 5+ messages in thread
From: Stephen Long @ 2020-04-27 21:40 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm, richard.henderson, apazos
Signed-off-by: Stephen Long <steplong@quicinc.com>
---
target/arm/crypto_helper.c | 12 ++++++++++++
target/arm/helper-sve.h | 1 +
target/arm/helper.h | 2 ++
target/arm/sve.decode | 4 ++++
target/arm/sve_helper.c | 8 ++++++++
target/arm/translate-sve.c | 30 ++++++++++++++++++++++++++++++
6 files changed, 57 insertions(+)
diff --git a/target/arm/crypto_helper.c b/target/arm/crypto_helper.c
index 45740c1bfd..0720b3b98f 100644
--- a/target/arm/crypto_helper.c
+++ b/target/arm/crypto_helper.c
@@ -705,3 +705,15 @@ void HELPER(crypto_sm4ekey)(void *vd, void *vn, void* vm)
rd[0] = d.l[0];
rd[1] = d.l[1];
}
+
+void HELPER(crypto_rax1)(void *vd, void *vn, void *vm, uint32_t desc)
+{
+ intptr_t i, opr_sz = simd_oprsz(desc) / 8;
+ uint64_t *d = vd, *n = vn, *m = vm;
+
+ for (i = 0; i < opr_sz; ++i) {
+ uint64_t nn = n[i];
+ uint64_t mm = m[i];
+ d[i] = nn ^ rol64(mm, 1);
+ }
+}
diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h
index 7eef4eb476..059003c26e 100644
--- a/target/arm/helper-sve.h
+++ b/target/arm/helper-sve.h
@@ -2692,3 +2692,4 @@ DEF_HELPER_FLAGS_6(fmmla_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_6(fmmla_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(sve2_sm4e, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(sve2_sm4ekey, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
diff --git a/target/arm/helper.h b/target/arm/helper.h
index 37f489412c..c74cea76a2 100644
--- a/target/arm/helper.h
+++ b/target/arm/helper.h
@@ -537,6 +537,8 @@ DEF_HELPER_FLAGS_3(crypto_sm3partw2, TCG_CALL_NO_RWG, void, ptr, ptr, ptr)
DEF_HELPER_FLAGS_2(crypto_sm4e, TCG_CALL_NO_RWG, void, ptr, ptr)
DEF_HELPER_FLAGS_3(crypto_sm4ekey, TCG_CALL_NO_RWG, void, ptr, ptr, ptr)
+DEF_HELPER_FLAGS_4(crypto_rax1, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+
DEF_HELPER_FLAGS_3(crc32, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32)
DEF_HELPER_FLAGS_3(crc32c, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32)
diff --git a/target/arm/sve.decode b/target/arm/sve.decode
index 1cb5792bb1..278530ca83 100644
--- a/target/arm/sve.decode
+++ b/target/arm/sve.decode
@@ -1435,3 +1435,7 @@ AESIMC 01000101 00 10000011100 1 00000 ..... @rdn_e0
AESE 01000101 00 10001 0 11100 0 ..... ..... @pd5_pn5_e0
AESD 01000101 00 10001 0 11100 1 ..... ..... @pd5_pn5_e0
SM4E 01000101 00 10001 1 11100 0 ..... ..... @pd5_pn5_e0
+
+## SVE2 crypto constructive binary operations
+SM4EKEY 01000101 00 1 ..... 11110 0 ..... ..... @rd_rn_rm_e0
+RAX1 01000101 00 1 ..... 11110 1 ..... ..... @rd_rn_rm_e0
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
index b3a7594981..3b560e702a 100644
--- a/target/arm/sve_helper.c
+++ b/target/arm/sve_helper.c
@@ -7524,3 +7524,11 @@ void HELPER(sve2_sm4e)(void *vd, void *vn, uint32_t desc)
HELPER(crypto_sm4e)(vd + i, vn + i);
}
}
+
+void HELPER(sve2_sm4ekey)(void *vd, void *vn, void *vm, uint32_t desc)
+{
+ intptr_t i, opr_sz = simd_oprsz(desc);
+ for (i = 0; i < opr_sz; i += 16) {
+ HELPER(crypto_sm4ekey)(vd + i, vn + i, vm + i);
+ }
+}
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index 4253955471..affe41779b 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -7990,3 +7990,33 @@ static bool trans_SM4E(DisasContext *s, arg_rr_esz *a)
}
return true;
}
+
+static bool trans_SM4EKEY(DisasContext *s, arg_rrr_esz *a)
+{
+ if (!dc_isar_feature(aa64_sve2_sm4, s)) {
+ return false;
+ }
+ if (sve_access_check(s)) {
+ unsigned vsz = vec_full_reg_size(s);
+ tcg_gen_gvec_3_ool(vec_full_reg_offset(s, a->rd),
+ vec_full_reg_offset(s, a->rn),
+ vec_full_reg_offset(s, a->rm),
+ vsz, vsz, 0, gen_helper_sve2_sm4ekey);
+ }
+ return true;
+}
+
+static bool trans_RAX1(DisasContext *s, arg_rrr_esz *a)
+{
+ if (!dc_isar_feature(aa64_sve2_sm4, s)) {
+ return false;
+ }
+ if (sve_access_check(s)) {
+ unsigned vsz = vec_full_reg_size(s);
+ tcg_gen_gvec_3_ool(vec_full_reg_offset(s, a->rd),
+ vec_full_reg_offset(s, a->rn),
+ vec_full_reg_offset(s, a->rm),
+ vsz, vsz, 0, gen_helper_crypto_rax1);
+ }
+ return true;
+}
--
2.17.1
^ permalink raw reply related [flat|nested] 5+ messages in thread* Re: [PATCH RFC v3 0/3] target/arm: Implement SVE2 Crypto Extensions
2020-04-27 21:40 [PATCH RFC v3 0/3] target/arm: Implement SVE2 Crypto Extensions Stephen Long
` (2 preceding siblings ...)
2020-04-27 21:40 ` [PATCH RFC v3 3/3] target/arm: Implement SVE2 SM4EKEY, RAX1 Stephen Long
@ 2020-06-16 18:19 ` Richard Henderson
3 siblings, 0 replies; 5+ messages in thread
From: Richard Henderson @ 2020-06-16 18:19 UTC (permalink / raw)
To: Stephen Long, qemu-devel; +Cc: qemu-arm, apazos
On 4/27/20 2:40 PM, Stephen Long wrote:
> Modified some of the crypto functions in crypto_helper.c to take in a
> desc parameter.
>
> Didn't add a desc parameter to SM4E and SM4EKEY since it is used in
> translate-a64.c and the functions in there need crypto_sm4e and
> crypto_sm4ekey to stay the same type (i.e. take 2 or 3 parameters)
>
> Stephen Long (3):
> target/arm: Implement SVE2 AESMC, AESIMC
> target/arm: Implement SVE2 AESE, AESD, SM4E
> target/arm: Implement SVE2 SM4EKEY, RAX1
In the end I took care of these insns myself, after rearranging the AdvSIMD
helpers.
r~
^ permalink raw reply [flat|nested] 5+ messages in thread