* [PATCH] target/arm: Fix alignment for VLD4.32
@ 2022-09-14 10:50 Clément Chigot
2022-09-14 13:11 ` Richard Henderson
0 siblings, 1 reply; 3+ messages in thread
From: Clément Chigot @ 2022-09-14 10:50 UTC (permalink / raw)
To: qemu-arm; +Cc: qemu-devel, peter.maydell, Clément Chigot
When requested, the alignment for VLD4.32 is 8 and not 16.
See ARM documentation about VLD4 encoding:
ebytes = 1 << UInt(size);
if size == '10' then
alignment = if a == '0' then 1 else 8;
else
alignment = if a == '0' then 1 else 4*ebytes;
Signed-off-by: Clément Chigot <chigot@adacore.com>
---
target/arm/translate-neon.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/target/arm/translate-neon.c b/target/arm/translate-neon.c
index 321c17e2c7..4016339d46 100644
--- a/target/arm/translate-neon.c
+++ b/target/arm/translate-neon.c
@@ -584,7 +584,11 @@ static bool trans_VLD_all_lanes(DisasContext *s, arg_VLD_all_lanes *a)
case 3:
return false;
case 4:
- align = pow2_align(size + 2);
+ if (size == 2) {
+ align = pow2_align(3);
+ } else {
+ align = pow2_align(size + 2);
+ }
break;
default:
g_assert_not_reached();
--
2.25.1
^ permalink raw reply related [flat|nested] 3+ messages in thread* Re: [PATCH] target/arm: Fix alignment for VLD4.32
2022-09-14 10:50 [PATCH] target/arm: Fix alignment for VLD4.32 Clément Chigot
@ 2022-09-14 13:11 ` Richard Henderson
2022-09-20 10:24 ` Peter Maydell
0 siblings, 1 reply; 3+ messages in thread
From: Richard Henderson @ 2022-09-14 13:11 UTC (permalink / raw)
To: Clément Chigot, qemu-arm; +Cc: qemu-devel, peter.maydell
On 9/14/22 11:50, Clément Chigot wrote:
> When requested, the alignment for VLD4.32 is 8 and not 16.
>
> See ARM documentation about VLD4 encoding:
> ebytes = 1 << UInt(size);
> if size == '10' then
> alignment = if a == '0' then 1 else 8;
> else
> alignment = if a == '0' then 1 else 4*ebytes;
>
> Signed-off-by: Clément Chigot <chigot@adacore.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
> ---
> target/arm/translate-neon.c | 6 +++++-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/target/arm/translate-neon.c b/target/arm/translate-neon.c
> index 321c17e2c7..4016339d46 100644
> --- a/target/arm/translate-neon.c
> +++ b/target/arm/translate-neon.c
> @@ -584,7 +584,11 @@ static bool trans_VLD_all_lanes(DisasContext *s, arg_VLD_all_lanes *a)
> case 3:
> return false;
> case 4:
> - align = pow2_align(size + 2);
> + if (size == 2) {
> + align = pow2_align(3);
> + } else {
> + align = pow2_align(size + 2);
> + }
> break;
> default:
> g_assert_not_reached();
^ permalink raw reply [flat|nested] 3+ messages in thread* Re: [PATCH] target/arm: Fix alignment for VLD4.32
2022-09-14 13:11 ` Richard Henderson
@ 2022-09-20 10:24 ` Peter Maydell
0 siblings, 0 replies; 3+ messages in thread
From: Peter Maydell @ 2022-09-20 10:24 UTC (permalink / raw)
To: Richard Henderson; +Cc: Clément Chigot, qemu-arm, qemu-devel
On Wed, 14 Sept 2022 at 14:11, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> On 9/14/22 11:50, Clément Chigot wrote:
> > When requested, the alignment for VLD4.32 is 8 and not 16.
> >
> > See ARM documentation about VLD4 encoding:
> > ebytes = 1 << UInt(size);
> > if size == '10' then
> > alignment = if a == '0' then 1 else 8;
> > else
> > alignment = if a == '0' then 1 else 4*ebytes;
> >
> > Signed-off-by: Clément Chigot <chigot@adacore.com>
>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Applied to target-arm.next, thanks.
-- PMM
^ permalink raw reply [flat|nested] 3+ messages in thread
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2022-09-14 10:50 [PATCH] target/arm: Fix alignment for VLD4.32 Clément Chigot
2022-09-14 13:11 ` Richard Henderson
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