From: Richard Henderson <richard.henderson@linaro.org>
To: Vitaly Chikunov <vt@altlinux.org>,
David Gibson <david@gibson.dropbear.id.au>,
Alexander Graf <agraf@suse.de>,
qemu-ppc@nongnu.org, qemu-devel@nongnu.org
Cc: qemu-stable@nongnu.org
Subject: Re: [PATCH] target/ppc: Fix rlwinm on ppc64
Date: Mon, 9 Mar 2020 21:13:05 -0700 [thread overview]
Message-ID: <dbf91244-ad5d-0d3b-7c0b-e11a6e0192a2@linaro.org> (raw)
In-Reply-To: <20200309204557.14836-1-vt@altlinux.org>
On 3/9/20 1:45 PM, Vitaly Chikunov wrote:
> rlwinm cannot just AND with Mask if shift value is zero on ppc64 when
> Mask Begin is greater than Mask End and high bits are set to 1.
>
> Note that PowerISA 3.0B says that for `rlwinm' ROTL32 is used, and
> ROTL32 is defined (in 3.3.14) so that rotated value should have two
> copies of lower word of the source value.
>
> This seems to be another incarnation of the fix from 820724d170
> ("target-ppc: Fix rlwimi, rlwinm, rlwnm again"), except I leave
> optimization when Mask value is less than 32 bits.
>
> Fixes: 7b4d326f47 ("target-ppc: Use the new deposit and extract ops")
> Cc: qemu-stable@nongnu.org
> Signed-off-by: Vitaly Chikunov <vt@altlinux.org>
> ---
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
next prev parent reply other threads:[~2020-03-10 4:14 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-09 20:45 [PATCH] target/ppc: Fix rlwinm on ppc64 Vitaly Chikunov
2020-03-09 22:15 ` no-reply
2020-03-10 2:34 ` David Gibson
2020-03-10 4:13 ` Richard Henderson [this message]
2020-03-10 23:15 ` David Gibson
2020-03-11 13:00 ` Vitaly Chikunov
2020-03-16 2:57 ` David Gibson
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