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[47.64.112.84]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-4b2b8c885e4sm51227731cf.13.2025.08.25.04.58.44 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 25 Aug 2025 04:58:47 -0700 (PDT) Message-ID: Date: Mon, 25 Aug 2025 13:58:42 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/4] target/ppc: Add IBM PPE42 family of processors To: Harsh Prateek Bora , Glenn Miles , qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, clg@redhat.com, npiggin@gmail.com, rathc@linux.ibm.com, richard.henderson@linaro.org, =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= , Pierrick Bouvier References: <20250819212856.219932-1-milesg@linux.ibm.com> <20250819212856.219932-2-milesg@linux.ibm.com> <0d2c9aa2-2dcc-4c22-8f33-e5ecac907cf4@linux.ibm.com> From: Thomas Huth Content-Language: en-US Autocrypt: addr=thuth@redhat.com; keydata= xsFNBFH7eUwBEACzyOXKU+5Pcs6wNpKzrlJwzRl3VGZt95VCdb+FgoU9g11m7FWcOafrVRwU yYkTm9+7zBUc0sW5AuPGR/dp3pSLX/yFWsA/UB4nJsHqgDvDU7BImSeiTrnpMOTXb7Arw2a2 4CflIyFqjCpfDM4MuTmzTjXq4Uov1giGE9X6viNo1pxyEpd7PanlKNnf4PqEQp06X4IgUacW tSGj6Gcns1bCuHV8OPWLkf4hkRnu8hdL6i60Yxz4E6TqlrpxsfYwLXgEeswPHOA6Mn4Cso9O 0lewVYfFfsmokfAVMKWzOl1Sr0KGI5T9CpmRfAiSHpthhHWnECcJFwl72NTi6kUcUzG4se81 O6n9d/kTj7pzTmBdfwuOZ0YUSqcqs0W+l1NcASSYZQaDoD3/SLk+nqVeCBB4OnYOGhgmIHNW 0CwMRO/GK+20alxzk//V9GmIM2ACElbfF8+Uug3pqiHkVnKqM7W9/S1NH2qmxB6zMiJUHlTH gnVeZX0dgH27mzstcF786uPcdEqS0KJuxh2kk5IvUSL3Qn3ZgmgdxBMyCPciD/1cb7/Ahazr 3ThHQXSHXkH/aDXdfLsKVuwDzHLVSkdSnZdt5HHh75/NFHxwaTlydgfHmFFwodK8y/TjyiGZ zg2Kje38xnz8zKn9iesFBCcONXS7txENTzX0z80WKBhK+XSFJwARAQABzR5UaG9tYXMgSHV0 aCA8dGh1dGhAcmVkaGF0LmNvbT7CwXgEEwECACIFAlVgX6oCGwMGCwkIBwMCBhUIAgkKCwQW AgMBAh4BAheAAAoJEC7Z13T+cC21EbIP/ii9cvT2HHGbFRl8HqGT6+7Wkb+XLMqJBMAIGiQK QIP3xk1HPTsLfVG0ao4hy/oYkGNOP8+ubLnZen6Yq3zAFiMhQ44lvgigDYJo3Ve59gfe99KX EbtB+X95ODARkq0McR6OAsPNJ7gpEUzfkQUUJTXRDQXfG/FX303Gvk+YU0spm2tsIKPl6AmV 1CegDljzjycyfJbk418MQmMu2T82kjrkEofUO2a24ed3VGC0/Uz//XCR2ZTo+vBoBUQl41BD eFFtoCSrzo3yPFS+w5fkH9NT8ChdpSlbNS32NhYQhJtr9zjWyFRf0Zk+T/1P7ECn6gTEkp5k ofFIA4MFBc/fXbaDRtBmPB0N9pqTFApIUI4vuFPPO0JDrII9dLwZ6lO9EKiwuVlvr1wwzsgq zJTPBU3qHaUO4d/8G+gD7AL/6T4zi8Jo/GmjBsnYaTzbm94lf0CjXjsOX3seMhaE6WAZOQQG tZHAO1kAPWpaxne+wtgMKthyPLNwelLf+xzGvrIKvLX6QuLoWMnWldu22z2ICVnLQChlR9d6 WW8QFEpo/FK7omuS8KvvopFcOOdlbFMM8Y/8vBgVMSsK6fsYUhruny/PahprPbYGiNIhKqz7 UvgyZVl4pBFjTaz/SbimTk210vIlkDyy1WuS8Zsn0htv4+jQPgo9rqFE4mipJjy/iboDzsFN BFH7eUwBEAC2nzfUeeI8dv0C4qrfCPze6NkryUflEut9WwHhfXCLjtvCjnoGqFelH/PE9NF4 4VPSCdvD1SSmFVzu6T9qWdcwMSaC+e7G/z0/AhBfqTeosAF5XvKQlAb9ZPkdDr7YN0a1XDfa +NgA+JZB4ROyBZFFAwNHT+HCnyzy0v9Sh3BgJJwfpXHH2l3LfncvV8rgFv0bvdr70U+On2XH 5bApOyW1WpIG5KPJlDdzcQTyptOJ1dnEHfwnABEfzI3dNf63rlxsGouX/NFRRRNqkdClQR3K gCwciaXfZ7ir7fF0u1N2UuLsWA8Ei1JrNypk+MRxhbvdQC4tyZCZ8mVDk+QOK6pyK2f4rMf/ WmqxNTtAVmNuZIwnJdjRMMSs4W4w6N/bRvpqtykSqx7VXcgqtv6eqoDZrNuhGbekQA0sAnCJ VPArerAZGArm63o39me/bRUQeQVSxEBmg66yshF9HkcUPGVeC4B0TPwz+HFcVhheo6hoJjLq knFOPLRj+0h+ZL+D0GenyqD3CyuyeTT5dGcNU9qT74bdSr20k/CklvI7S9yoQje8BeQAHtdV cvO8XCLrpGuw9SgOS7OP5oI26a0548M4KldAY+kqX6XVphEw3/6U1KTf7WxW5zYLTtadjISB X9xsRWSU+Yqs3C7oN5TIPSoj9tXMoxZkCIHWvnqGwZ7JhwARAQABwsFfBBgBAgAJBQJR+3lM AhsMAAoJEC7Z13T+cC21hPAQAIsBL9MdGpdEpvXs9CYrBkd6tS9mbaSWj6XBDfA1AEdQkBOn ZH1Qt7HJesk+qNSnLv6+jP4VwqK5AFMrKJ6IjE7jqgzGxtcZnvSjeDGPF1h2CKZQPpTw890k fy18AvgFHkVk2Oylyexw3aOBsXg6ukN44vIFqPoc+YSU0+0QIdYJp/XFsgWxnFIMYwDpxSHS 5fdDxUjsk3UBHZx+IhFjs2siVZi5wnHIqM7eK9abr2cK2weInTBwXwqVWjsXZ4tq5+jQrwDK cvxIcwXdUTLGxc4/Z/VRH1PZSvfQxdxMGmNTGaXVNfdFZjm4fz0mz+OUi6AHC4CZpwnsliGV ODqwX8Y1zic9viSTbKS01ZNp175POyWViUk9qisPZB7ypfSIVSEULrL347qY/hm9ahhqmn17 Ng255syASv3ehvX7iwWDfzXbA0/TVaqwa1YIkec+/8miicV0zMP9siRcYQkyTqSzaTFBBmqD oiT+z+/E59qj/EKfyce3sbC9XLjXv3mHMrq1tKX4G7IJGnS989E/fg6crv6NHae9Ckm7+lSs IQu4bBP2GxiRQ+NV3iV/KU3ebMRzqIC//DCOxzQNFNJAKldPe/bKZMCxEqtVoRkuJtNdp/5a yXFZ6TfE1hGKrDBYAm4vrnZ4CXFSBDllL59cFFOJCkn4Xboj/aVxxJxF30bn In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=170.10.133.124; envelope-from=thuth@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, T_SPF_TEMPERROR=0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 25/08/2025 13.46, Harsh Prateek Bora wrote: > Hi Thomas, > > On 8/25/25 17:04, Thomas Huth wrote: >> On 25/08/2025 13.24, Harsh Prateek Bora wrote: >>> Hi Glenn, >>> >>> This seems significant work. Thanks for upstreaming. >>> >>> On 8/20/25 02:58, Glenn Miles wrote: >>>> Adds the IBM PPE42 family of processors supporting the >>> >>> family of 32-bit processors ? >>> >>>> PPE42, PPE42X and PPE42XM processor versions.  These >>>> processors are used as embedded processors in the IBM >>>> Power9, Power10 and Power12 processors for various >>>> tasks.  It is basically a stripped down version of the >>>> IBM PowerPC 405 processor, with some added instructions >>>> for handling 64-bit loads and stores. >>>> >>>> For more information on the PPE 42 processor please visit: >>>> >>>> https://wiki.raptorcs.com/w/images/a/a3/PPE_42X_Core_Users_Manual.pdf >>>> >>>> Supports PPE42 SPR's (Including the MSR) and  Exceptions. >>>> >>>> Does not yet support new PPE42 instructions and does not >>>> prevent access to some invalid instructions and registers >>>> (currently allows for access to invalid GPR's and CR fields). >>>> >>>> Signed-off-by: Glenn Miles >>>> --- >>>>   target/ppc/cpu-models.c      |   7 + >>>>   target/ppc/cpu-models.h      |   4 + >>>>   target/ppc/cpu.h             |  66 +++++++- >>>>   target/ppc/cpu_init.c        | 286 ++++++++++++++++++++++++++++++----- >>>>   target/ppc/excp_helper.c     | 171 +++++++++++++++++++++ >>>>   target/ppc/helper_regs.c     |  28 +++- >>>>   target/ppc/tcg-excp_helper.c |  12 ++ >>>>   target/ppc/translate.c       |   6 +- >>>>   8 files changed, 535 insertions(+), 45 deletions(-) >>>> >>>> diff --git a/target/ppc/cpu-models.c b/target/ppc/cpu-models.c >>>> index ea86ea202a..09f73e23a8 100644 >>>> --- a/target/ppc/cpu-models.c >>>> +++ b/target/ppc/cpu-models.c >>>> @@ -116,6 +116,13 @@ >>>>                   NULL) >>>>       POWERPC_DEF("x2vp20", CPU_POWERPC_X2VP20,                 405, >>>>                   NULL) >>>> +    /* PPE42 Embedded >>>> Controllers                                            */ >>>> +    POWERPC_DEF("PPE42",         CPU_POWERPC_PPE42, ppe42, >>>> +                "Generic PPE 42") >>>> +    POWERPC_DEF("PPE42X",        CPU_POWERPC_PPE42X, ppe42x, >>>> +                "Generic PPE 42X") >>>> +    POWERPC_DEF("PPE42XM",       CPU_POWERPC_PPE42XM, ppe42xm, >>>> +                "Generic PPE 42XM") >>> >>> Can all the PPE42 specific code be conditionally compiled only for >>> !TARGET_PPC64 (and !CONFIG_USER_ONLY wherever possible)? >>> Not only to reduce the bloating size of respective binaries, but also to >>> avoid some code being added to hot path routines like >>> hreg_compute_hflags_value(). >> >> qemu-system-ppc64 is a superset of qemu-system-ppc, and there are even >> efforts to unify all system functionality into a singly binary, so >> excluding a 32-bit feature from qemu-system-ppc64 sounds like a step into >> the wrong direction to me right now...? > > We do have existing code getting conditionally compiled for TARGET_PPC64 > which I guess gets enabled with: >  --configure target-list=-softmmu > I understand the efforts are towards having a single binary to support > both, but what gets built-in is still decided with configure choice? > > Please correct/clarify with above understanding. As I said, qemu-system-ppc64 is currently a full superset of qemu-system-ppc. The ppc64 binary contains all the 32-bit code, you can perfectly run a "g3beige" or "bamboo" machine with qemu-system-ppc64, too. By disabling the ppe42 code in the ppc64 binary, this would now introduce an execption to that unwritten rule, so I'd expect that we'd not rather want to do this now. Thomas