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[173.198.77.219]) by smtp.gmail.com with ESMTPSA id gz8-20020a17090b0ec800b002343e59709asm3096432pjb.46.2023.02.17.19.46.22 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 17 Feb 2023 19:46:23 -0800 (PST) Message-ID: Date: Fri, 17 Feb 2023 17:46:20 -1000 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.7.1 Subject: Re: [PATCH v6 3/4] target/riscv: implement Zicbom extension Content-Language: en-US To: Daniel Henrique Barboza , qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, Christoph Muellner , Philipp Tomsich References: <20230217203445.51077-1-dbarboza@ventanamicro.com> <20230217203445.51077-4-dbarboza@ventanamicro.com> From: Richard Henderson In-Reply-To: <20230217203445.51077-4-dbarboza@ventanamicro.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -23 X-Spam_score: -2.4 X-Spam_bar: -- X-Spam_report: (-2.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.256, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 2/17/23 10:34, Daniel Henrique Barboza wrote: > + /* > + * Section 2.5.2 of cmobase v1.0.1: > + * > + * "A cache-block management instruction is permitted to > + * access the specified cache block whenever a load instruction > + * or store instruction is permitted to access the corresponding > + * physical addresses. If neither a load instruction nor store > + * instruction is permitted to access the physical addresses, > + * but an instruction fetch is permitted to access the physical > + * addresses, whether a cache-block management instruction is > + * permitted to access the cache block is UNSPECIFIED. > + * > + * This means we have to make a choice of whether checking > + * MMU_INST_FETCH is worth it or not. We'll go the easier > + * route and check MMU_DATA_LOAD and MMU_DATA_STORE only. > + */ > + ret = probe_access_range_flags(env, address, cbomlen, > + MMU_DATA_LOAD, > + mmu_idx, true, &phost, ra); > + > + if (ret == TLB_INVALID_MASK) { > + probe_access_range_flags(env, address, cbomlen, > + MMU_DATA_STORE, > + mmu_idx, true, &phost, ra); > + } Not correct, at minimum for discarding the result of the second call. But I suggested a different ordering of operations which avoid a third probe. r~