From: "Philippe Mathieu-Daudé" <philmd@redhat.com>
To: Peter Maydell <peter.maydell@linaro.org>,
Prasad J Pandit <pjp@redhat.com>
Cc: Prasad J Pandit <pjp@fedoraproject.org>, qemu-devel@nongnu.org
Subject: Re: [PULL 00/21] target-arm queue
Date: Wed, 3 Feb 2021 10:22:03 +0100 [thread overview]
Message-ID: <dc90c90a-b9fd-d89c-629a-e588c47d9953@redhat.com> (raw)
In-Reply-To: <20210202175517.28729-1-peter.maydell@linaro.org>
Hi Peter,
On 2/2/21 6:54 PM, Peter Maydell wrote:
> Mostly just bug fixes. The important one here is
> hw/intc/arm_gic: Fix interrupt ID in GICD_SGIR register
> which fixes a buffer overrun that's a security issue if you're running
> KVM on Arm with kernel-irqchip=off (which hopefully nobody is doing in
> a security context, because kernel-irqchip=on is the default and the
> sensible choice for performance).
FYI Prasad mentioned a CVE was requested:
https://www.mail-archive.com/qemu-devel@nongnu.org/msg778659.html
As you said it is an odd configuration, I am not sure it is worth
to wait for the CVE number to add it to the commit (which helps
downstream distributions tracking these).
[updating]
Just got detail from Prasad on IRC, it usually takes ~1 day to get
the CVE number assigned, so maybe worth postponing this until tomorrow.
Prasad, can you reply to this message ASAP once you get the number?
Thanks,
Phil.
> -- PMM
>
> The following changes since commit cf7ca7d5b9faca13f1f8e3ea92cfb2f741eb0c0e:
>
> Merge remote-tracking branch 'remotes/stefanha-gitlab/tags/tracing-pull-request' into staging (2021-02-01 16:28:00 +0000)
>
> are available in the Git repository at:
>
> https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210202-1
>
> for you to fetch changes up to 14657850c9cc10948551fbb884c30eb5a3a7370a:
>
> hw/arm: Display CPU type in machine description (2021-02-02 17:53:44 +0000)
>
> ----------------------------------------------------------------
> target-arm queue:
> * hw/intc/arm_gic: Allow to use QTest without crashing
> * hw/char/exynos4210_uart: Fix buffer size reporting with FIFO disabled
> * hw/char/exynos4210_uart: Fix missing call to report ready for input
> * hw/arm/smmuv3: Fix addr_mask for range-based invalidation
> * hw/ssi/imx_spi: Fix various minor bugs
> * hw/intc/arm_gic: Fix interrupt ID in GICD_SGIR register
> * hw/arm: Add missing Kconfig dependencies
> * hw/arm: Display CPU type in machine description
>
> ----------------------------------------------------------------
> Bin Meng (5):
> hw/ssi: imx_spi: Use a macro for number of chip selects supported
> hw/ssi: imx_spi: Remove imx_spi_update_irq() in imx_spi_reset()
> hw/ssi: imx_spi: Round up the burst length to be multiple of 8
> hw/ssi: imx_spi: Correct the burst length > 32 bit transfer logic
> hw/ssi: imx_spi: Correct tx and rx fifo endianness
>
> Iris Johnson (2):
> hw/char/exynos4210_uart: Fix buffer size reporting with FIFO disabled
> hw/char/exynos4210_uart: Fix missing call to report ready for input
>
> Philippe Mathieu-Daudé (12):
> hw/intc/arm_gic: Allow to use QTest without crashing
> hw/ssi: imx_spi: Remove pointless variable initialization
> hw/ssi: imx_spi: Rework imx_spi_reset() to keep CONREG register value
> hw/ssi: imx_spi: Rework imx_spi_read() to handle block disabled
> hw/ssi: imx_spi: Rework imx_spi_write() to handle block disabled
> hw/intc/arm_gic: Fix interrupt ID in GICD_SGIR register
> hw/arm/stm32f405_soc: Add missing dependency on OR_IRQ
> hw/arm/exynos4210: Add missing dependency on OR_IRQ
> hw/arm/xlnx-versal: Versal SoC requires ZDMA
> hw/arm/xlnx-versal: Versal SoC requires ZynqMP peripherals
> hw/net/can: ZynqMP CAN device requires PTIMER
> hw/arm: Display CPU type in machine description
>
> Xuzhou Cheng (1):
> hw/ssi: imx_spi: Disable chip selects when controller is disabled
>
> Zenghui Yu (1):
> hw/arm/smmuv3: Fix addr_mask for range-based invalidation
>
> include/hw/ssi/imx_spi.h | 5 +-
> hw/arm/digic_boards.c | 2 +-
> hw/arm/microbit.c | 2 +-
> hw/arm/netduino2.c | 2 +-
> hw/arm/netduinoplus2.c | 2 +-
> hw/arm/orangepi.c | 2 +-
> hw/arm/smmuv3.c | 4 +-
> hw/arm/stellaris.c | 4 +-
> hw/char/exynos4210_uart.c | 7 ++-
> hw/intc/arm_gic.c | 5 +-
> hw/ssi/imx_spi.c | 153 +++++++++++++++++++++++++++++-----------------
> hw/Kconfig | 1 +
> hw/arm/Kconfig | 5 ++
> hw/dma/Kconfig | 3 +
> hw/dma/meson.build | 2 +-
> 15 files changed, 130 insertions(+), 69 deletions(-)
>
next prev parent reply other threads:[~2021-02-03 9:23 UTC|newest]
Thread overview: 43+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-02-02 17:54 [PULL 00/21] target-arm queue Peter Maydell
2021-02-02 17:54 ` [PULL 01/21] hw/intc/arm_gic: Allow to use QTest without crashing Peter Maydell
2021-02-02 17:54 ` [PULL 02/21] hw/char/exynos4210_uart: Fix buffer size reporting with FIFO disabled Peter Maydell
2021-02-02 17:54 ` [PULL 03/21] hw/char/exynos4210_uart: Fix missing call to report ready for input Peter Maydell
2021-02-02 17:55 ` [PULL 04/21] hw/arm/smmuv3: Fix addr_mask for range-based invalidation Peter Maydell
2021-02-02 17:55 ` [PULL 05/21] hw/ssi: imx_spi: Use a macro for number of chip selects supported Peter Maydell
2021-02-02 17:55 ` [PULL 06/21] hw/ssi: imx_spi: Remove imx_spi_update_irq() in imx_spi_reset() Peter Maydell
2021-02-02 17:55 ` [PULL 07/21] hw/ssi: imx_spi: Remove pointless variable initialization Peter Maydell
2021-02-02 17:55 ` [PULL 08/21] hw/ssi: imx_spi: Rework imx_spi_reset() to keep CONREG register value Peter Maydell
2021-02-02 17:55 ` [PULL 09/21] hw/ssi: imx_spi: Rework imx_spi_read() to handle block disabled Peter Maydell
2021-02-02 17:55 ` [PULL 10/21] hw/ssi: imx_spi: Rework imx_spi_write() " Peter Maydell
2021-02-02 17:55 ` [PULL 11/21] hw/ssi: imx_spi: Disable chip selects when controller is disabled Peter Maydell
2021-02-02 17:55 ` [PULL 12/21] hw/ssi: imx_spi: Round up the burst length to be multiple of 8 Peter Maydell
2021-02-02 17:55 ` [PULL 13/21] hw/ssi: imx_spi: Correct the burst length > 32 bit transfer logic Peter Maydell
2021-02-02 17:55 ` [PULL 14/21] hw/ssi: imx_spi: Correct tx and rx fifo endianness Peter Maydell
2021-02-02 17:55 ` [PULL 15/21] hw/intc/arm_gic: Fix interrupt ID in GICD_SGIR register Peter Maydell
2021-02-02 17:55 ` [PULL 16/21] hw/arm/stm32f405_soc: Add missing dependency on OR_IRQ Peter Maydell
2021-02-02 17:55 ` [PULL 17/21] hw/arm/exynos4210: " Peter Maydell
2021-02-02 17:55 ` [PULL 18/21] hw/arm/xlnx-versal: Versal SoC requires ZDMA Peter Maydell
2021-02-02 17:55 ` [PULL 19/21] hw/arm/xlnx-versal: Versal SoC requires ZynqMP peripherals Peter Maydell
2021-02-02 17:55 ` [PULL 20/21] hw/net/can: ZynqMP CAN device requires PTIMER Peter Maydell
2021-02-02 17:55 ` [PULL 21/21] hw/arm: Display CPU type in machine description Peter Maydell
2021-02-03 9:22 ` Philippe Mathieu-Daudé [this message]
2021-02-03 10:12 ` [PULL 00/21] target-arm queue P J P
-- strict thread matches above, loose matches on Subject: below --
2025-03-07 15:06 Peter Maydell
2025-03-09 0:41 ` Stefan Hajnoczi
2024-07-30 9:39 Peter Maydell
2024-07-31 1:18 ` Richard Henderson
2024-04-30 16:48 Peter Maydell
2024-04-30 23:01 ` Richard Henderson
2024-01-16 15:12 Peter Maydell
2023-05-30 13:25 Peter Maydell
2023-05-30 14:13 ` Richard Henderson
2023-04-20 10:04 Peter Maydell
2023-04-21 10:49 ` Richard Henderson
2023-04-21 11:54 ` Peter Maydell
2023-03-06 15:34 Peter Maydell
2023-03-07 12:42 ` Peter Maydell
2022-03-18 13:22 Peter Maydell
2022-03-19 10:09 ` Peter Maydell
2021-08-02 11:57 Peter Maydell
2021-08-02 13:51 ` Peter Maydell
2021-01-12 16:57 Peter Maydell
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