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[174.21.143.238]) by smtp.gmail.com with ESMTPSA id m31sm2744103pjb.52.2020.06.30.08.01.00 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 30 Jun 2020 08:01:01 -0700 (PDT) Subject: Re: [PATCH 2/2] target/riscv: Do amo*.w insns operate with 32 bits To: LIU Zhiwei , qemu-devel@nongnu.org, qemu-riscv@nongnu.org References: <20200629130731.1080-1-zhiwei_liu@c-sky.com> <20200629130731.1080-3-zhiwei_liu@c-sky.com> From: Richard Henderson Message-ID: Date: Tue, 30 Jun 2020 08:00:59 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.8.0 MIME-Version: 1.0 In-Reply-To: <20200629130731.1080-3-zhiwei_liu@c-sky.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::1043; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1043.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: palmer@dabbelt.com, wenmeng_zhang@c-sky.com, Alistair.Francis@wdc.com, wxy194768@alibaba-inc.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 6/29/20 6:07 AM, LIU Zhiwei wrote: > +static bool > +gen_amo_w(DisasContext *ctx, arg_atomic *a, > + void(*func)(TCGv, TCGv, TCGv, TCGArg, MemOp), > + MemOp mop, bool sign) > { > TCGv src1 = tcg_temp_new(); > TCGv src2 = tcg_temp_new(); > > gen_get_gpr(src1, a->rs1); > gen_get_gpr(src2, a->rs2); > + if (sign) { > + tcg_gen_ext32s_tl(src2, src2); > + } else { > + tcg_gen_ext32u_tl(src2, src2); > + } > > (*func)(src2, src1, src2, ctx->mem_idx, mop); > - > + tcg_gen_ext32s_tl(src2, src2); > gen_set_gpr(a->rd, src2); > + > tcg_temp_free(src1); > tcg_temp_free(src2); > return true; With the fix to tcg, there should be no change required here, since you're already passing MO_TESL for signed input. Note that unsigned comparisions work as expected with sign-extended inputs. That's what the risc-v isa does, after all. r~