* [Qemu-devel] [PATCH] i386: Enable IA32_MISC_ENABLE MWAIT bit when exposing mwait/monitor
@ 2019-05-14 6:06 Wanpeng Li
2019-05-20 12:59 ` Paolo Bonzini
0 siblings, 1 reply; 4+ messages in thread
From: Wanpeng Li @ 2019-05-14 6:06 UTC (permalink / raw)
To: qemu-devel, kvm
Cc: Paolo Bonzini, Eduardo Habkost, Radim Krčmář
From: Wanpeng Li <wanpengli@tencent.com>
The CPUID.01H:ECX[bit 3] ought to mirror the value of the MSR
IA32_MISC_ENABLE MWAIT bit and as userspace has control of them
both, it is userspace's job to configure both bits to match on
the initial setup.
Cc: Eduardo Habkost <ehabkost@redhat.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: Radim Krčmář <rkrcmar@redhat.com>
Signed-off-by: Wanpeng Li <wanpengli@tencent.com>
---
target/i386/cpu.c | 3 +++
target/i386/cpu.h | 1 +
2 files changed, 4 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 722c551..40b6108 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -4729,6 +4729,9 @@ static void x86_cpu_reset(CPUState *s)
env->pat = 0x0007040600070406ULL;
env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
+ if (enable_cpu_pm) {
+ env->msr_ia32_misc_enable |= MSR_IA32_MISC_ENABLE_MWAIT;
+ }
memset(env->dr, 0, sizeof(env->dr));
env->dr[6] = DR6_FIXED_1;
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 0128910..b94c329 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -387,6 +387,7 @@ typedef enum X86Seg {
#define MSR_IA32_MISC_ENABLE 0x1a0
/* Indicates good rep/movs microcode on some processors: */
#define MSR_IA32_MISC_ENABLE_DEFAULT 1
+#define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << 18)
#define MSR_MTRRphysBase(reg) (0x200 + 2 * (reg))
#define MSR_MTRRphysMask(reg) (0x200 + 2 * (reg) + 1)
--
2.7.4
^ permalink raw reply related [flat|nested] 4+ messages in thread* Re: [Qemu-devel] [PATCH] i386: Enable IA32_MISC_ENABLE MWAIT bit when exposing mwait/monitor
2019-05-14 6:06 [Qemu-devel] [PATCH] i386: Enable IA32_MISC_ENABLE MWAIT bit when exposing mwait/monitor Wanpeng Li
@ 2019-05-20 12:59 ` Paolo Bonzini
2019-05-20 21:05 ` Eduardo Habkost
0 siblings, 1 reply; 4+ messages in thread
From: Paolo Bonzini @ 2019-05-20 12:59 UTC (permalink / raw)
To: Wanpeng Li, qemu-devel, kvm; +Cc: Eduardo Habkost, Radim Krčmář
On 14/05/19 08:06, Wanpeng Li wrote:
> From: Wanpeng Li <wanpengli@tencent.com>
>
> The CPUID.01H:ECX[bit 3] ought to mirror the value of the MSR
> IA32_MISC_ENABLE MWAIT bit and as userspace has control of them
> both, it is userspace's job to configure both bits to match on
> the initial setup.
Queued, thanks.
Paolo
> Cc: Eduardo Habkost <ehabkost@redhat.com>
> Cc: Paolo Bonzini <pbonzini@redhat.com>
> Cc: Radim Krčmář <rkrcmar@redhat.com>
> Signed-off-by: Wanpeng Li <wanpengli@tencent.com>
> ---
> target/i386/cpu.c | 3 +++
> target/i386/cpu.h | 1 +
> 2 files changed, 4 insertions(+)
>
> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> index 722c551..40b6108 100644
> --- a/target/i386/cpu.c
> +++ b/target/i386/cpu.c
> @@ -4729,6 +4729,9 @@ static void x86_cpu_reset(CPUState *s)
>
> env->pat = 0x0007040600070406ULL;
> env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
> + if (enable_cpu_pm) {
> + env->msr_ia32_misc_enable |= MSR_IA32_MISC_ENABLE_MWAIT;
> + }
>
> memset(env->dr, 0, sizeof(env->dr));
> env->dr[6] = DR6_FIXED_1;
> diff --git a/target/i386/cpu.h b/target/i386/cpu.h
> index 0128910..b94c329 100644
> --- a/target/i386/cpu.h
> +++ b/target/i386/cpu.h
> @@ -387,6 +387,7 @@ typedef enum X86Seg {
> #define MSR_IA32_MISC_ENABLE 0x1a0
> /* Indicates good rep/movs microcode on some processors: */
> #define MSR_IA32_MISC_ENABLE_DEFAULT 1
> +#define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << 18)
>
> #define MSR_MTRRphysBase(reg) (0x200 + 2 * (reg))
> #define MSR_MTRRphysMask(reg) (0x200 + 2 * (reg) + 1)
>
^ permalink raw reply [flat|nested] 4+ messages in thread* Re: [Qemu-devel] [PATCH] i386: Enable IA32_MISC_ENABLE MWAIT bit when exposing mwait/monitor
2019-05-20 12:59 ` Paolo Bonzini
@ 2019-05-20 21:05 ` Eduardo Habkost
2019-05-22 10:29 ` Paolo Bonzini
0 siblings, 1 reply; 4+ messages in thread
From: Eduardo Habkost @ 2019-05-20 21:05 UTC (permalink / raw)
To: Paolo Bonzini; +Cc: Wanpeng Li, qemu-devel, kvm, Radim Krčmář
On Mon, May 20, 2019 at 02:59:53PM +0200, Paolo Bonzini wrote:
> On 14/05/19 08:06, Wanpeng Li wrote:
> > From: Wanpeng Li <wanpengli@tencent.com>
> >
> > The CPUID.01H:ECX[bit 3] ought to mirror the value of the MSR
> > IA32_MISC_ENABLE MWAIT bit and as userspace has control of them
> > both, it is userspace's job to configure both bits to match on
> > the initial setup.
>
> Queued, thanks.
>
> Paolo
>
> > Cc: Eduardo Habkost <ehabkost@redhat.com>
> > Cc: Paolo Bonzini <pbonzini@redhat.com>
> > Cc: Radim Krčmář <rkrcmar@redhat.com>
> > Signed-off-by: Wanpeng Li <wanpengli@tencent.com>
> > ---
> > target/i386/cpu.c | 3 +++
> > target/i386/cpu.h | 1 +
> > 2 files changed, 4 insertions(+)
> >
> > diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> > index 722c551..40b6108 100644
> > --- a/target/i386/cpu.c
> > +++ b/target/i386/cpu.c
> > @@ -4729,6 +4729,9 @@ static void x86_cpu_reset(CPUState *s)
> >
> > env->pat = 0x0007040600070406ULL;
> > env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
> > + if (enable_cpu_pm) {
> > + env->msr_ia32_misc_enable |= MSR_IA32_MISC_ENABLE_MWAIT;
> > + }
What if enable_cpu_pm is false but we're running TCG, or if
enable_cpu_pm is true but we're not using -cpu host?
Shouldn't this be conditional on
(env->features[FEAT_1_ECX] & CPUID_EXT_MONITOR)
instead?
> >
> > memset(env->dr, 0, sizeof(env->dr));
> > env->dr[6] = DR6_FIXED_1;
> > diff --git a/target/i386/cpu.h b/target/i386/cpu.h
> > index 0128910..b94c329 100644
> > --- a/target/i386/cpu.h
> > +++ b/target/i386/cpu.h
> > @@ -387,6 +387,7 @@ typedef enum X86Seg {
> > #define MSR_IA32_MISC_ENABLE 0x1a0
> > /* Indicates good rep/movs microcode on some processors: */
> > #define MSR_IA32_MISC_ENABLE_DEFAULT 1
> > +#define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << 18)
> >
> > #define MSR_MTRRphysBase(reg) (0x200 + 2 * (reg))
> > #define MSR_MTRRphysMask(reg) (0x200 + 2 * (reg) + 1)
> >
>
--
Eduardo
^ permalink raw reply [flat|nested] 4+ messages in thread* Re: [Qemu-devel] [PATCH] i386: Enable IA32_MISC_ENABLE MWAIT bit when exposing mwait/monitor
2019-05-20 21:05 ` Eduardo Habkost
@ 2019-05-22 10:29 ` Paolo Bonzini
0 siblings, 0 replies; 4+ messages in thread
From: Paolo Bonzini @ 2019-05-22 10:29 UTC (permalink / raw)
To: Eduardo Habkost; +Cc: Wanpeng Li, qemu-devel, kvm, Radim Krčmář
On 20/05/19 23:05, Eduardo Habkost wrote:
> What if enable_cpu_pm is false but we're running TCG, or if
> enable_cpu_pm is true but we're not using -cpu host?
>
> Shouldn't this be conditional on
> (env->features[FEAT_1_ECX] & CPUID_EXT_MONITOR)
> instead?
Yes, it should. I fixed it locally.
Paolo
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2019-05-22 10:31 UTC | newest]
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2019-05-14 6:06 [Qemu-devel] [PATCH] i386: Enable IA32_MISC_ENABLE MWAIT bit when exposing mwait/monitor Wanpeng Li
2019-05-20 12:59 ` Paolo Bonzini
2019-05-20 21:05 ` Eduardo Habkost
2019-05-22 10:29 ` Paolo Bonzini
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