From: Richard Henderson <richard.henderson@linaro.org>
To: "Frédéric Pétrot" <frederic.petrot@univ-grenoble-alpes.fr>,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: philmd@redhat.com, bin.meng@windriver.com,
alistair.francis@wdc.com, palmer@dabbelt.com,
fabien.portas@grenoble-inp.org
Subject: Re: [PATCH v3 12/21] target/riscv: support for 128-bit U-type instructions
Date: Wed, 20 Oct 2021 10:59:22 -0700 [thread overview]
Message-ID: <dcc439d2-68db-200d-0fc8-44a73979c4ff@linaro.org> (raw)
In-Reply-To: <20211019094812.614056-13-frederic.petrot@univ-grenoble-alpes.fr>
On 10/19/21 2:48 AM, Frédéric Pétrot wrote:
> Adding the 128-bit version of lui and auipc.
>
> Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
> Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
> ---
> target/riscv/insn_trans/trans_rvi.c.inc | 19 +++++++++++++++++--
> 1 file changed, 17 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
> index 92f41f3a86..b5e292a2aa 100644
> --- a/target/riscv/insn_trans/trans_rvi.c.inc
> +++ b/target/riscv/insn_trans/trans_rvi.c.inc
> @@ -26,14 +26,17 @@ static bool trans_illegal(DisasContext *ctx, arg_empty *a)
>
> static bool trans_c64_illegal(DisasContext *ctx, arg_empty *a)
> {
> - REQUIRE_64BIT(ctx);
> - return trans_illegal(ctx, a);
> + REQUIRE_64_OR_128BIT(ctx);
> + return trans_illegal(ctx, a);
> }
>
> static bool trans_lui(DisasContext *ctx, arg_lui *a)
> {
> if (a->rd != 0) {
> tcg_gen_movi_tl(cpu_gpr[a->rd], a->imm);
> + if (get_xl_max(ctx) == MXL_RV128) {
> + tcg_gen_movi_tl(cpu_gprh[a->rd], -(a->imm < 0));
> + }
> }
> return true;
> }
> @@ -41,7 +44,19 @@ static bool trans_lui(DisasContext *ctx, arg_lui *a)
> static bool trans_auipc(DisasContext *ctx, arg_auipc *a)
> {
> if (a->rd != 0) {
> + if (get_xl_max(ctx) == MXL_RV128) {
> + /* TODO : when pc is 128 bits, use all its bits */
> + TCGv pc = tcg_constant_tl(ctx->base.pc_next),
> + imml = tcg_constant_tl(a->imm),
> + immh = tcg_constant_tl(-(a->imm < 0)),
> + zero = tcg_constant_tl(0);
> + tcg_gen_add2_tl(cpu_gpr[a->rd], cpu_gprh[a->rd],
> + pc, zero,
> + imml, immh);
A runtime computation of constant + constant is pointless.
I think you should refactor these into a gen_set_gpri, and hide the sign-extension into
gprh there.
r~
next prev parent reply other threads:[~2021-10-20 18:02 UTC|newest]
Thread overview: 49+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-19 9:47 [PATCH v3 00/21] Adding partial support for 128-bit riscv target Frédéric Pétrot
2021-10-19 9:47 ` [PATCH v3 01/21] memory: change define name for consistency Frédéric Pétrot
2021-10-20 15:07 ` Philippe Mathieu-Daudé
2021-10-19 9:47 ` [PATCH v3 02/21] memory: add a few defines for octo (128-bit) values Frédéric Pétrot
2021-10-19 18:00 ` Richard Henderson
2021-10-19 9:47 ` [PATCH v3 03/21] Int128.h: addition of a few 128-bit operations Frédéric Pétrot
2021-10-19 18:15 ` Richard Henderson
2021-10-19 9:47 ` [PATCH v3 04/21] target/riscv: additional macros to check instruction support Frédéric Pétrot
2021-10-20 14:08 ` Richard Henderson
2021-10-21 16:22 ` Frédéric Pétrot
2021-10-19 9:47 ` [PATCH v3 05/21] target/riscv: separation of bitwise logic and aritmetic helpers Frédéric Pétrot
2021-10-20 14:14 ` Richard Henderson
2021-10-19 9:47 ` [PATCH v3 06/21] target/riscv: array for the 64 upper bits of 128-bit registers Frédéric Pétrot
2021-10-20 14:44 ` Richard Henderson
2021-10-22 6:06 ` Frédéric Pétrot
2021-10-19 9:47 ` [PATCH v3 07/21] target/riscv: setup everything so that riscv128-softmmu compiles Frédéric Pétrot
2021-10-20 14:57 ` Richard Henderson
2021-10-19 9:47 ` [PATCH v3 08/21] target/riscv: adding accessors to the registers upper part Frédéric Pétrot
2021-10-20 15:09 ` Richard Henderson
2021-10-19 9:48 ` [PATCH v3 09/21] target/riscv: moving some insns close to similar insns Frédéric Pétrot
2021-10-20 15:11 ` Richard Henderson
2021-10-19 9:48 ` [PATCH v3 10/21] target/riscv: support for 128-bit loads and store Frédéric Pétrot
2021-10-20 17:31 ` Richard Henderson
2021-10-19 9:48 ` [PATCH v3 11/21] target/riscv: support for 128-bit bitwise instructions Frédéric Pétrot
2021-10-20 17:47 ` Richard Henderson
2021-10-20 19:18 ` Frédéric Pétrot
2021-10-19 9:48 ` [PATCH v3 12/21] target/riscv: support for 128-bit U-type instructions Frédéric Pétrot
2021-10-20 17:59 ` Richard Henderson [this message]
2021-10-19 9:48 ` [PATCH v3 13/21] target/riscv: support for 128-bit shift instructions Frédéric Pétrot
2021-10-20 19:06 ` Richard Henderson
2021-10-24 22:49 ` Frédéric Pétrot
2021-10-19 9:48 ` [PATCH v3 14/21] target/riscv: support for 128-bit arithmetic instructions Frédéric Pétrot
2021-10-20 20:15 ` Richard Henderson
2021-10-19 9:48 ` [PATCH v3 15/21] target/riscv: support for 128-bit M extension Frédéric Pétrot
2021-10-20 20:58 ` Richard Henderson
2021-10-19 9:48 ` [PATCH v3 16/21] target/riscv: adding high part of some csrs Frédéric Pétrot
2021-10-20 21:38 ` Richard Henderson
2021-10-20 23:03 ` Richard Henderson
2021-10-19 9:48 ` [PATCH v3 17/21] target/riscv: helper functions to wrap calls to 128-bit csr insns Frédéric Pétrot
2021-10-20 21:47 ` Richard Henderson
2021-10-19 9:48 ` [PATCH v3 18/21] target/riscv: modification of the trans_csrxx for 128-bit support Frédéric Pétrot
2021-10-20 21:53 ` Richard Henderson
2021-10-19 9:48 ` [PATCH v3 19/21] target/riscv: actual functions to realize crs 128-bit insns Frédéric Pétrot
2021-10-20 22:18 ` Richard Henderson
2021-10-19 9:48 ` [PATCH v3 20/21] target/riscv: adding 128-bit access functions for some csrs Frédéric Pétrot
2021-10-20 23:18 ` Richard Henderson
2021-10-19 9:48 ` [PATCH v3 21/21] target/riscv: support for 128-bit satp Frédéric Pétrot
2021-10-20 23:09 ` Richard Henderson
2021-10-21 11:12 ` Frédéric Pétrot
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