From: Richard Henderson <richard.henderson@linaro.org>
To: Ziqiao Kong <ziqiaokong@gmail.com>, qemu-devel@nongnu.org
Cc: pbonzini@redhat.com, ehabkost@redhat.com
Subject: Re: [PATCH] Set the correct env->fpip for x86 float instructions [cleaned]
Date: Tue, 27 Apr 2021 10:49:36 -0700 [thread overview]
Message-ID: <dcca83eb-40e7-91a2-c8dc-73a5a51d23db@linaro.org> (raw)
In-Reply-To: <20210416153430.92187-1-ziqiaokong@gmail.com>
On 4/16/21 8:34 AM, Ziqiao Kong wrote:
> +++ b/target/i386/tcg/translate.c
> @@ -6337,7 +6337,10 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
> goto unknown_op;
> }
> }
> + tcg_gen_movi_tl(s->tmp0, pc_start - s->cs_base);
> + tcg_gen_st_tl(s->tmp0, cpu_env, offsetof(CPUX86State, fpip));
This placement is wrong because it catches instructions that should not modify
FIP, like FINIT.
It might be best to set a flag around this case like
bool update_fip;
case 0xd8 .. 0xdf:
...
update_fip = true;
if (mod != 3) {
...
} else {
...
}
if (update_fip) {
...
}
break;
and set update_fip to false for the set of insns that either do not update FIP
or clear it (8.1.8 x87 fpu instruction and data (operand) pointers).
I notice you're not saving FCS to go along with this, at least for
CPUID.(EAX=07H,ECX=0H):EBX[bit 13] = 0.
And if you're going to this trouble, you might want to think about FDP+FDS as
well. It should be about the same amount of effort.
r~
next prev parent reply other threads:[~2021-04-27 17:54 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-16 15:34 [PATCH] Set the correct env->fpip for x86 float instructions [cleaned] Ziqiao Kong
2021-04-22 10:46 ` Ziqiao Kong
2021-04-27 17:49 ` Richard Henderson [this message]
2021-04-28 3:25 ` Ziqiao Kong
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