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Tue, 27 Apr 2021 10:49:38 -0700 (PDT) Received: from [192.168.1.11] ([71.212.144.24]) by smtp.gmail.com with ESMTPSA id t19sm333370pgv.75.2021.04.27.10.49.38 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 27 Apr 2021 10:49:38 -0700 (PDT) Subject: Re: [PATCH] Set the correct env->fpip for x86 float instructions [cleaned] To: Ziqiao Kong , qemu-devel@nongnu.org References: <20210416153430.92187-1-ziqiaokong@gmail.com> From: Richard Henderson Message-ID: Date: Tue, 27 Apr 2021 10:49:36 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.7.1 MIME-Version: 1.0 In-Reply-To: <20210416153430.92187-1-ziqiaokong@gmail.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::52d; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pbonzini@redhat.com, ehabkost@redhat.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 4/16/21 8:34 AM, Ziqiao Kong wrote: > +++ b/target/i386/tcg/translate.c > @@ -6337,7 +6337,10 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) > goto unknown_op; > } > } > + tcg_gen_movi_tl(s->tmp0, pc_start - s->cs_base); > + tcg_gen_st_tl(s->tmp0, cpu_env, offsetof(CPUX86State, fpip)); This placement is wrong because it catches instructions that should not modify FIP, like FINIT. It might be best to set a flag around this case like bool update_fip; case 0xd8 .. 0xdf: ... update_fip = true; if (mod != 3) { ... } else { ... } if (update_fip) { ... } break; and set update_fip to false for the set of insns that either do not update FIP or clear it (8.1.8 x87 fpu instruction and data (operand) pointers). I notice you're not saving FCS to go along with this, at least for CPUID.(EAX=07H,ECX=0H):EBX[bit 13] = 0. And if you're going to this trouble, you might want to think about FDP+FDS as well. It should be about the same amount of effort. r~