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Thu, 26 Oct 2023 21:44:11 -0700 (PDT) Received: from [172.19.1.246] ([192.80.84.35]) by smtp.googlemail.com with ESMTPSA id h25-20020a0cab19000000b0065b31dfdf70sm336558qvb.11.2023.10.26.21.44.10 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 26 Oct 2023 21:44:11 -0700 (PDT) Message-ID: Date: Fri, 27 Oct 2023 06:44:10 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 08/29] tcg/aarch64: Generate TBZ, TBNZ Content-Language: en-US To: Richard Henderson , qemu-devel@nongnu.org References: <20231026001542.1141412-1-richard.henderson@linaro.org> <20231026001542.1141412-17-richard.henderson@linaro.org> From: Paolo Bonzini In-Reply-To: <20231026001542.1141412-17-richard.henderson@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 10/26/23 02:13, Richard Henderson wrote: > + case TCG_COND_TSTEQ: > + case TCG_COND_TSTNE: > + if (b_const && is_power_of_2(b)) { > + tbit = ctz64(b); > + need_cmp = false; > + } I think another value that can be handled efficiently is 0xffffffff which becomes a "cbz/cbnz wNN, LABEL" instruction. This could be interesting if the i386 frontend implemented JE/JNE and JS/JNS (of sizes smaller than MO_TL) using masks like 0xffffffff and 0x80000000 respectively. Like (for SF): MemOp size = (s->cc_op - CC_OP_ADDB) & 3; if (size == MO_TL) { return (CCPrepare) { .cond = TCG_COND_EQ, .reg = cpu_cc_dst, .mask = -1 }; } else { return (CCPrepare) { .cond = TCG_COND_TSTEQ, .reg = cpu_cc_dst, .imm = (1ull << (8 << size)) - 1, .mask = -1 }; } Then on aarch64, JE could become CBZ and JS could become TBNZ. Unfortunately, the code produced on x86 is not awful but also not too good; we discussed earlier how TST against 0xffffffff and 0x80000000 can be computed efficiently using "testl reg, reg", but you don't get to that point in tcg_out_testi because the other conditions require an S32 constraint. Those constants don't satisfy it. :( So you lose the sign extension instructions, but you get a somewhat bulky MOV to load the constant followed by "testl reg, reg_containing_imm". I guess in principle you could add TCG_TARGET_{br,mov,set}condi_valid(cond, const) but it's pretty ugly. Paolo