* [PATCH 1/1] target/loongarch: Fix some exception need't update CSR_BADV
@ 2025-11-17 7:50 Song Gao
2025-11-17 8:48 ` Bibo Mao
2025-11-17 10:29 ` Bibo Mao
0 siblings, 2 replies; 5+ messages in thread
From: Song Gao @ 2025-11-17 7:50 UTC (permalink / raw)
To: maobibo; +Cc: qemu-devel, philmd, jiaxun.yang
According to Volume 1 Manual 7.4.8, certain exceptions require setting CSR_BADV,
but the code does not match.this patch correct it. and the exception PIL,PIS,PIF,
PME,PNR, PNX, PPI already update on raise_mmu_exception(),these are need't update.
Signed-off-by: Song Gao <gaosong@loongson.cn>
---
target/loongarch/tcg/tcg_cpu.c | 24 +++++++++++++-----------
1 file changed, 13 insertions(+), 11 deletions(-)
diff --git a/target/loongarch/tcg/tcg_cpu.c b/target/loongarch/tcg/tcg_cpu.c
index 9d077c56d9..7f94c183c4 100644
--- a/target/loongarch/tcg/tcg_cpu.c
+++ b/target/loongarch/tcg/tcg_cpu.c
@@ -109,10 +109,22 @@ static void loongarch_cpu_do_interrupt(CPUState *cs)
}
QEMU_FALLTHROUGH;
case EXCCODE_PIF:
- case EXCCODE_ADEF:
cause = cs->exception_index;
update_badinstr = 0;
break;
+ case EXCCODE_ADEF:
+ update_badinstr = 0;
+ QEMU_FALLTHROUGH;
+ case EXCCODE_BCE:
+ case EXCCODE_ADEM:
+ env->CSR_BADV = env->pc;
+ QEMU_FALLTHROUGH;
+ case EXCCODE_PNR:
+ case EXCCODE_PNX:
+ case EXCCODE_PPI:
+ case EXCCODE_PIL:
+ case EXCCODE_PIS:
+ case EXCCODE_PME:
case EXCCODE_SYS:
case EXCCODE_BRK:
case EXCCODE_INE:
@@ -121,16 +133,6 @@ static void loongarch_cpu_do_interrupt(CPUState *cs)
case EXCCODE_FPE:
case EXCCODE_SXD:
case EXCCODE_ASXD:
- env->CSR_BADV = env->pc;
- QEMU_FALLTHROUGH;
- case EXCCODE_BCE:
- case EXCCODE_ADEM:
- case EXCCODE_PIL:
- case EXCCODE_PIS:
- case EXCCODE_PME:
- case EXCCODE_PNR:
- case EXCCODE_PNX:
- case EXCCODE_PPI:
cause = cs->exception_index;
break;
default:
--
2.51.0
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH 1/1] target/loongarch: Fix some exception need't update CSR_BADV
2025-11-17 7:50 [PATCH 1/1] target/loongarch: Fix some exception need't update CSR_BADV Song Gao
@ 2025-11-17 8:48 ` Bibo Mao
2025-11-17 9:58 ` gaosong
2025-11-17 10:29 ` Bibo Mao
1 sibling, 1 reply; 5+ messages in thread
From: Bibo Mao @ 2025-11-17 8:48 UTC (permalink / raw)
To: Song Gao; +Cc: qemu-devel, philmd, jiaxun.yang
On 2025/11/17 下午3:50, Song Gao wrote:
> According to Volume 1 Manual 7.4.8, certain exceptions require setting CSR_BADV,
> but the code does not match.this patch correct it. and the exception PIL,PIS,PIF,
> PME,PNR, PNX, PPI already update on raise_mmu_exception(),these are need't update.
>
> Signed-off-by: Song Gao <gaosong@loongson.cn>
> ---
> target/loongarch/tcg/tcg_cpu.c | 24 +++++++++++++-----------
> 1 file changed, 13 insertions(+), 11 deletions(-)
>
> diff --git a/target/loongarch/tcg/tcg_cpu.c b/target/loongarch/tcg/tcg_cpu.c
> index 9d077c56d9..7f94c183c4 100644
> --- a/target/loongarch/tcg/tcg_cpu.c
> +++ b/target/loongarch/tcg/tcg_cpu.c
> @@ -109,10 +109,22 @@ static void loongarch_cpu_do_interrupt(CPUState *cs)
> }
> QEMU_FALLTHROUGH;
> case EXCCODE_PIF:
> - case EXCCODE_ADEF:
> cause = cs->exception_index;
> update_badinstr = 0;
> break;
> + case EXCCODE_ADEF:
> + update_badinstr = 0;
> + QEMU_FALLTHROUGH;
why is there such modification with EXCCODE_ADEF? what is the problem
with exception EXCCODE_ADEF?
> + case EXCCODE_BCE:
> + case EXCCODE_ADEM:
> + env->CSR_BADV = env->pc;
> + QEMU_FALLTHROUGH;
With EXCCODE_BCE/EXCCODE_ADEM, if CSR_BADV is missing, please use
another patch.
> + case EXCCODE_PNR:
> + case EXCCODE_PNX:
> + case EXCCODE_PPI:
> + case EXCCODE_PIL:
> + case EXCCODE_PIS:
> + case EXCCODE_PME:
What is the problem with EXCCODE_PNR/EXCCODE_PNX exception here?
Regards
Bibo Mao
> case EXCCODE_SYS:
> case EXCCODE_BRK:
> case EXCCODE_INE:
> @@ -121,16 +133,6 @@ static void loongarch_cpu_do_interrupt(CPUState *cs)
> case EXCCODE_FPE:
> case EXCCODE_SXD:
> case EXCCODE_ASXD:
> - env->CSR_BADV = env->pc;
> - QEMU_FALLTHROUGH;
> - case EXCCODE_BCE:
> - case EXCCODE_ADEM:
> - case EXCCODE_PIL:
> - case EXCCODE_PIS:
> - case EXCCODE_PME:
> - case EXCCODE_PNR:
> - case EXCCODE_PNX:
> - case EXCCODE_PPI:
> cause = cs->exception_index;
> break;
> default:
>
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 1/1] target/loongarch: Fix some exception need't update CSR_BADV
2025-11-17 8:48 ` Bibo Mao
@ 2025-11-17 9:58 ` gaosong
2025-11-17 10:16 ` Bibo Mao
0 siblings, 1 reply; 5+ messages in thread
From: gaosong @ 2025-11-17 9:58 UTC (permalink / raw)
To: Bibo Mao; +Cc: qemu-devel, philmd, jiaxun.yang
在 2025/11/17 下午4:48, Bibo Mao 写道:
>
>
> On 2025/11/17 下午3:50, Song Gao wrote:
>> According to Volume 1 Manual 7.4.8, certain exceptions require
>> setting CSR_BADV,
>> but the code does not match.this patch correct it. and the exception
>> PIL,PIS,PIF,
>> PME,PNR, PNX, PPI already update on raise_mmu_exception(),these are
>> need't update.
>>
>> Signed-off-by: Song Gao <gaosong@loongson.cn>
>> ---
>> target/loongarch/tcg/tcg_cpu.c | 24 +++++++++++++-----------
>> 1 file changed, 13 insertions(+), 11 deletions(-)
>>
>> diff --git a/target/loongarch/tcg/tcg_cpu.c
>> b/target/loongarch/tcg/tcg_cpu.c
>> index 9d077c56d9..7f94c183c4 100644
>> --- a/target/loongarch/tcg/tcg_cpu.c
>> +++ b/target/loongarch/tcg/tcg_cpu.c
>> @@ -109,10 +109,22 @@ static void loongarch_cpu_do_interrupt(CPUState
>> *cs)
>> }
>> QEMU_FALLTHROUGH;
>> case EXCCODE_PIF:
>> - case EXCCODE_ADEF:
>> cause = cs->exception_index;
>> update_badinstr = 0;
>> break;
>> + case EXCCODE_ADEF:
>> + update_badinstr = 0;
>> + QEMU_FALLTHROUGH;
> why is there such modification with EXCCODE_ADEF? what is the problem
> with exception EXCCODE_ADEF?
>
EXCCODE_ADEF also missing update CSR_BADV.
>> + case EXCCODE_BCE:
>> + case EXCCODE_ADEM:
>> + env->CSR_BADV = env->pc;
>> + QEMU_FALLTHROUGH;
> With EXCCODE_BCE/EXCCODE_ADEM, if CSR_BADV is missing, please use
> another patch.
>> + case EXCCODE_PNR:
>> + case EXCCODE_PNX:
>> + case EXCCODE_PPI:
>> + case EXCCODE_PIL:
>> + case EXCCODE_PIS:
>> + case EXCCODE_PME:
> What is the problem with EXCCODE_PNR/EXCCODE_PNX exception here?
>
These exceptions already update CSR_BADV on raise_mmu_exception(),
and the PGD value frome CSR_BADV, see 7.5.7.
"When CSR.TLBRERA.IsTLBR=0, the bad virtual address
information in the current context is located in CSR.BADV;"
we shoudn't updat CSR_BADV here.
Thanks.
Song Gao.
> Regards
> Bibo Mao
>> case EXCCODE_SYS:
>> case EXCCODE_BRK:
>> case EXCCODE_INE:
>> @@ -121,16 +133,6 @@ static void loongarch_cpu_do_interrupt(CPUState
>> *cs)
>> case EXCCODE_FPE:
>> case EXCCODE_SXD:
>> case EXCCODE_ASXD:
>> - env->CSR_BADV = env->pc;
>> - QEMU_FALLTHROUGH;
>> - case EXCCODE_BCE:
>> - case EXCCODE_ADEM:
>> - case EXCCODE_PIL:
>> - case EXCCODE_PIS:
>> - case EXCCODE_PME:
>> - case EXCCODE_PNR:
>> - case EXCCODE_PNX:
>> - case EXCCODE_PPI:
>> cause = cs->exception_index;
>> break;
>> default:
>>
>
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 1/1] target/loongarch: Fix some exception need't update CSR_BADV
2025-11-17 9:58 ` gaosong
@ 2025-11-17 10:16 ` Bibo Mao
0 siblings, 0 replies; 5+ messages in thread
From: Bibo Mao @ 2025-11-17 10:16 UTC (permalink / raw)
To: gaosong; +Cc: qemu-devel, philmd, jiaxun.yang
On 2025/11/17 下午5:58, gaosong wrote:
> 在 2025/11/17 下午4:48, Bibo Mao 写道:
>>
>>
>> On 2025/11/17 下午3:50, Song Gao wrote:
>>> According to Volume 1 Manual 7.4.8, certain exceptions require
>>> setting CSR_BADV,
>>> but the code does not match.this patch correct it. and the exception
>>> PIL,PIS,PIF,
>>> PME,PNR, PNX, PPI already update on raise_mmu_exception(),these are
>>> need't update.
>>>
>>> Signed-off-by: Song Gao <gaosong@loongson.cn>
>>> ---
>>> target/loongarch/tcg/tcg_cpu.c | 24 +++++++++++++-----------
>>> 1 file changed, 13 insertions(+), 11 deletions(-)
>>>
>>> diff --git a/target/loongarch/tcg/tcg_cpu.c
>>> b/target/loongarch/tcg/tcg_cpu.c
>>> index 9d077c56d9..7f94c183c4 100644
>>> --- a/target/loongarch/tcg/tcg_cpu.c
>>> +++ b/target/loongarch/tcg/tcg_cpu.c
>>> @@ -109,10 +109,22 @@ static void loongarch_cpu_do_interrupt(CPUState
>>> *cs)
>>> }
>>> QEMU_FALLTHROUGH;
>>> case EXCCODE_PIF:
>>> - case EXCCODE_ADEF:
>>> cause = cs->exception_index;
>>> update_badinstr = 0;
>>> break;
>>> + case EXCCODE_ADEF:
>>> + update_badinstr = 0;
>>> + QEMU_FALLTHROUGH;
>> why is there such modification with EXCCODE_ADEF? what is the problem
>> with exception EXCCODE_ADEF?
>>
> EXCCODE_ADEF also missing update CSR_BADV.
ok, please use another patch if CSR_BADV need be updated with
EXCCODE_ADEF exception.
>>> + case EXCCODE_BCE:
>>> + case EXCCODE_ADEM:
>>> + env->CSR_BADV = env->pc;
>>> + QEMU_FALLTHROUGH;
>> With EXCCODE_BCE/EXCCODE_ADEM, if CSR_BADV is missing, please use
>> another patch.
>>> + case EXCCODE_PNR:
>>> + case EXCCODE_PNX:
>>> + case EXCCODE_PPI:
>>> + case EXCCODE_PIL:
>>> + case EXCCODE_PIS:
>>> + case EXCCODE_PME:
>> What is the problem with EXCCODE_PNR/EXCCODE_PNX exception here?
>>
> These exceptions already update CSR_BADV on raise_mmu_exception(),
>
> and the PGD value frome CSR_BADV, see 7.5.7.
> "When CSR.TLBRERA.IsTLBR=0, the bad virtual address
> information in the current context is located in CSR.BADV;"
>
> we shoudn't updat CSR_BADV here.
In the original code, CSR_BADV is not updated with
EXCCODE_PNR/EXCCODE_PNX exception.
Regards
Bibo Mao
>
> Thanks.
> Song Gao.
>> Regards
>> Bibo Mao
>>> case EXCCODE_SYS:
>>> case EXCCODE_BRK:
>>> case EXCCODE_INE:
>>> @@ -121,16 +133,6 @@ static void loongarch_cpu_do_interrupt(CPUState
>>> *cs)
>>> case EXCCODE_FPE:
>>> case EXCCODE_SXD:
>>> case EXCCODE_ASXD:
>>> - env->CSR_BADV = env->pc;
>>> - QEMU_FALLTHROUGH;
>>> - case EXCCODE_BCE:
>>> - case EXCCODE_ADEM:
>>> - case EXCCODE_PIL:
>>> - case EXCCODE_PIS:
>>> - case EXCCODE_PME:
>>> - case EXCCODE_PNR:
>>> - case EXCCODE_PNX:
>>> - case EXCCODE_PPI:
>>> cause = cs->exception_index;
>>> break;
>>> default:
>>>
>>
>
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 1/1] target/loongarch: Fix some exception need't update CSR_BADV
2025-11-17 7:50 [PATCH 1/1] target/loongarch: Fix some exception need't update CSR_BADV Song Gao
2025-11-17 8:48 ` Bibo Mao
@ 2025-11-17 10:29 ` Bibo Mao
1 sibling, 0 replies; 5+ messages in thread
From: Bibo Mao @ 2025-11-17 10:29 UTC (permalink / raw)
To: Song Gao; +Cc: qemu-devel, philmd, jiaxun.yang
On 2025/11/17 下午3:50, Song Gao wrote:
> According to Volume 1 Manual 7.4.8, certain exceptions require setting CSR_BADV,
> but the code does not match.this patch correct it. and the exception PIL,PIS,PIF,
> PME,PNR, PNX, PPI already update on raise_mmu_exception(),these are need't update.
>
> Signed-off-by: Song Gao <gaosong@loongson.cn>
> ---
> target/loongarch/tcg/tcg_cpu.c | 24 +++++++++++++-----------
> 1 file changed, 13 insertions(+), 11 deletions(-)
>
> diff --git a/target/loongarch/tcg/tcg_cpu.c b/target/loongarch/tcg/tcg_cpu.c
> index 9d077c56d9..7f94c183c4 100644
> --- a/target/loongarch/tcg/tcg_cpu.c
> +++ b/target/loongarch/tcg/tcg_cpu.c
> @@ -109,10 +109,22 @@ static void loongarch_cpu_do_interrupt(CPUState *cs)
> }
> QEMU_FALLTHROUGH;
> case EXCCODE_PIF:
> - case EXCCODE_ADEF:
> cause = cs->exception_index;
> update_badinstr = 0;
> break;
> + case EXCCODE_ADEF:
> + update_badinstr = 0;
> + QEMU_FALLTHROUGH;
> + case EXCCODE_BCE:
> + case EXCCODE_ADEM:
> + env->CSR_BADV = env->pc;
> + QEMU_FALLTHROUGH;
With EXCCODE_BCE exception, CSR_BADV comes from its pc. However with
EXCCODE_ADEM exception, CSR_BADV should not come from its pc value.
Regards
Bibo Mao
> + case EXCCODE_PNR:
> + case EXCCODE_PNX:
> + case EXCCODE_PPI:
> + case EXCCODE_PIL:
> + case EXCCODE_PIS:
> + case EXCCODE_PME:
> case EXCCODE_SYS:
> case EXCCODE_BRK:
> case EXCCODE_INE:
> @@ -121,16 +133,6 @@ static void loongarch_cpu_do_interrupt(CPUState *cs)
> case EXCCODE_FPE:
> case EXCCODE_SXD:
> case EXCCODE_ASXD:
> - env->CSR_BADV = env->pc;
> - QEMU_FALLTHROUGH;
> - case EXCCODE_BCE:
> - case EXCCODE_ADEM:
> - case EXCCODE_PIL:
> - case EXCCODE_PIS:
> - case EXCCODE_PME:
> - case EXCCODE_PNR:
> - case EXCCODE_PNX:
> - case EXCCODE_PPI:
> cause = cs->exception_index;
> break;
> default:
>
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2025-11-17 10:32 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
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2025-11-17 7:50 [PATCH 1/1] target/loongarch: Fix some exception need't update CSR_BADV Song Gao
2025-11-17 8:48 ` Bibo Mao
2025-11-17 9:58 ` gaosong
2025-11-17 10:16 ` Bibo Mao
2025-11-17 10:29 ` Bibo Mao
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