From: Richard Henderson <richard.henderson@linaro.org>
To: Weiwei Li <liweiwei@iscas.ac.cn>,
qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Cc: palmer@dabbelt.com, alistair.francis@wdc.com,
bin.meng@windriver.com, dbarboza@ventanamicro.com,
zhiwei_liu@linux.alibaba.com, wangjunqiang@iscas.ac.cn,
lazyparser@gmail.com
Subject: Re: [PATCH v2 6/8] accel/tcg: Uncache the host address for instruction fetch when tlb size < 1
Date: Wed, 19 Apr 2023 07:41:57 +0200 [thread overview]
Message-ID: <dd0a4aa6-e9cb-77ad-7a94-2cacf2e740b1@linaro.org> (raw)
In-Reply-To: <20230418140632.53166-7-liweiwei@iscas.ac.cn>
On 4/18/23 16:06, Weiwei Li wrote:
> When PMP entry overlap part of the page, we'll set the tlb_size to 1, which
> will make the address in tlb entry set with TLB_INVALID_MASK, and the next
> access will again go through tlb_fill.However, this way will not work in
> tb_gen_code() => get_page_addr_code_hostp(): the TLB host address will be
> cached, and the following instructions can use this host address directly
> which may lead to the bypass of PMP related check.
>
> Signed-off-by: Weiwei Li<liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang<wangjunqiang@iscas.ac.cn>
> ---
> accel/tcg/cputlb.c | 5 +++++
> 1 file changed, 5 insertions(+)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
next prev parent reply other threads:[~2023-04-19 5:42 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-18 14:06 [PATCH v2 0/8] target/riscv: Fix PMP related problem Weiwei Li
2023-04-18 14:06 ` [PATCH v2 1/8] target/riscv: Update pmp_get_tlb_size() Weiwei Li
2023-04-18 14:06 ` [PATCH v2 2/8] target/riscv: Move pmp_get_tlb_size apart from get_physical_address_pmp Weiwei Li
2023-04-18 14:06 ` [PATCH v2 3/8] target/riscv: flush tlb when pmpaddr is updated Weiwei Li
2023-04-18 14:06 ` [PATCH v2 4/8] target/riscv: Flush TLB only when pmpcfg/pmpaddr really changes Weiwei Li
2023-04-18 14:06 ` [PATCH v2 5/8] target/riscv: flush tb when PMP entry changes Weiwei Li
2023-04-18 14:06 ` [PATCH v2 6/8] accel/tcg: Uncache the host address for instruction fetch when tlb size < 1 Weiwei Li
2023-04-19 1:36 ` LIU Zhiwei
2023-04-19 5:41 ` Richard Henderson [this message]
2023-04-18 14:06 ` [PATCH v2 7/8] target/riscv: Make the short cut really work in pmp_hart_has_privs Weiwei Li
2023-04-18 14:06 ` [PATCH v2 8/8] target/riscv: Separate pmp_update_rule() in pmpcfg_csr_write Use pmp_update_rule_addr() and pmp_update_rule_nums() separately to update rule nums only once for each pmpcfg_csr_write. Then we can also move tlb_flush and tb_flush into pmp_update_rule_nums() Weiwei Li
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