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Tue, 16 Jun 2020 14:05:02 GMT Received: from b01ledav002.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 2BC50124052; Tue, 16 Jun 2020 14:05:02 +0000 (GMT) Received: from b01ledav002.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id ED1F8124055; Tue, 16 Jun 2020 14:05:01 +0000 (GMT) Received: from sbct-3.pok.ibm.com (unknown [9.47.158.153]) by b01ledav002.gho.pok.ibm.com (Postfix) with ESMTP; Tue, 16 Jun 2020 14:05:01 +0000 (GMT) Subject: Re: [PATCH v2 4/5] acpi: Enable TPM IRQ To: Auger Eric , Stefan Berger References: <20200615142327.671546-1-stefanb@linux.vnet.ibm.com> <20200615142327.671546-5-stefanb@linux.vnet.ibm.com> <8e11e2d6-5e02-89c0-759f-d74189421eec@linux.ibm.com> From: Stefan Berger Message-ID: Date: Tue, 16 Jun 2020 10:05:01 -0400 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.4.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Content-Language: en-US X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.216, 18.0.687 definitions=2020-06-16_04:2020-06-16, 2020-06-16 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 spamscore=0 mlxlogscore=999 adultscore=0 phishscore=0 bulkscore=0 suspectscore=0 clxscore=1015 priorityscore=1501 lowpriorityscore=0 malwarescore=0 impostorscore=0 cotscore=-2147483648 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2004280000 definitions=main-2006160103 Received-SPF: pass client-ip=148.163.156.1; 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Tsirkin" , qemu-devel , "Bonzini, Paolo" , =?UTF-8?Q?Marc-Andr=c3=a9_Lureau?= , Philippe Mathieu Daude , Marek Kedzierski Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 6/16/20 9:01 AM, Auger Eric wrote: > Hi Stefan, > > On 6/15/20 7:11 PM, Stefan Berger wrote: >> On 6/15/20 11:13 AM, Marc-André Lureau wrote: >>>> diff --git a/include/hw/acpi/tpm.h b/include/hw/acpi/tpm.h >>>> index 1a2a57a21f..063a9eb42a 100644 >>>> --- a/include/hw/acpi/tpm.h >>>> +++ b/include/hw/acpi/tpm.h >>>> @@ -24,7 +24,7 @@ >>>>   #define TPM_TIS_ADDR_BASE           0xFED40000 >>>>   #define TPM_TIS_ADDR_SIZE           0x5000 >>>> >>>> -#define TPM_TIS_IRQ                 5 >>>> +#define TPM_TIS_IRQ                 13 >> >> Eric, >> >>  does this change have any negative side effects on ARM? If you prefer, >> we can split this part here up into TPM_TIS_ISA_IRQ and TPM_TIS_SYSBUS >> IRQ and leave the latter at '5' because we know that this is working. > The IRQ is not advertised in dt nor ACPI on ARM. However it is > advertised in the capability reg and in the vector. reg So I think this > should be fixed? I guess on ARM we will pick up a completely different > IRQ num, allocated from the platform bus slot. The specification https://trustedcomputinggroup.org/wp-content/uploads/PC-Client-Specific-Platform-TPM-Profile-for-TPM-2p0-v1p04_r0p37_pub-1.pdf declares several fields in the Interface Capability Register (table 23, pdf page 89) to be mandatory and they must be set to '1'. So I would not want to touch those. We can set the interrupt vector register to '0' in case interrupts are not supported. Following the spec 0 means that no interrupts are supported. I will now split TPM_TIS_IRQ into TPM_TIS_ISA_IRQ and TPM_TIS_SYSBUS_IRQ and will in the end set TPM_TIS_SYSBUS_IRQ to 'disabled', indicating that IRQs are not supported, though they should work even though on ARM there may not be a driver to test this with. Does this sound ok?    Stefan > > Thanks > > Eric >>    Stefan >> >> >>>>   #define TPM_TIS_NUM_LOCALITIES      5     /* per spec */ >>>>   #define TPM_TIS_LOCALITY_SHIFT      12 >>>> -- >>>> 2.24.1 >>>>