* [PATCH 00/11] Various updates for the Cadence GEM model
@ 2023-10-17 19:44 Luc Michel
2023-10-17 19:44 ` [PATCH 01/11] hw/net/cadence_gem: use REG32 macro for register definitions Luc Michel
` (11 more replies)
0 siblings, 12 replies; 25+ messages in thread
From: Luc Michel @ 2023-10-17 19:44 UTC (permalink / raw)
To: qemu-devel
Cc: Luc Michel, qemu-arm, Edgar E . Iglesias, Alistair Francis,
Peter Maydell, Jason Wang, Philippe Mathieu-Daudé,
Francisco Iglesias, Frederic Konrad, Sai Pavan Boddu
Hi,
This series brings small changes to the Cadence GEM Ethernet model.
There is (almost) no behaviour change.
Patches 1 to 9 replace handcrafted defines with the use of REG32 and
FIELDS macros for register and fields declarations.
Patch 10 fixes PHY accesses so that they are done only on a write to the
PHYMNTNC register (as the real hardware does).
Patch 11 fixes a potential bug on hosts where unsigned would not be 32
bits.
Thanks,
--
Luc
Luc Michel (11):
hw/net/cadence_gem: use REG32 macro for register definitions
hw/net/cadence_gem: use FIELD for screening registers
hw/net/cadence_gem: use FIELD to describe NWCTRL register fields
hw/net/cadence_gem: use FIELD to describe NWCFG register fields
hw/net/cadence_gem: use FIELD to describe DMACFG register fields
hw/net/cadence_gem: use FIELD to describe [TX|RX]STATUS register
fields
hw/net/cadence_gem: use FIELD to describe IRQ register fields
hw/net/cadence_gem: use FIELD to describe DESCONF6 register fields
hw/net/cadence_gem: use FIELD to describe PHYMNTNC register fields
hw/net/cadence_gem: perform PHY access on write only
hw/net/cadence_gem: enforce 32 bits variable size for CRC
hw/net/cadence_gem.c | 910 ++++++++++++++++++++++++-------------------
1 file changed, 510 insertions(+), 400 deletions(-)
--
2.39.2
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH 01/11] hw/net/cadence_gem: use REG32 macro for register definitions
2023-10-17 19:44 [PATCH 00/11] Various updates for the Cadence GEM model Luc Michel
@ 2023-10-17 19:44 ` Luc Michel
2023-10-18 6:22 ` Boddu, Sai Pavan
2023-10-17 19:44 ` [PATCH 02/11] hw/net/cadence_gem: use FIELD for screening registers Luc Michel
` (10 subsequent siblings)
11 siblings, 1 reply; 25+ messages in thread
From: Luc Michel @ 2023-10-17 19:44 UTC (permalink / raw)
To: qemu-devel
Cc: Luc Michel, qemu-arm, Edgar E . Iglesias, Alistair Francis,
Peter Maydell, Jason Wang, Philippe Mathieu-Daudé,
Francisco Iglesias, Frederic Konrad, Sai Pavan Boddu
Replace register defines with the REG32 macro from registerfields.h in
the Cadence GEM device.
Signed-off-by: Luc Michel <luc.michel@amd.com>
---
hw/net/cadence_gem.c | 527 +++++++++++++++++++++----------------------
1 file changed, 261 insertions(+), 266 deletions(-)
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index f445d8bb5e..0e5744ecd7 100644
--- a/hw/net/cadence_gem.c
+++ b/hw/net/cadence_gem.c
@@ -26,10 +26,11 @@
#include <zlib.h> /* For crc32 */
#include "hw/irq.h"
#include "hw/net/cadence_gem.h"
#include "hw/qdev-properties.h"
+#include "hw/registerfields.h"
#include "migration/vmstate.h"
#include "qapi/error.h"
#include "qemu/log.h"
#include "qemu/module.h"
#include "sysemu/dma.h"
@@ -42,151 +43,146 @@
qemu_log(": %s: ", __func__); \
qemu_log(__VA_ARGS__); \
} \
} while (0)
-#define GEM_NWCTRL (0x00000000 / 4) /* Network Control reg */
-#define GEM_NWCFG (0x00000004 / 4) /* Network Config reg */
-#define GEM_NWSTATUS (0x00000008 / 4) /* Network Status reg */
-#define GEM_USERIO (0x0000000C / 4) /* User IO reg */
-#define GEM_DMACFG (0x00000010 / 4) /* DMA Control reg */
-#define GEM_TXSTATUS (0x00000014 / 4) /* TX Status reg */
-#define GEM_RXQBASE (0x00000018 / 4) /* RX Q Base address reg */
-#define GEM_TXQBASE (0x0000001C / 4) /* TX Q Base address reg */
-#define GEM_RXSTATUS (0x00000020 / 4) /* RX Status reg */
-#define GEM_ISR (0x00000024 / 4) /* Interrupt Status reg */
-#define GEM_IER (0x00000028 / 4) /* Interrupt Enable reg */
-#define GEM_IDR (0x0000002C / 4) /* Interrupt Disable reg */
-#define GEM_IMR (0x00000030 / 4) /* Interrupt Mask reg */
-#define GEM_PHYMNTNC (0x00000034 / 4) /* Phy Maintenance reg */
-#define GEM_RXPAUSE (0x00000038 / 4) /* RX Pause Time reg */
-#define GEM_TXPAUSE (0x0000003C / 4) /* TX Pause Time reg */
-#define GEM_TXPARTIALSF (0x00000040 / 4) /* TX Partial Store and Forward */
-#define GEM_RXPARTIALSF (0x00000044 / 4) /* RX Partial Store and Forward */
-#define GEM_JUMBO_MAX_LEN (0x00000048 / 4) /* Max Jumbo Frame Size */
-#define GEM_HASHLO (0x00000080 / 4) /* Hash Low address reg */
-#define GEM_HASHHI (0x00000084 / 4) /* Hash High address reg */
-#define GEM_SPADDR1LO (0x00000088 / 4) /* Specific addr 1 low reg */
-#define GEM_SPADDR1HI (0x0000008C / 4) /* Specific addr 1 high reg */
-#define GEM_SPADDR2LO (0x00000090 / 4) /* Specific addr 2 low reg */
-#define GEM_SPADDR2HI (0x00000094 / 4) /* Specific addr 2 high reg */
-#define GEM_SPADDR3LO (0x00000098 / 4) /* Specific addr 3 low reg */
-#define GEM_SPADDR3HI (0x0000009C / 4) /* Specific addr 3 high reg */
-#define GEM_SPADDR4LO (0x000000A0 / 4) /* Specific addr 4 low reg */
-#define GEM_SPADDR4HI (0x000000A4 / 4) /* Specific addr 4 high reg */
-#define GEM_TIDMATCH1 (0x000000A8 / 4) /* Type ID1 Match reg */
-#define GEM_TIDMATCH2 (0x000000AC / 4) /* Type ID2 Match reg */
-#define GEM_TIDMATCH3 (0x000000B0 / 4) /* Type ID3 Match reg */
-#define GEM_TIDMATCH4 (0x000000B4 / 4) /* Type ID4 Match reg */
-#define GEM_WOLAN (0x000000B8 / 4) /* Wake on LAN reg */
-#define GEM_IPGSTRETCH (0x000000BC / 4) /* IPG Stretch reg */
-#define GEM_SVLAN (0x000000C0 / 4) /* Stacked VLAN reg */
-#define GEM_MODID (0x000000FC / 4) /* Module ID reg */
-#define GEM_OCTTXLO (0x00000100 / 4) /* Octets transmitted Low reg */
-#define GEM_OCTTXHI (0x00000104 / 4) /* Octets transmitted High reg */
-#define GEM_TXCNT (0x00000108 / 4) /* Error-free Frames transmitted */
-#define GEM_TXBCNT (0x0000010C / 4) /* Error-free Broadcast Frames */
-#define GEM_TXMCNT (0x00000110 / 4) /* Error-free Multicast Frame */
-#define GEM_TXPAUSECNT (0x00000114 / 4) /* Pause Frames Transmitted */
-#define GEM_TX64CNT (0x00000118 / 4) /* Error-free 64 TX */
-#define GEM_TX65CNT (0x0000011C / 4) /* Error-free 65-127 TX */
-#define GEM_TX128CNT (0x00000120 / 4) /* Error-free 128-255 TX */
-#define GEM_TX256CNT (0x00000124 / 4) /* Error-free 256-511 */
-#define GEM_TX512CNT (0x00000128 / 4) /* Error-free 512-1023 TX */
-#define GEM_TX1024CNT (0x0000012C / 4) /* Error-free 1024-1518 TX */
-#define GEM_TX1519CNT (0x00000130 / 4) /* Error-free larger than 1519 TX */
-#define GEM_TXURUNCNT (0x00000134 / 4) /* TX under run error counter */
-#define GEM_SINGLECOLLCNT (0x00000138 / 4) /* Single Collision Frames */
-#define GEM_MULTCOLLCNT (0x0000013C / 4) /* Multiple Collision Frames */
-#define GEM_EXCESSCOLLCNT (0x00000140 / 4) /* Excessive Collision Frames */
-#define GEM_LATECOLLCNT (0x00000144 / 4) /* Late Collision Frames */
-#define GEM_DEFERTXCNT (0x00000148 / 4) /* Deferred Transmission Frames */
-#define GEM_CSENSECNT (0x0000014C / 4) /* Carrier Sense Error Counter */
-#define GEM_OCTRXLO (0x00000150 / 4) /* Octets Received register Low */
-#define GEM_OCTRXHI (0x00000154 / 4) /* Octets Received register High */
-#define GEM_RXCNT (0x00000158 / 4) /* Error-free Frames Received */
-#define GEM_RXBROADCNT (0x0000015C / 4) /* Error-free Broadcast Frames RX */
-#define GEM_RXMULTICNT (0x00000160 / 4) /* Error-free Multicast Frames RX */
-#define GEM_RXPAUSECNT (0x00000164 / 4) /* Pause Frames Received Counter */
-#define GEM_RX64CNT (0x00000168 / 4) /* Error-free 64 byte Frames RX */
-#define GEM_RX65CNT (0x0000016C / 4) /* Error-free 65-127B Frames RX */
-#define GEM_RX128CNT (0x00000170 / 4) /* Error-free 128-255B Frames RX */
-#define GEM_RX256CNT (0x00000174 / 4) /* Error-free 256-512B Frames RX */
-#define GEM_RX512CNT (0x00000178 / 4) /* Error-free 512-1023B Frames RX */
-#define GEM_RX1024CNT (0x0000017C / 4) /* Error-free 1024-1518B Frames RX */
-#define GEM_RX1519CNT (0x00000180 / 4) /* Error-free 1519-max Frames RX */
-#define GEM_RXUNDERCNT (0x00000184 / 4) /* Undersize Frames Received */
-#define GEM_RXOVERCNT (0x00000188 / 4) /* Oversize Frames Received */
-#define GEM_RXJABCNT (0x0000018C / 4) /* Jabbers Received Counter */
-#define GEM_RXFCSCNT (0x00000190 / 4) /* Frame Check seq. Error Counter */
-#define GEM_RXLENERRCNT (0x00000194 / 4) /* Length Field Error Counter */
-#define GEM_RXSYMERRCNT (0x00000198 / 4) /* Symbol Error Counter */
-#define GEM_RXALIGNERRCNT (0x0000019C / 4) /* Alignment Error Counter */
-#define GEM_RXRSCERRCNT (0x000001A0 / 4) /* Receive Resource Error Counter */
-#define GEM_RXORUNCNT (0x000001A4 / 4) /* Receive Overrun Counter */
-#define GEM_RXIPCSERRCNT (0x000001A8 / 4) /* IP header Checksum Err Counter */
-#define GEM_RXTCPCCNT (0x000001AC / 4) /* TCP Checksum Error Counter */
-#define GEM_RXUDPCCNT (0x000001B0 / 4) /* UDP Checksum Error Counter */
+REG32(NWCTRL, 0x0) /* Network Control reg */
+REG32(NWCFG, 0x4) /* Network Config reg */
+REG32(NWSTATUS, 0x8) /* Network Status reg */
+REG32(USERIO, 0xc) /* User IO reg */
+REG32(DMACFG, 0x10) /* DMA Control reg */
+REG32(TXSTATUS, 0x14) /* TX Status reg */
+REG32(RXQBASE, 0x18) /* RX Q Base address reg */
+REG32(TXQBASE, 0x1c) /* TX Q Base address reg */
+REG32(RXSTATUS, 0x20) /* RX Status reg */
+REG32(ISR, 0x24) /* Interrupt Status reg */
+REG32(IER, 0x28) /* Interrupt Enable reg */
+REG32(IDR, 0x2c) /* Interrupt Disable reg */
+REG32(IMR, 0x30) /* Interrupt Mask reg */
+REG32(PHYMNTNC, 0x34) /* Phy Maintenance reg */
+REG32(RXPAUSE, 0x38) /* RX Pause Time reg */
+REG32(TXPAUSE, 0x3c) /* TX Pause Time reg */
+REG32(TXPARTIALSF, 0x40) /* TX Partial Store and Forward */
+REG32(RXPARTIALSF, 0x44) /* RX Partial Store and Forward */
+REG32(JUMBO_MAX_LEN, 0x48) /* Max Jumbo Frame Size */
+REG32(HASHLO, 0x80) /* Hash Low address reg */
+REG32(HASHHI, 0x84) /* Hash High address reg */
+REG32(SPADDR1LO, 0x88) /* Specific addr 1 low reg */
+REG32(SPADDR1HI, 0x8c) /* Specific addr 1 high reg */
+REG32(SPADDR2LO, 0x90) /* Specific addr 2 low reg */
+REG32(SPADDR2HI, 0x94) /* Specific addr 2 high reg */
+REG32(SPADDR3LO, 0x98) /* Specific addr 3 low reg */
+REG32(SPADDR3HI, 0x9c) /* Specific addr 3 high reg */
+REG32(SPADDR4LO, 0xa0) /* Specific addr 4 low reg */
+REG32(SPADDR4HI, 0xa4) /* Specific addr 4 high reg */
+REG32(TIDMATCH1, 0xa8) /* Type ID1 Match reg */
+REG32(TIDMATCH2, 0xac) /* Type ID2 Match reg */
+REG32(TIDMATCH3, 0xb0) /* Type ID3 Match reg */
+REG32(TIDMATCH4, 0xb4) /* Type ID4 Match reg */
+REG32(WOLAN, 0xb8) /* Wake on LAN reg */
+REG32(IPGSTRETCH, 0xbc) /* IPG Stretch reg */
+REG32(SVLAN, 0xc0) /* Stacked VLAN reg */
+REG32(MODID, 0xfc) /* Module ID reg */
+REG32(OCTTXLO, 0x100) /* Octects transmitted Low reg */
+REG32(OCTTXHI, 0x104) /* Octects transmitted High reg */
+REG32(TXCNT, 0x108) /* Error-free Frames transmitted */
+REG32(TXBCNT, 0x10c) /* Error-free Broadcast Frames */
+REG32(TXMCNT, 0x110) /* Error-free Multicast Frame */
+REG32(TXPAUSECNT, 0x114) /* Pause Frames Transmitted */
+REG32(TX64CNT, 0x118) /* Error-free 64 TX */
+REG32(TX65CNT, 0x11c) /* Error-free 65-127 TX */
+REG32(TX128CNT, 0x120) /* Error-free 128-255 TX */
+REG32(TX256CNT, 0x124) /* Error-free 256-511 */
+REG32(TX512CNT, 0x128) /* Error-free 512-1023 TX */
+REG32(TX1024CNT, 0x12c) /* Error-free 1024-1518 TX */
+REG32(TX1519CNT, 0x130) /* Error-free larger than 1519 TX */
+REG32(TXURUNCNT, 0x134) /* TX under run error counter */
+REG32(SINGLECOLLCNT, 0x138) /* Single Collision Frames */
+REG32(MULTCOLLCNT, 0x13c) /* Multiple Collision Frames */
+REG32(EXCESSCOLLCNT, 0x140) /* Excessive Collision Frames */
+REG32(LATECOLLCNT, 0x144) /* Late Collision Frames */
+REG32(DEFERTXCNT, 0x148) /* Deferred Transmission Frames */
+REG32(CSENSECNT, 0x14c) /* Carrier Sense Error Counter */
+REG32(OCTRXLO, 0x150) /* Octects Received register Low */
+REG32(OCTRXHI, 0x154) /* Octects Received register High */
+REG32(RXCNT, 0x158) /* Error-free Frames Received */
+REG32(RXBROADCNT, 0x15c) /* Error-free Broadcast Frames RX */
+REG32(RXMULTICNT, 0x160) /* Error-free Multicast Frames RX */
+REG32(RXPAUSECNT, 0x164) /* Pause Frames Received Counter */
+REG32(RX64CNT, 0x168) /* Error-free 64 byte Frames RX */
+REG32(RX65CNT, 0x16c) /* Error-free 65-127B Frames RX */
+REG32(RX128CNT, 0x170) /* Error-free 128-255B Frames RX */
+REG32(RX256CNT, 0x174) /* Error-free 256-512B Frames RX */
+REG32(RX512CNT, 0x178) /* Error-free 512-1023B Frames RX */
+REG32(RX1024CNT, 0x17c) /* Error-free 1024-1518B Frames RX */
+REG32(RX1519CNT, 0x180) /* Error-free 1519-max Frames RX */
+REG32(RXUNDERCNT, 0x184) /* Undersize Frames Received */
+REG32(RXOVERCNT, 0x188) /* Oversize Frames Received */
+REG32(RXJABCNT, 0x18c) /* Jabbers Received Counter */
+REG32(RXFCSCNT, 0x190) /* Frame Check seq. Error Counter */
+REG32(RXLENERRCNT, 0x194) /* Length Field Error Counter */
+REG32(RXSYMERRCNT, 0x198) /* Symbol Error Counter */
+REG32(RXALIGNERRCNT, 0x19c) /* Alignment Error Counter */
+REG32(RXRSCERRCNT, 0x1a0) /* Receive Resource Error Counter */
+REG32(RXORUNCNT, 0x1a4) /* Receive Overrun Counter */
+REG32(RXIPCSERRCNT, 0x1a8) /* IP header Checksum Err Counter */
+REG32(RXTCPCCNT, 0x1ac) /* TCP Checksum Error Counter */
+REG32(RXUDPCCNT, 0x1b0) /* UDP Checksum Error Counter */
-#define GEM_1588S (0x000001D0 / 4) /* 1588 Timer Seconds */
-#define GEM_1588NS (0x000001D4 / 4) /* 1588 Timer Nanoseconds */
-#define GEM_1588ADJ (0x000001D8 / 4) /* 1588 Timer Adjust */
-#define GEM_1588INC (0x000001DC / 4) /* 1588 Timer Increment */
-#define GEM_PTPETXS (0x000001E0 / 4) /* PTP Event Frame Transmitted (s) */
-#define GEM_PTPETXNS (0x000001E4 / 4) /*
- * PTP Event Frame Transmitted (ns)
- */
-#define GEM_PTPERXS (0x000001E8 / 4) /* PTP Event Frame Received (s) */
-#define GEM_PTPERXNS (0x000001EC / 4) /* PTP Event Frame Received (ns) */
-#define GEM_PTPPTXS (0x000001E0 / 4) /* PTP Peer Frame Transmitted (s) */
-#define GEM_PTPPTXNS (0x000001E4 / 4) /* PTP Peer Frame Transmitted (ns) */
-#define GEM_PTPPRXS (0x000001E8 / 4) /* PTP Peer Frame Received (s) */
-#define GEM_PTPPRXNS (0x000001EC / 4) /* PTP Peer Frame Received (ns) */
+REG32(1588S, 0x1d0) /* 1588 Timer Seconds */
+REG32(1588NS, 0x1d4) /* 1588 Timer Nanoseconds */
+REG32(1588ADJ, 0x1d8) /* 1588 Timer Adjust */
+REG32(1588INC, 0x1dc) /* 1588 Timer Increment */
+REG32(PTPETXS, 0x1e0) /* PTP Event Frame Transmitted (s) */
+REG32(PTPETXNS, 0x1e4) /* PTP Event Frame Transmitted (ns) */
+REG32(PTPERXS, 0x1e8) /* PTP Event Frame Received (s) */
+REG32(PTPERXNS, 0x1ec) /* PTP Event Frame Received (ns) */
+REG32(PTPPTXS, 0x1e0) /* PTP Peer Frame Transmitted (s) */
+REG32(PTPPTXNS, 0x1e4) /* PTP Peer Frame Transmitted (ns) */
+REG32(PTPPRXS, 0x1e8) /* PTP Peer Frame Received (s) */
+REG32(PTPPRXNS, 0x1ec) /* PTP Peer Frame Received (ns) */
/* Design Configuration Registers */
-#define GEM_DESCONF (0x00000280 / 4)
-#define GEM_DESCONF2 (0x00000284 / 4)
-#define GEM_DESCONF3 (0x00000288 / 4)
-#define GEM_DESCONF4 (0x0000028C / 4)
-#define GEM_DESCONF5 (0x00000290 / 4)
-#define GEM_DESCONF6 (0x00000294 / 4)
+REG32(DESCONF, 0x280)
+REG32(DESCONF2, 0x284)
+REG32(DESCONF3, 0x288)
+REG32(DESCONF4, 0x28c)
+REG32(DESCONF5, 0x290)
+REG32(DESCONF6, 0x294)
#define GEM_DESCONF6_64B_MASK (1U << 23)
-#define GEM_DESCONF7 (0x00000298 / 4)
+REG32(DESCONF7, 0x298)
-#define GEM_INT_Q1_STATUS (0x00000400 / 4)
-#define GEM_INT_Q1_MASK (0x00000640 / 4)
+REG32(INT_Q1_STATUS, 0x400)
+REG32(INT_Q1_MASK, 0x640)
-#define GEM_TRANSMIT_Q1_PTR (0x00000440 / 4)
-#define GEM_TRANSMIT_Q7_PTR (GEM_TRANSMIT_Q1_PTR + 6)
+REG32(TRANSMIT_Q1_PTR, 0x440)
+REG32(TRANSMIT_Q7_PTR, 0x458)
-#define GEM_RECEIVE_Q1_PTR (0x00000480 / 4)
-#define GEM_RECEIVE_Q7_PTR (GEM_RECEIVE_Q1_PTR + 6)
+REG32(RECEIVE_Q1_PTR, 0x480)
+REG32(RECEIVE_Q7_PTR, 0x498)
-#define GEM_TBQPH (0x000004C8 / 4)
-#define GEM_RBQPH (0x000004D4 / 4)
+REG32(TBQPH, 0x4c8)
+REG32(RBQPH, 0x4d4)
-#define GEM_INT_Q1_ENABLE (0x00000600 / 4)
-#define GEM_INT_Q7_ENABLE (GEM_INT_Q1_ENABLE + 6)
+REG32(INT_Q1_ENABLE, 0x600)
+REG32(INT_Q7_ENABLE, 0x618)
-#define GEM_INT_Q1_DISABLE (0x00000620 / 4)
-#define GEM_INT_Q7_DISABLE (GEM_INT_Q1_DISABLE + 6)
+REG32(INT_Q1_DISABLE, 0x620)
+REG32(INT_Q7_DISABLE, 0x638)
-#define GEM_INT_Q1_MASK (0x00000640 / 4)
-#define GEM_INT_Q7_MASK (GEM_INT_Q1_MASK + 6)
-
-#define GEM_SCREENING_TYPE1_REGISTER_0 (0x00000500 / 4)
+REG32(SCREENING_TYPE1_REG0, 0x500)
#define GEM_ST1R_UDP_PORT_MATCH_ENABLE (1 << 29)
#define GEM_ST1R_DSTC_ENABLE (1 << 28)
#define GEM_ST1R_UDP_PORT_MATCH_SHIFT (12)
#define GEM_ST1R_UDP_PORT_MATCH_WIDTH (27 - GEM_ST1R_UDP_PORT_MATCH_SHIFT + 1)
#define GEM_ST1R_DSTC_MATCH_SHIFT (4)
#define GEM_ST1R_DSTC_MATCH_WIDTH (11 - GEM_ST1R_DSTC_MATCH_SHIFT + 1)
#define GEM_ST1R_QUEUE_SHIFT (0)
#define GEM_ST1R_QUEUE_WIDTH (3 - GEM_ST1R_QUEUE_SHIFT + 1)
-#define GEM_SCREENING_TYPE2_REGISTER_0 (0x00000540 / 4)
+REG32(SCREENING_TYPE2_REG0, 0x540)
#define GEM_ST2R_COMPARE_A_ENABLE (1 << 18)
#define GEM_ST2R_COMPARE_A_SHIFT (13)
#define GEM_ST2R_COMPARE_WIDTH (17 - GEM_ST2R_COMPARE_A_SHIFT + 1)
#define GEM_ST2R_ETHERTYPE_ENABLE (1 << 12)
@@ -194,12 +190,12 @@
#define GEM_ST2R_ETHERTYPE_INDEX_WIDTH (11 - GEM_ST2R_ETHERTYPE_INDEX_SHIFT \
+ 1)
#define GEM_ST2R_QUEUE_SHIFT (0)
#define GEM_ST2R_QUEUE_WIDTH (3 - GEM_ST2R_QUEUE_SHIFT + 1)
-#define GEM_SCREENING_TYPE2_ETHERTYPE_REG_0 (0x000006e0 / 4)
-#define GEM_TYPE2_COMPARE_0_WORD_0 (0x00000700 / 4)
+REG32(SCREENING_TYPE2_ETHERTYPE_REG0, 0x6e0)
+REG32(TYPE2_COMPARE_0_WORD_0, 0x700)
#define GEM_T2CW1_COMPARE_OFFSET_SHIFT (7)
#define GEM_T2CW1_COMPARE_OFFSET_WIDTH (8 - GEM_T2CW1_COMPARE_OFFSET_SHIFT + 1)
#define GEM_T2CW1_OFFSET_VALUE_SHIFT (0)
#define GEM_T2CW1_OFFSET_VALUE_WIDTH (6 - GEM_T2CW1_OFFSET_VALUE_SHIFT + 1)
@@ -323,11 +319,11 @@
static inline uint64_t tx_desc_get_buffer(CadenceGEMState *s, uint32_t *desc)
{
uint64_t ret = desc[0];
- if (s->regs[GEM_DMACFG] & GEM_DMACFG_ADDR_64B) {
+ if (s->regs[R_DMACFG] & GEM_DMACFG_ADDR_64B) {
ret |= (uint64_t)desc[2] << 32;
}
return ret;
}
@@ -368,24 +364,24 @@ static inline void print_gem_tx_desc(uint32_t *desc, uint8_t queue)
static inline uint64_t rx_desc_get_buffer(CadenceGEMState *s, uint32_t *desc)
{
uint64_t ret = desc[0] & ~0x3UL;
- if (s->regs[GEM_DMACFG] & GEM_DMACFG_ADDR_64B) {
+ if (s->regs[R_DMACFG] & GEM_DMACFG_ADDR_64B) {
ret |= (uint64_t)desc[2] << 32;
}
return ret;
}
static inline int gem_get_desc_len(CadenceGEMState *s, bool rx_n_tx)
{
int ret = 2;
- if (s->regs[GEM_DMACFG] & GEM_DMACFG_ADDR_64B) {
+ if (s->regs[R_DMACFG] & GEM_DMACFG_ADDR_64B) {
ret += 2;
}
- if (s->regs[GEM_DMACFG] & (rx_n_tx ? GEM_DMACFG_RX_BD_EXT
+ if (s->regs[R_DMACFG] & (rx_n_tx ? GEM_DMACFG_RX_BD_EXT
: GEM_DMACFG_TX_BD_EXT)) {
ret += 2;
}
assert(ret <= DESC_MAX_NUM_WORDS);
@@ -454,32 +450,32 @@ static inline void rx_desc_set_sar(uint32_t *desc, int sar_idx)
static const uint8_t broadcast_addr[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
static uint32_t gem_get_max_buf_len(CadenceGEMState *s, bool tx)
{
uint32_t size;
- if (s->regs[GEM_NWCFG] & GEM_NWCFG_JUMBO_FRAME) {
- size = s->regs[GEM_JUMBO_MAX_LEN];
+ if (s->regs[R_NWCFG] & GEM_NWCFG_JUMBO_FRAME) {
+ size = s->regs[R_JUMBO_MAX_LEN];
if (size > s->jumbo_max_len) {
size = s->jumbo_max_len;
qemu_log_mask(LOG_GUEST_ERROR, "GEM_JUMBO_MAX_LEN reg cannot be"
" greater than 0x%" PRIx32 "\n", s->jumbo_max_len);
}
} else if (tx) {
size = 1518;
} else {
- size = s->regs[GEM_NWCFG] & GEM_NWCFG_RCV_1538 ? 1538 : 1518;
+ size = s->regs[R_NWCFG] & GEM_NWCFG_RCV_1538 ? 1538 : 1518;
}
return size;
}
static void gem_set_isr(CadenceGEMState *s, int q, uint32_t flag)
{
if (q == 0) {
- s->regs[GEM_ISR] |= flag & ~(s->regs[GEM_IMR]);
+ s->regs[R_ISR] |= flag & ~(s->regs[R_IMR]);
} else {
- s->regs[GEM_INT_Q1_STATUS + q - 1] |= flag &
- ~(s->regs[GEM_INT_Q1_MASK + q - 1]);
+ s->regs[R_INT_Q1_STATUS + q - 1] |= flag &
+ ~(s->regs[R_INT_Q1_MASK + q - 1]);
}
}
/*
* gem_init_register_masks:
@@ -489,47 +485,47 @@ static void gem_set_isr(CadenceGEMState *s, int q, uint32_t flag)
static void gem_init_register_masks(CadenceGEMState *s)
{
unsigned int i;
/* Mask of register bits which are read only */
memset(&s->regs_ro[0], 0, sizeof(s->regs_ro));
- s->regs_ro[GEM_NWCTRL] = 0xFFF80000;
- s->regs_ro[GEM_NWSTATUS] = 0xFFFFFFFF;
- s->regs_ro[GEM_DMACFG] = 0x8E00F000;
- s->regs_ro[GEM_TXSTATUS] = 0xFFFFFE08;
- s->regs_ro[GEM_RXQBASE] = 0x00000003;
- s->regs_ro[GEM_TXQBASE] = 0x00000003;
- s->regs_ro[GEM_RXSTATUS] = 0xFFFFFFF0;
- s->regs_ro[GEM_ISR] = 0xFFFFFFFF;
- s->regs_ro[GEM_IMR] = 0xFFFFFFFF;
- s->regs_ro[GEM_MODID] = 0xFFFFFFFF;
+ s->regs_ro[R_NWCTRL] = 0xFFF80000;
+ s->regs_ro[R_NWSTATUS] = 0xFFFFFFFF;
+ s->regs_ro[R_DMACFG] = 0x8E00F000;
+ s->regs_ro[R_TXSTATUS] = 0xFFFFFE08;
+ s->regs_ro[R_RXQBASE] = 0x00000003;
+ s->regs_ro[R_TXQBASE] = 0x00000003;
+ s->regs_ro[R_RXSTATUS] = 0xFFFFFFF0;
+ s->regs_ro[R_ISR] = 0xFFFFFFFF;
+ s->regs_ro[R_IMR] = 0xFFFFFFFF;
+ s->regs_ro[R_MODID] = 0xFFFFFFFF;
for (i = 0; i < s->num_priority_queues; i++) {
- s->regs_ro[GEM_INT_Q1_STATUS + i] = 0xFFFFFFFF;
- s->regs_ro[GEM_INT_Q1_ENABLE + i] = 0xFFFFF319;
- s->regs_ro[GEM_INT_Q1_DISABLE + i] = 0xFFFFF319;
- s->regs_ro[GEM_INT_Q1_MASK + i] = 0xFFFFFFFF;
+ s->regs_ro[R_INT_Q1_STATUS + i] = 0xFFFFFFFF;
+ s->regs_ro[R_INT_Q1_ENABLE + i] = 0xFFFFF319;
+ s->regs_ro[R_INT_Q1_DISABLE + i] = 0xFFFFF319;
+ s->regs_ro[R_INT_Q1_MASK + i] = 0xFFFFFFFF;
}
/* Mask of register bits which are clear on read */
memset(&s->regs_rtc[0], 0, sizeof(s->regs_rtc));
- s->regs_rtc[GEM_ISR] = 0xFFFFFFFF;
+ s->regs_rtc[R_ISR] = 0xFFFFFFFF;
for (i = 0; i < s->num_priority_queues; i++) {
- s->regs_rtc[GEM_INT_Q1_STATUS + i] = 0x00000CE6;
+ s->regs_rtc[R_INT_Q1_STATUS + i] = 0x00000CE6;
}
/* Mask of register bits which are write 1 to clear */
memset(&s->regs_w1c[0], 0, sizeof(s->regs_w1c));
- s->regs_w1c[GEM_TXSTATUS] = 0x000001F7;
- s->regs_w1c[GEM_RXSTATUS] = 0x0000000F;
+ s->regs_w1c[R_TXSTATUS] = 0x000001F7;
+ s->regs_w1c[R_RXSTATUS] = 0x0000000F;
/* Mask of register bits which are write only */
memset(&s->regs_wo[0], 0, sizeof(s->regs_wo));
- s->regs_wo[GEM_NWCTRL] = 0x00073E60;
- s->regs_wo[GEM_IER] = 0x07FFFFFF;
- s->regs_wo[GEM_IDR] = 0x07FFFFFF;
+ s->regs_wo[R_NWCTRL] = 0x00073E60;
+ s->regs_wo[R_IER] = 0x07FFFFFF;
+ s->regs_wo[R_IDR] = 0x07FFFFFF;
for (i = 0; i < s->num_priority_queues; i++) {
- s->regs_wo[GEM_INT_Q1_ENABLE + i] = 0x00000CE6;
- s->regs_wo[GEM_INT_Q1_DISABLE + i] = 0x00000CE6;
+ s->regs_wo[R_INT_Q1_ENABLE + i] = 0x00000CE6;
+ s->regs_wo[R_INT_Q1_DISABLE + i] = 0x00000CE6;
}
}
/*
* phy_update_link:
@@ -559,11 +555,11 @@ static bool gem_can_receive(NetClientState *nc)
int i;
s = qemu_get_nic_opaque(nc);
/* Do nothing if receive is not enabled. */
- if (!(s->regs[GEM_NWCTRL] & GEM_NWCTRL_RXENA)) {
+ if (!(s->regs[R_NWCTRL] & GEM_NWCTRL_RXENA)) {
if (s->can_rx_state != 1) {
s->can_rx_state = 1;
DB_PRINT("can't receive - no enable\n");
}
return false;
@@ -596,14 +592,14 @@ static bool gem_can_receive(NetClientState *nc)
*/
static void gem_update_int_status(CadenceGEMState *s)
{
int i;
- qemu_set_irq(s->irq[0], !!s->regs[GEM_ISR]);
+ qemu_set_irq(s->irq[0], !!s->regs[R_ISR]);
for (i = 1; i < s->num_priority_queues; ++i) {
- qemu_set_irq(s->irq[i], !!s->regs[GEM_INT_Q1_STATUS + i - 1]);
+ qemu_set_irq(s->irq[i], !!s->regs[R_INT_Q1_STATUS + i - 1]);
}
}
/*
* gem_receive_updatestats:
@@ -613,43 +609,43 @@ static void gem_receive_updatestats(CadenceGEMState *s, const uint8_t *packet,
unsigned bytes)
{
uint64_t octets;
/* Total octets (bytes) received */
- octets = ((uint64_t)(s->regs[GEM_OCTRXLO]) << 32) |
- s->regs[GEM_OCTRXHI];
+ octets = ((uint64_t)(s->regs[R_OCTRXLO]) << 32) |
+ s->regs[R_OCTRXHI];
octets += bytes;
- s->regs[GEM_OCTRXLO] = octets >> 32;
- s->regs[GEM_OCTRXHI] = octets;
+ s->regs[R_OCTRXLO] = octets >> 32;
+ s->regs[R_OCTRXHI] = octets;
/* Error-free Frames received */
- s->regs[GEM_RXCNT]++;
+ s->regs[R_RXCNT]++;
/* Error-free Broadcast Frames counter */
if (!memcmp(packet, broadcast_addr, 6)) {
- s->regs[GEM_RXBROADCNT]++;
+ s->regs[R_RXBROADCNT]++;
}
/* Error-free Multicast Frames counter */
if (packet[0] == 0x01) {
- s->regs[GEM_RXMULTICNT]++;
+ s->regs[R_RXMULTICNT]++;
}
if (bytes <= 64) {
- s->regs[GEM_RX64CNT]++;
+ s->regs[R_RX64CNT]++;
} else if (bytes <= 127) {
- s->regs[GEM_RX65CNT]++;
+ s->regs[R_RX65CNT]++;
} else if (bytes <= 255) {
- s->regs[GEM_RX128CNT]++;
+ s->regs[R_RX128CNT]++;
} else if (bytes <= 511) {
- s->regs[GEM_RX256CNT]++;
+ s->regs[R_RX256CNT]++;
} else if (bytes <= 1023) {
- s->regs[GEM_RX512CNT]++;
+ s->regs[R_RX512CNT]++;
} else if (bytes <= 1518) {
- s->regs[GEM_RX1024CNT]++;
+ s->regs[R_RX1024CNT]++;
} else {
- s->regs[GEM_RX1519CNT]++;
+ s->regs[R_RX1519CNT]++;
}
}
/*
* Get the MAC Address bit from the specified position
@@ -704,39 +700,39 @@ static int gem_mac_address_filter(CadenceGEMState *s, const uint8_t *packet)
{
uint8_t *gem_spaddr;
int i, is_mc;
/* Promiscuous mode? */
- if (s->regs[GEM_NWCFG] & GEM_NWCFG_PROMISC) {
+ if (s->regs[R_NWCFG] & GEM_NWCFG_PROMISC) {
return GEM_RX_PROMISCUOUS_ACCEPT;
}
if (!memcmp(packet, broadcast_addr, 6)) {
/* Reject broadcast packets? */
- if (s->regs[GEM_NWCFG] & GEM_NWCFG_BCAST_REJ) {
+ if (s->regs[R_NWCFG] & GEM_NWCFG_BCAST_REJ) {
return GEM_RX_REJECT;
}
return GEM_RX_BROADCAST_ACCEPT;
}
/* Accept packets -w- hash match? */
is_mc = is_multicast_ether_addr(packet);
- if ((is_mc && (s->regs[GEM_NWCFG] & GEM_NWCFG_MCAST_HASH)) ||
- (!is_mc && (s->regs[GEM_NWCFG] & GEM_NWCFG_UCAST_HASH))) {
+ if ((is_mc && (s->regs[R_NWCFG] & GEM_NWCFG_MCAST_HASH)) ||
+ (!is_mc && (s->regs[R_NWCFG] & GEM_NWCFG_UCAST_HASH))) {
uint64_t buckets;
unsigned hash_index;
hash_index = calc_mac_hash(packet);
- buckets = ((uint64_t)s->regs[GEM_HASHHI] << 32) | s->regs[GEM_HASHLO];
+ buckets = ((uint64_t)s->regs[R_HASHHI] << 32) | s->regs[R_HASHLO];
if ((buckets >> hash_index) & 1) {
return is_mc ? GEM_RX_MULTICAST_HASH_ACCEPT
: GEM_RX_UNICAST_HASH_ACCEPT;
}
}
/* Check all 4 specific addresses */
- gem_spaddr = (uint8_t *)&(s->regs[GEM_SPADDR1LO]);
+ gem_spaddr = (uint8_t *)&(s->regs[R_SPADDR1LO]);
for (i = 3; i >= 0; i--) {
if (s->sar_active[i] && !memcmp(packet, gem_spaddr + 8 * i, 6)) {
return GEM_RX_SAR_ACCEPT + i;
}
}
@@ -752,11 +748,11 @@ static int get_queue_from_screen(CadenceGEMState *s, uint8_t *rxbuf_ptr,
uint32_t reg;
bool matched, mismatched;
int i, j;
for (i = 0; i < s->num_type1_screeners; i++) {
- reg = s->regs[GEM_SCREENING_TYPE1_REGISTER_0 + i];
+ reg = s->regs[R_SCREENING_TYPE1_REG0 + i];
matched = false;
mismatched = false;
/* Screening is based on UDP Port */
if (reg & GEM_ST1R_UDP_PORT_MATCH_ENABLE) {
@@ -784,11 +780,11 @@ static int get_queue_from_screen(CadenceGEMState *s, uint8_t *rxbuf_ptr,
return extract32(reg, GEM_ST1R_QUEUE_SHIFT, GEM_ST1R_QUEUE_WIDTH);
}
}
for (i = 0; i < s->num_type2_screeners; i++) {
- reg = s->regs[GEM_SCREENING_TYPE2_REGISTER_0 + i];
+ reg = s->regs[R_SCREENING_TYPE2_REG0 + i];
matched = false;
mismatched = false;
if (reg & GEM_ST2R_ETHERTYPE_ENABLE) {
uint16_t type = rxbuf_ptr[12] << 8 | rxbuf_ptr[13];
@@ -797,11 +793,11 @@ static int get_queue_from_screen(CadenceGEMState *s, uint8_t *rxbuf_ptr,
if (et_idx > s->num_type2_screeners) {
qemu_log_mask(LOG_GUEST_ERROR, "Out of range ethertype "
"register index: %d\n", et_idx);
}
- if (type == s->regs[GEM_SCREENING_TYPE2_ETHERTYPE_REG_0 +
+ if (type == s->regs[R_SCREENING_TYPE2_ETHERTYPE_REG0 +
et_idx]) {
matched = true;
} else {
mismatched = true;
}
@@ -821,12 +817,12 @@ static int get_queue_from_screen(CadenceGEMState *s, uint8_t *rxbuf_ptr,
if (cr_idx > s->num_type2_screeners) {
qemu_log_mask(LOG_GUEST_ERROR, "Out of range compare "
"register index: %d\n", cr_idx);
}
- cr0 = s->regs[GEM_TYPE2_COMPARE_0_WORD_0 + cr_idx * 2];
- cr1 = s->regs[GEM_TYPE2_COMPARE_0_WORD_0 + cr_idx * 2 + 1];
+ cr0 = s->regs[R_TYPE2_COMPARE_0_WORD_0 + cr_idx * 2];
+ cr1 = s->regs[R_TYPE2_COMPARE_0_WORD_0 + cr_idx * 2 + 1];
offset = extract32(cr1, GEM_T2CW1_OFFSET_VALUE_SHIFT,
GEM_T2CW1_OFFSET_VALUE_WIDTH);
switch (extract32(cr1, GEM_T2CW1_COMPARE_OFFSET_SHIFT,
GEM_T2CW1_COMPARE_OFFSET_WIDTH)) {
@@ -869,15 +865,15 @@ static uint32_t gem_get_queue_base_addr(CadenceGEMState *s, bool tx, int q)
{
uint32_t base_addr = 0;
switch (q) {
case 0:
- base_addr = s->regs[tx ? GEM_TXQBASE : GEM_RXQBASE];
+ base_addr = s->regs[tx ? R_TXQBASE : R_RXQBASE];
break;
case 1 ... (MAX_PRIORITY_QUEUES - 1):
- base_addr = s->regs[(tx ? GEM_TRANSMIT_Q1_PTR :
- GEM_RECEIVE_Q1_PTR) + q - 1];
+ base_addr = s->regs[(tx ? R_TRANSMIT_Q1_PTR :
+ R_RECEIVE_Q1_PTR) + q - 1];
break;
default:
g_assert_not_reached();
};
@@ -896,12 +892,12 @@ static inline uint32_t gem_get_rx_queue_base_addr(CadenceGEMState *s, int q)
static hwaddr gem_get_desc_addr(CadenceGEMState *s, bool tx, int q)
{
hwaddr desc_addr = 0;
- if (s->regs[GEM_DMACFG] & GEM_DMACFG_ADDR_64B) {
- desc_addr = s->regs[tx ? GEM_TBQPH : GEM_RBQPH];
+ if (s->regs[R_DMACFG] & GEM_DMACFG_ADDR_64B) {
+ desc_addr = s->regs[tx ? R_TBQPH : R_RBQPH];
}
desc_addr <<= 32;
desc_addr |= tx ? s->tx_desc_addr[q] : s->rx_desc_addr[q];
return desc_addr;
}
@@ -928,11 +924,11 @@ static void gem_get_rx_desc(CadenceGEMState *s, int q)
sizeof(uint32_t) * gem_get_desc_len(s, true));
/* Descriptor owned by software ? */
if (rx_desc_get_ownership(s->rx_desc[q]) == 1) {
DB_PRINT("descriptor 0x%" HWADDR_PRIx " owned by sw.\n", desc_addr);
- s->regs[GEM_RXSTATUS] |= GEM_RXSTATUS_NOBUF;
+ s->regs[R_RXSTATUS] |= GEM_RXSTATUS_NOBUF;
gem_set_isr(s, q, GEM_INT_RXUSED);
/* Handle interrupt consequences */
gem_update_int_status(s);
}
}
@@ -956,11 +952,11 @@ static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size)
if (maf == GEM_RX_REJECT) {
return size; /* no, drop silently b/c it's not an error */
}
/* Discard packets with receive length error enabled ? */
- if (s->regs[GEM_NWCFG] & GEM_NWCFG_LERR_DISC) {
+ if (s->regs[R_NWCFG] & GEM_NWCFG_LERR_DISC) {
unsigned type_len;
/* Fish the ethertype / length field out of the RX packet */
type_len = buf[12] << 8 | buf[13];
/* It is a length field, not an ethertype */
@@ -973,17 +969,17 @@ static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size)
}
/*
* Determine configured receive buffer offset (probably 0)
*/
- rxbuf_offset = (s->regs[GEM_NWCFG] & GEM_NWCFG_BUFF_OFST_M) >>
+ rxbuf_offset = (s->regs[R_NWCFG] & GEM_NWCFG_BUFF_OFST_M) >>
GEM_NWCFG_BUFF_OFST_S;
/* The configure size of each receive buffer. Determines how many
* buffers needed to hold this packet.
*/
- rxbufsize = ((s->regs[GEM_DMACFG] & GEM_DMACFG_RBUFSZ_M) >>
+ rxbufsize = ((s->regs[R_DMACFG] & GEM_DMACFG_RBUFSZ_M) >>
GEM_DMACFG_RBUFSZ_S) * GEM_DMACFG_RBUFSZ_MUL;
bytes_to_copy = size;
/* Hardware allows a zero value here but warns against it. To avoid QEMU
* indefinite loops we enforce a minimum value here
@@ -999,11 +995,11 @@ static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size)
if (size < 60) {
size = 60;
}
/* Strip of FCS field ? (usually yes) */
- if (s->regs[GEM_NWCFG] & GEM_NWCFG_STRIP_FCS) {
+ if (s->regs[R_NWCFG] & GEM_NWCFG_STRIP_FCS) {
rxbuf_ptr = (void *)buf;
} else {
unsigned crc_val;
if (size > MAX_FRAME_SIZE - sizeof(crc_val)) {
@@ -1105,11 +1101,11 @@ static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size)
}
/* Count it */
gem_receive_updatestats(s, buf, size);
- s->regs[GEM_RXSTATUS] |= GEM_RXSTATUS_FRMRCVD;
+ s->regs[R_RXSTATUS] |= GEM_RXSTATUS_FRMRCVD;
gem_set_isr(s, q, GEM_INT_RXCMPL);
/* Handle interrupt consequences */
gem_update_int_status(s);
@@ -1124,43 +1120,43 @@ static void gem_transmit_updatestats(CadenceGEMState *s, const uint8_t *packet,
unsigned bytes)
{
uint64_t octets;
/* Total octets (bytes) transmitted */
- octets = ((uint64_t)(s->regs[GEM_OCTTXLO]) << 32) |
- s->regs[GEM_OCTTXHI];
+ octets = ((uint64_t)(s->regs[R_OCTTXLO]) << 32) |
+ s->regs[R_OCTTXHI];
octets += bytes;
- s->regs[GEM_OCTTXLO] = octets >> 32;
- s->regs[GEM_OCTTXHI] = octets;
+ s->regs[R_OCTTXLO] = octets >> 32;
+ s->regs[R_OCTTXHI] = octets;
/* Error-free Frames transmitted */
- s->regs[GEM_TXCNT]++;
+ s->regs[R_TXCNT]++;
/* Error-free Broadcast Frames counter */
if (!memcmp(packet, broadcast_addr, 6)) {
- s->regs[GEM_TXBCNT]++;
+ s->regs[R_TXBCNT]++;
}
/* Error-free Multicast Frames counter */
if (packet[0] == 0x01) {
- s->regs[GEM_TXMCNT]++;
+ s->regs[R_TXMCNT]++;
}
if (bytes <= 64) {
- s->regs[GEM_TX64CNT]++;
+ s->regs[R_TX64CNT]++;
} else if (bytes <= 127) {
- s->regs[GEM_TX65CNT]++;
+ s->regs[R_TX65CNT]++;
} else if (bytes <= 255) {
- s->regs[GEM_TX128CNT]++;
+ s->regs[R_TX128CNT]++;
} else if (bytes <= 511) {
- s->regs[GEM_TX256CNT]++;
+ s->regs[R_TX256CNT]++;
} else if (bytes <= 1023) {
- s->regs[GEM_TX512CNT]++;
+ s->regs[R_TX512CNT]++;
} else if (bytes <= 1518) {
- s->regs[GEM_TX1024CNT]++;
+ s->regs[R_TX1024CNT]++;
} else {
- s->regs[GEM_TX1519CNT]++;
+ s->regs[R_TX1519CNT]++;
}
}
/*
* gem_transmit:
@@ -1173,11 +1169,11 @@ static void gem_transmit(CadenceGEMState *s)
uint8_t *p;
unsigned total_bytes;
int q = 0;
/* Do nothing if transmit is not enabled. */
- if (!(s->regs[GEM_NWCTRL] & GEM_NWCTRL_TXENA)) {
+ if (!(s->regs[R_NWCTRL] & GEM_NWCTRL_TXENA)) {
return;
}
DB_PRINT("\n");
@@ -1198,11 +1194,11 @@ static void gem_transmit(CadenceGEMState *s)
sizeof(uint32_t) * gem_get_desc_len(s, false));
/* Handle all descriptors owned by hardware */
while (tx_desc_get_used(desc) == 0) {
/* Do nothing if transmit is not enabled. */
- if (!(s->regs[GEM_NWCTRL] & GEM_NWCTRL_TXENA)) {
+ if (!(s->regs[R_NWCTRL] & GEM_NWCTRL_TXENA)) {
return;
}
print_gem_tx_desc(desc, q);
/* The real hardware would eat this (and possibly crash).
@@ -1256,26 +1252,26 @@ static void gem_transmit(CadenceGEMState *s)
s->tx_desc_addr[q] = packet_desc_addr +
4 * gem_get_desc_len(s, false);
}
DB_PRINT("TX descriptor next: 0x%08x\n", s->tx_desc_addr[q]);
- s->regs[GEM_TXSTATUS] |= GEM_TXSTATUS_TXCMPL;
+ s->regs[R_TXSTATUS] |= GEM_TXSTATUS_TXCMPL;
gem_set_isr(s, q, GEM_INT_TXCMPL);
/* Handle interrupt consequences */
gem_update_int_status(s);
/* Is checksum offload enabled? */
- if (s->regs[GEM_DMACFG] & GEM_DMACFG_TXCSUM_OFFL) {
+ if (s->regs[R_DMACFG] & GEM_DMACFG_TXCSUM_OFFL) {
net_checksum_calculate(s->tx_packet, total_bytes, CSUM_ALL);
}
/* Update MAC statistics */
gem_transmit_updatestats(s, s->tx_packet, total_bytes);
/* Send the packet somewhere */
- if (s->phy_loop || (s->regs[GEM_NWCTRL] &
+ if (s->phy_loop || (s->regs[R_NWCTRL] &
GEM_NWCTRL_LOCALLOOP)) {
qemu_receive_packet(qemu_get_queue(s->nic), s->tx_packet,
total_bytes);
} else {
qemu_send_packet(qemu_get_queue(s->nic), s->tx_packet,
@@ -1287,13 +1283,12 @@ static void gem_transmit(CadenceGEMState *s)
total_bytes = 0;
}
/* read next descriptor */
if (tx_desc_get_wrap(desc)) {
-
- if (s->regs[GEM_DMACFG] & GEM_DMACFG_ADDR_64B) {
- packet_desc_addr = s->regs[GEM_TBQPH];
+ if (s->regs[R_DMACFG] & GEM_DMACFG_ADDR_64B) {
+ packet_desc_addr = s->regs[R_TBQPH];
packet_desc_addr <<= 32;
} else {
packet_desc_addr = 0;
}
packet_desc_addr |= gem_get_tx_queue_base_addr(s, q);
@@ -1305,11 +1300,11 @@ static void gem_transmit(CadenceGEMState *s)
MEMTXATTRS_UNSPECIFIED, desc,
sizeof(uint32_t) * gem_get_desc_len(s, false));
}
if (tx_desc_get_used(desc)) {
- s->regs[GEM_TXSTATUS] |= GEM_TXSTATUS_USED;
+ s->regs[R_TXSTATUS] |= GEM_TXSTATUS_USED;
/* IRQ TXUSED is defined only for queue 0 */
if (q == 0) {
gem_set_isr(s, 0, GEM_INT_TXUSED);
}
gem_update_int_status(s);
@@ -1351,34 +1346,34 @@ static void gem_reset(DeviceState *d)
DB_PRINT("\n");
/* Set post reset register values */
memset(&s->regs[0], 0, sizeof(s->regs));
- s->regs[GEM_NWCFG] = 0x00080000;
- s->regs[GEM_NWSTATUS] = 0x00000006;
- s->regs[GEM_DMACFG] = 0x00020784;
- s->regs[GEM_IMR] = 0x07ffffff;
- s->regs[GEM_TXPAUSE] = 0x0000ffff;
- s->regs[GEM_TXPARTIALSF] = 0x000003ff;
- s->regs[GEM_RXPARTIALSF] = 0x000003ff;
- s->regs[GEM_MODID] = s->revision;
- s->regs[GEM_DESCONF] = 0x02D00111;
- s->regs[GEM_DESCONF2] = 0x2ab10000 | s->jumbo_max_len;
- s->regs[GEM_DESCONF5] = 0x002f2045;
- s->regs[GEM_DESCONF6] = GEM_DESCONF6_64B_MASK;
- s->regs[GEM_INT_Q1_MASK] = 0x00000CE6;
- s->regs[GEM_JUMBO_MAX_LEN] = s->jumbo_max_len;
+ s->regs[R_NWCFG] = 0x00080000;
+ s->regs[R_NWSTATUS] = 0x00000006;
+ s->regs[R_DMACFG] = 0x00020784;
+ s->regs[R_IMR] = 0x07ffffff;
+ s->regs[R_TXPAUSE] = 0x0000ffff;
+ s->regs[R_TXPARTIALSF] = 0x000003ff;
+ s->regs[R_RXPARTIALSF] = 0x000003ff;
+ s->regs[R_MODID] = s->revision;
+ s->regs[R_DESCONF] = 0x02D00111;
+ s->regs[R_DESCONF2] = 0x2ab10000 | s->jumbo_max_len;
+ s->regs[R_DESCONF5] = 0x002f2045;
+ s->regs[R_DESCONF6] = GEM_DESCONF6_64B_MASK;
+ s->regs[R_INT_Q1_MASK] = 0x00000CE6;
+ s->regs[R_JUMBO_MAX_LEN] = s->jumbo_max_len;
if (s->num_priority_queues > 1) {
queues_mask = MAKE_64BIT_MASK(1, s->num_priority_queues - 1);
- s->regs[GEM_DESCONF6] |= queues_mask;
+ s->regs[R_DESCONF6] |= queues_mask;
}
/* Set MAC address */
a = &s->conf.macaddr.a[0];
- s->regs[GEM_SPADDR1LO] = a[0] | (a[1] << 8) | (a[2] << 16) | (a[3] << 24);
- s->regs[GEM_SPADDR1HI] = a[4] | (a[5] << 8);
+ s->regs[R_SPADDR1LO] = a[0] | (a[1] << 8) | (a[2] << 16) | (a[3] << 24);
+ s->regs[R_SPADDR1HI] = a[4] | (a[5] << 8);
for (i = 0; i < 4; i++) {
s->sar_active[i] = false;
}
@@ -1435,15 +1430,15 @@ static uint64_t gem_read(void *opaque, hwaddr offset, unsigned size)
retval = s->regs[offset];
DB_PRINT("offset: 0x%04x read: 0x%08x\n", (unsigned)offset*4, retval);
switch (offset) {
- case GEM_ISR:
+ case R_ISR:
DB_PRINT("lowering irqs on ISR read\n");
/* The interrupts get updated at the end of the function. */
break;
- case GEM_PHYMNTNC:
+ case R_PHYMNTNC:
if (retval & GEM_PHYMNTNC_OP_R) {
uint32_t phy_addr, reg_num;
phy_addr = (retval & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT;
if (phy_addr == s->phy_addr) {
@@ -1493,11 +1488,11 @@ static void gem_write(void *opaque, hwaddr offset, uint64_t val,
/* do w1c */
s->regs[offset] &= ~(s->regs_w1c[offset] & val);
/* Handle register write side effects */
switch (offset) {
- case GEM_NWCTRL:
+ case R_NWCTRL:
if (val & GEM_NWCTRL_RXENA) {
for (i = 0; i < s->num_priority_queues; ++i) {
gem_get_rx_desc(s, i);
}
}
@@ -1513,60 +1508,60 @@ static void gem_write(void *opaque, hwaddr offset, uint64_t val,
if (gem_can_receive(qemu_get_queue(s->nic))) {
qemu_flush_queued_packets(qemu_get_queue(s->nic));
}
break;
- case GEM_TXSTATUS:
+ case R_TXSTATUS:
gem_update_int_status(s);
break;
- case GEM_RXQBASE:
+ case R_RXQBASE:
s->rx_desc_addr[0] = val;
break;
- case GEM_RECEIVE_Q1_PTR ... GEM_RECEIVE_Q7_PTR:
- s->rx_desc_addr[offset - GEM_RECEIVE_Q1_PTR + 1] = val;
+ case R_RECEIVE_Q1_PTR ... R_RECEIVE_Q7_PTR:
+ s->rx_desc_addr[offset - R_RECEIVE_Q1_PTR + 1] = val;
break;
- case GEM_TXQBASE:
+ case R_TXQBASE:
s->tx_desc_addr[0] = val;
break;
- case GEM_TRANSMIT_Q1_PTR ... GEM_TRANSMIT_Q7_PTR:
- s->tx_desc_addr[offset - GEM_TRANSMIT_Q1_PTR + 1] = val;
+ case R_TRANSMIT_Q1_PTR ... R_TRANSMIT_Q7_PTR:
+ s->tx_desc_addr[offset - R_TRANSMIT_Q1_PTR + 1] = val;
break;
- case GEM_RXSTATUS:
+ case R_RXSTATUS:
gem_update_int_status(s);
break;
- case GEM_IER:
- s->regs[GEM_IMR] &= ~val;
+ case R_IER:
+ s->regs[R_IMR] &= ~val;
gem_update_int_status(s);
break;
- case GEM_JUMBO_MAX_LEN:
- s->regs[GEM_JUMBO_MAX_LEN] = val & MAX_JUMBO_FRAME_SIZE_MASK;
+ case R_JUMBO_MAX_LEN:
+ s->regs[R_JUMBO_MAX_LEN] = val & MAX_JUMBO_FRAME_SIZE_MASK;
break;
- case GEM_INT_Q1_ENABLE ... GEM_INT_Q7_ENABLE:
- s->regs[GEM_INT_Q1_MASK + offset - GEM_INT_Q1_ENABLE] &= ~val;
+ case R_INT_Q1_ENABLE ... R_INT_Q7_ENABLE:
+ s->regs[R_INT_Q1_MASK + offset - R_INT_Q1_ENABLE] &= ~val;
gem_update_int_status(s);
break;
- case GEM_IDR:
- s->regs[GEM_IMR] |= val;
+ case R_IDR:
+ s->regs[R_IMR] |= val;
gem_update_int_status(s);
break;
- case GEM_INT_Q1_DISABLE ... GEM_INT_Q7_DISABLE:
- s->regs[GEM_INT_Q1_MASK + offset - GEM_INT_Q1_DISABLE] |= val;
+ case R_INT_Q1_DISABLE ... R_INT_Q7_DISABLE:
+ s->regs[R_INT_Q1_MASK + offset - R_INT_Q1_DISABLE] |= val;
gem_update_int_status(s);
break;
- case GEM_SPADDR1LO:
- case GEM_SPADDR2LO:
- case GEM_SPADDR3LO:
- case GEM_SPADDR4LO:
- s->sar_active[(offset - GEM_SPADDR1LO) / 2] = false;
+ case R_SPADDR1LO:
+ case R_SPADDR2LO:
+ case R_SPADDR3LO:
+ case R_SPADDR4LO:
+ s->sar_active[(offset - R_SPADDR1LO) / 2] = false;
break;
- case GEM_SPADDR1HI:
- case GEM_SPADDR2HI:
- case GEM_SPADDR3HI:
- case GEM_SPADDR4HI:
- s->sar_active[(offset - GEM_SPADDR1HI) / 2] = true;
+ case R_SPADDR1HI:
+ case R_SPADDR2HI:
+ case R_SPADDR3HI:
+ case R_SPADDR4HI:
+ s->sar_active[(offset - R_SPADDR1HI) / 2] = true;
break;
- case GEM_PHYMNTNC:
+ case R_PHYMNTNC:
if (val & GEM_PHYMNTNC_OP_W) {
uint32_t phy_addr, reg_num;
phy_addr = (val & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT;
if (phy_addr == s->phy_addr) {
--
2.39.2
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH 02/11] hw/net/cadence_gem: use FIELD for screening registers
2023-10-17 19:44 [PATCH 00/11] Various updates for the Cadence GEM model Luc Michel
2023-10-17 19:44 ` [PATCH 01/11] hw/net/cadence_gem: use REG32 macro for register definitions Luc Michel
@ 2023-10-17 19:44 ` Luc Michel
2023-10-18 10:14 ` Boddu, Sai Pavan
2023-10-17 19:44 ` [PATCH 03/11] hw/net/cadence_gem: use FIELD to describe NWCTRL register fields Luc Michel
` (9 subsequent siblings)
11 siblings, 1 reply; 25+ messages in thread
From: Luc Michel @ 2023-10-17 19:44 UTC (permalink / raw)
To: qemu-devel
Cc: Luc Michel, qemu-arm, Edgar E . Iglesias, Alistair Francis,
Peter Maydell, Jason Wang, Philippe Mathieu-Daudé,
Francisco Iglesias, Frederic Konrad, Sai Pavan Boddu
Describe screening registers fields using the FIELD macros.
Signed-off-by: Luc Michel <luc.michel@amd.com>
---
hw/net/cadence_gem.c | 92 ++++++++++++++++++++++----------------------
1 file changed, 47 insertions(+), 45 deletions(-)
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index 0e5744ecd7..f01c81de97 100644
--- a/hw/net/cadence_gem.c
+++ b/hw/net/cadence_gem.c
@@ -168,39 +168,42 @@ REG32(INT_Q7_ENABLE, 0x618)
REG32(INT_Q1_DISABLE, 0x620)
REG32(INT_Q7_DISABLE, 0x638)
REG32(SCREENING_TYPE1_REG0, 0x500)
-
-#define GEM_ST1R_UDP_PORT_MATCH_ENABLE (1 << 29)
-#define GEM_ST1R_DSTC_ENABLE (1 << 28)
-#define GEM_ST1R_UDP_PORT_MATCH_SHIFT (12)
-#define GEM_ST1R_UDP_PORT_MATCH_WIDTH (27 - GEM_ST1R_UDP_PORT_MATCH_SHIFT + 1)
-#define GEM_ST1R_DSTC_MATCH_SHIFT (4)
-#define GEM_ST1R_DSTC_MATCH_WIDTH (11 - GEM_ST1R_DSTC_MATCH_SHIFT + 1)
-#define GEM_ST1R_QUEUE_SHIFT (0)
-#define GEM_ST1R_QUEUE_WIDTH (3 - GEM_ST1R_QUEUE_SHIFT + 1)
+ FIELD(SCREENING_TYPE1_REG0, QUEUE_NUM, 0, 4)
+ FIELD(SCREENING_TYPE1_REG0, DSTC_MATCH, 4, 8)
+ FIELD(SCREENING_TYPE1_REG0, UDP_PORT_MATCH, 12, 16)
+ FIELD(SCREENING_TYPE1_REG0, DSTC_ENABLE, 28, 1)
+ FIELD(SCREENING_TYPE1_REG0, UDP_PORT_MATCH_EN, 29, 1)
+ FIELD(SCREENING_TYPE1_REG0, DROP_ON_MATCH, 30, 1)
REG32(SCREENING_TYPE2_REG0, 0x540)
-
-#define GEM_ST2R_COMPARE_A_ENABLE (1 << 18)
-#define GEM_ST2R_COMPARE_A_SHIFT (13)
-#define GEM_ST2R_COMPARE_WIDTH (17 - GEM_ST2R_COMPARE_A_SHIFT + 1)
-#define GEM_ST2R_ETHERTYPE_ENABLE (1 << 12)
-#define GEM_ST2R_ETHERTYPE_INDEX_SHIFT (9)
-#define GEM_ST2R_ETHERTYPE_INDEX_WIDTH (11 - GEM_ST2R_ETHERTYPE_INDEX_SHIFT \
- + 1)
-#define GEM_ST2R_QUEUE_SHIFT (0)
-#define GEM_ST2R_QUEUE_WIDTH (3 - GEM_ST2R_QUEUE_SHIFT + 1)
+ FIELD(SCREENING_TYPE2_REG0, QUEUE_NUM, 0, 4)
+ FIELD(SCREENING_TYPE2_REG0, VLAN_PRIORITY, 4, 3)
+ FIELD(SCREENING_TYPE2_REG0, VLAN_ENABLE, 8, 1)
+ FIELD(SCREENING_TYPE2_REG0, ETHERTYPE_REG_INDEX, 9, 3)
+ FIELD(SCREENING_TYPE2_REG0, ETHERTYPE_ENABLE, 12, 1)
+ FIELD(SCREENING_TYPE2_REG0, COMPARE_A, 13, 5)
+ FIELD(SCREENING_TYPE2_REG0, COMPARE_A_ENABLE, 18, 1)
+ FIELD(SCREENING_TYPE2_REG0, COMPARE_B, 19, 5)
+ FIELD(SCREENING_TYPE2_REG0, COMPARE_B_ENABLE, 24, 1)
+ FIELD(SCREENING_TYPE2_REG0, COMPARE_C, 25, 5)
+ FIELD(SCREENING_TYPE2_REG0, COMPARE_C_ENABLE, 30, 1)
+ FIELD(SCREENING_TYPE2_REG0, DROP_ON_MATCH, 31, 1)
REG32(SCREENING_TYPE2_ETHERTYPE_REG0, 0x6e0)
+
REG32(TYPE2_COMPARE_0_WORD_0, 0x700)
+ FIELD(TYPE2_COMPARE_0_WORD_0, MASK_VALUE, 0, 16)
+ FIELD(TYPE2_COMPARE_0_WORD_0, COMPARE_VALUE, 16, 16)
-#define GEM_T2CW1_COMPARE_OFFSET_SHIFT (7)
-#define GEM_T2CW1_COMPARE_OFFSET_WIDTH (8 - GEM_T2CW1_COMPARE_OFFSET_SHIFT + 1)
-#define GEM_T2CW1_OFFSET_VALUE_SHIFT (0)
-#define GEM_T2CW1_OFFSET_VALUE_WIDTH (6 - GEM_T2CW1_OFFSET_VALUE_SHIFT + 1)
+REG32(TYPE2_COMPARE_0_WORD_1, 0x704)
+ FIELD(TYPE2_COMPARE_0_WORD_1, OFFSET_VALUE, 0, 7)
+ FIELD(TYPE2_COMPARE_0_WORD_1, COMPARE_OFFSET, 7, 2)
+ FIELD(TYPE2_COMPARE_0_WORD_1, DISABLE_MASK, 9, 1)
+ FIELD(TYPE2_COMPARE_0_WORD_1, COMPARE_VLAN_ID, 10, 1)
/*****************************************/
#define GEM_NWCTRL_TXSTART 0x00000200 /* Transmit Enable */
#define GEM_NWCTRL_TXENA 0x00000008 /* Transmit Enable */
#define GEM_NWCTRL_RXENA 0x00000004 /* Receive Enable */
@@ -753,45 +756,43 @@ static int get_queue_from_screen(CadenceGEMState *s, uint8_t *rxbuf_ptr,
reg = s->regs[R_SCREENING_TYPE1_REG0 + i];
matched = false;
mismatched = false;
/* Screening is based on UDP Port */
- if (reg & GEM_ST1R_UDP_PORT_MATCH_ENABLE) {
+ if (FIELD_EX32(reg, SCREENING_TYPE1_REG0, UDP_PORT_MATCH_EN)) {
uint16_t udp_port = rxbuf_ptr[14 + 22] << 8 | rxbuf_ptr[14 + 23];
- if (udp_port == extract32(reg, GEM_ST1R_UDP_PORT_MATCH_SHIFT,
- GEM_ST1R_UDP_PORT_MATCH_WIDTH)) {
+ if (udp_port == FIELD_EX32(reg, SCREENING_TYPE1_REG0, UDP_PORT_MATCH)) {
matched = true;
} else {
mismatched = true;
}
}
/* Screening is based on DS/TC */
- if (reg & GEM_ST1R_DSTC_ENABLE) {
+ if (FIELD_EX32(reg, SCREENING_TYPE1_REG0, DSTC_ENABLE)) {
uint8_t dscp = rxbuf_ptr[14 + 1];
- if (dscp == extract32(reg, GEM_ST1R_DSTC_MATCH_SHIFT,
- GEM_ST1R_DSTC_MATCH_WIDTH)) {
+ if (dscp == FIELD_EX32(reg, SCREENING_TYPE1_REG0, DSTC_MATCH)) {
matched = true;
} else {
mismatched = true;
}
}
if (matched && !mismatched) {
- return extract32(reg, GEM_ST1R_QUEUE_SHIFT, GEM_ST1R_QUEUE_WIDTH);
+ return FIELD_EX32(reg, SCREENING_TYPE1_REG0, QUEUE_NUM);
}
}
for (i = 0; i < s->num_type2_screeners; i++) {
reg = s->regs[R_SCREENING_TYPE2_REG0 + i];
matched = false;
mismatched = false;
- if (reg & GEM_ST2R_ETHERTYPE_ENABLE) {
+ if (FIELD_EX32(reg, SCREENING_TYPE2_REG0, ETHERTYPE_ENABLE)) {
uint16_t type = rxbuf_ptr[12] << 8 | rxbuf_ptr[13];
- int et_idx = extract32(reg, GEM_ST2R_ETHERTYPE_INDEX_SHIFT,
- GEM_ST2R_ETHERTYPE_INDEX_WIDTH);
+ int et_idx = FIELD_EX32(reg, SCREENING_TYPE2_REG0,
+ ETHERTYPE_REG_INDEX);
if (et_idx > s->num_type2_screeners) {
qemu_log_mask(LOG_GUEST_ERROR, "Out of range ethertype "
"register index: %d\n", et_idx);
}
@@ -803,31 +804,31 @@ static int get_queue_from_screen(CadenceGEMState *s, uint8_t *rxbuf_ptr,
}
}
/* Compare A, B, C */
for (j = 0; j < 3; j++) {
- uint32_t cr0, cr1, mask;
+ uint32_t cr0, cr1, mask, compare;
uint16_t rx_cmp;
int offset;
- int cr_idx = extract32(reg, GEM_ST2R_COMPARE_A_SHIFT + j * 6,
- GEM_ST2R_COMPARE_WIDTH);
+ int cr_idx = extract32(reg, R_SCREENING_TYPE2_REG0_COMPARE_A_SHIFT + j * 6,
+ R_SCREENING_TYPE2_REG0_COMPARE_A_LENGTH);
- if (!(reg & (GEM_ST2R_COMPARE_A_ENABLE << (j * 6)))) {
+ if (!extract32(reg, R_SCREENING_TYPE2_REG0_COMPARE_A_ENABLE_SHIFT + j * 6,
+ R_SCREENING_TYPE2_REG0_COMPARE_A_ENABLE_LENGTH)) {
continue;
}
+
if (cr_idx > s->num_type2_screeners) {
qemu_log_mask(LOG_GUEST_ERROR, "Out of range compare "
"register index: %d\n", cr_idx);
}
cr0 = s->regs[R_TYPE2_COMPARE_0_WORD_0 + cr_idx * 2];
- cr1 = s->regs[R_TYPE2_COMPARE_0_WORD_0 + cr_idx * 2 + 1];
- offset = extract32(cr1, GEM_T2CW1_OFFSET_VALUE_SHIFT,
- GEM_T2CW1_OFFSET_VALUE_WIDTH);
+ cr1 = s->regs[R_TYPE2_COMPARE_0_WORD_1 + cr_idx * 2];
+ offset = FIELD_EX32(cr1, TYPE2_COMPARE_0_WORD_1, OFFSET_VALUE);
- switch (extract32(cr1, GEM_T2CW1_COMPARE_OFFSET_SHIFT,
- GEM_T2CW1_COMPARE_OFFSET_WIDTH)) {
+ switch (FIELD_EX32(cr1, TYPE2_COMPARE_0_WORD_1, COMPARE_OFFSET)) {
case 3: /* Skip UDP header */
qemu_log_mask(LOG_UNIMP, "TCP compare offsets"
"unimplemented - assuming UDP\n");
offset += 8;
/* Fallthrough */
@@ -841,21 +842,22 @@ static int get_queue_from_screen(CadenceGEMState *s, uint8_t *rxbuf_ptr,
/* Offset from start of frame */
break;
}
rx_cmp = rxbuf_ptr[offset] << 8 | rxbuf_ptr[offset];
- mask = extract32(cr0, 0, 16);
+ mask = FIELD_EX32(cr0, TYPE2_COMPARE_0_WORD_0, MASK_VALUE);
+ compare = FIELD_EX32(cr0, TYPE2_COMPARE_0_WORD_0, COMPARE_VALUE);
- if ((rx_cmp & mask) == (extract32(cr0, 16, 16) & mask)) {
+ if ((rx_cmp & mask) == (compare & mask)) {
matched = true;
} else {
mismatched = true;
}
}
if (matched && !mismatched) {
- return extract32(reg, GEM_ST2R_QUEUE_SHIFT, GEM_ST2R_QUEUE_WIDTH);
+ return FIELD_EX32(reg, SCREENING_TYPE2_REG0, QUEUE_NUM);
}
}
/* We made it here, assume it's queue 0 */
return 0;
--
2.39.2
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH 03/11] hw/net/cadence_gem: use FIELD to describe NWCTRL register fields
2023-10-17 19:44 [PATCH 00/11] Various updates for the Cadence GEM model Luc Michel
2023-10-17 19:44 ` [PATCH 01/11] hw/net/cadence_gem: use REG32 macro for register definitions Luc Michel
2023-10-17 19:44 ` [PATCH 02/11] hw/net/cadence_gem: use FIELD for screening registers Luc Michel
@ 2023-10-17 19:44 ` Luc Michel
2023-10-18 10:15 ` Boddu, Sai Pavan
2023-10-17 19:44 ` [PATCH 04/11] hw/net/cadence_gem: use FIELD to describe NWCFG " Luc Michel
` (8 subsequent siblings)
11 siblings, 1 reply; 25+ messages in thread
From: Luc Michel @ 2023-10-17 19:44 UTC (permalink / raw)
To: qemu-devel
Cc: Luc Michel, qemu-arm, Edgar E . Iglesias, Alistair Francis,
Peter Maydell, Jason Wang, Philippe Mathieu-Daudé,
Francisco Iglesias, Frederic Konrad, Sai Pavan Boddu
Use the FIELD macro to describe the NWCTRL register fields.
Signed-off-by: Luc Michel <luc.michel@amd.com>
---
hw/net/cadence_gem.c | 53 +++++++++++++++++++++++++++++++++-----------
1 file changed, 40 insertions(+), 13 deletions(-)
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index f01c81de97..2864f0940e 100644
--- a/hw/net/cadence_gem.c
+++ b/hw/net/cadence_gem.c
@@ -44,10 +44,42 @@
qemu_log(__VA_ARGS__); \
} \
} while (0)
REG32(NWCTRL, 0x0) /* Network Control reg */
+ FIELD(NWCTRL, LOOPBACK , 0, 1)
+ FIELD(NWCTRL, LOOPBACK_LOCAL , 1, 1)
+ FIELD(NWCTRL, ENABLE_RECEIVE, 2, 1)
+ FIELD(NWCTRL, ENABLE_TRANSMIT, 3, 1)
+ FIELD(NWCTRL, MAN_PORT_EN , 4, 1)
+ FIELD(NWCTRL, CLEAR_ALL_STATS_REGS , 5, 1)
+ FIELD(NWCTRL, INC_ALL_STATS_REGS, 6, 1)
+ FIELD(NWCTRL, STATS_WRITE_EN, 7, 1)
+ FIELD(NWCTRL, BACK_PRESSURE, 8, 1)
+ FIELD(NWCTRL, TRANSMIT_START , 9, 1)
+ FIELD(NWCTRL, TRANSMIT_HALT, 10, 1)
+ FIELD(NWCTRL, TX_PAUSE_FRAME_RE, 11, 1)
+ FIELD(NWCTRL, TX_PAUSE_FRAME_ZE, 12, 1)
+ FIELD(NWCTRL, STATS_TAKE_SNAP, 13, 1)
+ FIELD(NWCTRL, STATS_READ_SNAP, 14, 1)
+ FIELD(NWCTRL, STORE_RX_TS, 15, 1)
+ FIELD(NWCTRL, PFC_ENABLE, 16, 1)
+ FIELD(NWCTRL, PFC_PRIO_BASED, 17, 1)
+ FIELD(NWCTRL, FLUSH_RX_PKT_PCLK , 18, 1)
+ FIELD(NWCTRL, TX_LPI_EN, 19, 1)
+ FIELD(NWCTRL, PTP_UNICAST_ENA, 20, 1)
+ FIELD(NWCTRL, ALT_SGMII_MODE, 21, 1)
+ FIELD(NWCTRL, STORE_UDP_OFFSET, 22, 1)
+ FIELD(NWCTRL, EXT_TSU_PORT_EN, 23, 1)
+ FIELD(NWCTRL, ONE_STEP_SYNC_MO, 24, 1)
+ FIELD(NWCTRL, PFC_CTRL , 25, 1)
+ FIELD(NWCTRL, EXT_RXQ_SEL_EN , 26, 1)
+ FIELD(NWCTRL, OSS_CORRECTION_FIELD, 27, 1)
+ FIELD(NWCTRL, SEL_MII_ON_RGMII, 28, 1)
+ FIELD(NWCTRL, TWO_PT_FIVE_GIG, 29, 1)
+ FIELD(NWCTRL, IFG_EATS_QAV_CREDIT, 30, 1)
+
REG32(NWCFG, 0x4) /* Network Config reg */
REG32(NWSTATUS, 0x8) /* Network Status reg */
REG32(USERIO, 0xc) /* User IO reg */
REG32(DMACFG, 0x10) /* DMA Control reg */
REG32(TXSTATUS, 0x14) /* TX Status reg */
@@ -202,15 +234,10 @@ REG32(TYPE2_COMPARE_0_WORD_1, 0x704)
FIELD(TYPE2_COMPARE_0_WORD_1, COMPARE_OFFSET, 7, 2)
FIELD(TYPE2_COMPARE_0_WORD_1, DISABLE_MASK, 9, 1)
FIELD(TYPE2_COMPARE_0_WORD_1, COMPARE_VLAN_ID, 10, 1)
/*****************************************/
-#define GEM_NWCTRL_TXSTART 0x00000200 /* Transmit Enable */
-#define GEM_NWCTRL_TXENA 0x00000008 /* Transmit Enable */
-#define GEM_NWCTRL_RXENA 0x00000004 /* Receive Enable */
-#define GEM_NWCTRL_LOCALLOOP 0x00000002 /* Local Loopback */
-
#define GEM_NWCFG_STRIP_FCS 0x00020000 /* Strip FCS field */
#define GEM_NWCFG_LERR_DISC 0x00010000 /* Discard RX frames with len err */
#define GEM_NWCFG_BUFF_OFST_M 0x0000C000 /* Receive buffer offset mask */
#define GEM_NWCFG_BUFF_OFST_S 14 /* Receive buffer offset shift */
#define GEM_NWCFG_RCV_1538 0x00000100 /* Receive 1538 bytes frame */
@@ -558,11 +585,11 @@ static bool gem_can_receive(NetClientState *nc)
int i;
s = qemu_get_nic_opaque(nc);
/* Do nothing if receive is not enabled. */
- if (!(s->regs[R_NWCTRL] & GEM_NWCTRL_RXENA)) {
+ if (!FIELD_EX32(s->regs[R_NWCTRL], NWCTRL, ENABLE_RECEIVE)) {
if (s->can_rx_state != 1) {
s->can_rx_state = 1;
DB_PRINT("can't receive - no enable\n");
}
return false;
@@ -1171,11 +1198,11 @@ static void gem_transmit(CadenceGEMState *s)
uint8_t *p;
unsigned total_bytes;
int q = 0;
/* Do nothing if transmit is not enabled. */
- if (!(s->regs[R_NWCTRL] & GEM_NWCTRL_TXENA)) {
+ if (!FIELD_EX32(s->regs[R_NWCTRL], NWCTRL, ENABLE_TRANSMIT)) {
return;
}
DB_PRINT("\n");
@@ -1196,11 +1223,11 @@ static void gem_transmit(CadenceGEMState *s)
sizeof(uint32_t) * gem_get_desc_len(s, false));
/* Handle all descriptors owned by hardware */
while (tx_desc_get_used(desc) == 0) {
/* Do nothing if transmit is not enabled. */
- if (!(s->regs[R_NWCTRL] & GEM_NWCTRL_TXENA)) {
+ if (!FIELD_EX32(s->regs[R_NWCTRL], NWCTRL, ENABLE_TRANSMIT)) {
return;
}
print_gem_tx_desc(desc, q);
/* The real hardware would eat this (and possibly crash).
@@ -1269,12 +1296,12 @@ static void gem_transmit(CadenceGEMState *s)
/* Update MAC statistics */
gem_transmit_updatestats(s, s->tx_packet, total_bytes);
/* Send the packet somewhere */
- if (s->phy_loop || (s->regs[R_NWCTRL] &
- GEM_NWCTRL_LOCALLOOP)) {
+ if (s->phy_loop || FIELD_EX32(s->regs[R_NWCTRL], NWCTRL,
+ LOOPBACK_LOCAL)) {
qemu_receive_packet(qemu_get_queue(s->nic), s->tx_packet,
total_bytes);
} else {
qemu_send_packet(qemu_get_queue(s->nic), s->tx_packet,
total_bytes);
@@ -1491,19 +1518,19 @@ static void gem_write(void *opaque, hwaddr offset, uint64_t val,
s->regs[offset] &= ~(s->regs_w1c[offset] & val);
/* Handle register write side effects */
switch (offset) {
case R_NWCTRL:
- if (val & GEM_NWCTRL_RXENA) {
+ if (FIELD_EX32(val, NWCTRL, ENABLE_RECEIVE)) {
for (i = 0; i < s->num_priority_queues; ++i) {
gem_get_rx_desc(s, i);
}
}
- if (val & GEM_NWCTRL_TXSTART) {
+ if (FIELD_EX32(val, NWCTRL, TRANSMIT_START)) {
gem_transmit(s);
}
- if (!(val & GEM_NWCTRL_TXENA)) {
+ if (!(FIELD_EX32(val, NWCTRL, ENABLE_TRANSMIT))) {
/* Reset to start of Q when transmit disabled. */
for (i = 0; i < s->num_priority_queues; i++) {
s->tx_desc_addr[i] = gem_get_tx_queue_base_addr(s, i);
}
}
--
2.39.2
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH 04/11] hw/net/cadence_gem: use FIELD to describe NWCFG register fields
2023-10-17 19:44 [PATCH 00/11] Various updates for the Cadence GEM model Luc Michel
` (2 preceding siblings ...)
2023-10-17 19:44 ` [PATCH 03/11] hw/net/cadence_gem: use FIELD to describe NWCTRL register fields Luc Michel
@ 2023-10-17 19:44 ` Luc Michel
2023-10-18 10:18 ` Boddu, Sai Pavan
2023-10-17 19:44 ` [PATCH 05/11] hw/net/cadence_gem: use FIELD to describe DMACFG " Luc Michel
` (7 subsequent siblings)
11 siblings, 1 reply; 25+ messages in thread
From: Luc Michel @ 2023-10-17 19:44 UTC (permalink / raw)
To: qemu-devel
Cc: Luc Michel, qemu-arm, Edgar E . Iglesias, Alistair Francis,
Peter Maydell, Jason Wang, Philippe Mathieu-Daudé,
Francisco Iglesias, Frederic Konrad, Sai Pavan Boddu
Use de FIELD macro to describe the NWCFG register fields.
Signed-off-by: Luc Michel <luc.michel@amd.com>
---
hw/net/cadence_gem.c | 60 ++++++++++++++++++++++++++++----------------
1 file changed, 39 insertions(+), 21 deletions(-)
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index 2864f0940e..09f570b6fb 100644
--- a/hw/net/cadence_gem.c
+++ b/hw/net/cadence_gem.c
@@ -77,10 +77,39 @@ REG32(NWCTRL, 0x0) /* Network Control reg */
FIELD(NWCTRL, SEL_MII_ON_RGMII, 28, 1)
FIELD(NWCTRL, TWO_PT_FIVE_GIG, 29, 1)
FIELD(NWCTRL, IFG_EATS_QAV_CREDIT, 30, 1)
REG32(NWCFG, 0x4) /* Network Config reg */
+ FIELD(NWCFG, SPEED, 0, 1)
+ FIELD(NWCFG, FULL_DUPLEX, 1, 1)
+ FIELD(NWCFG, DISCARD_NON_VLAN_FRAMES, 2, 1)
+ FIELD(NWCFG, JUMBO_FRAMES, 3, 1)
+ FIELD(NWCFG, PROMISC, 4, 1)
+ FIELD(NWCFG, NO_BROADCAST, 5, 1)
+ FIELD(NWCFG, MULTICAST_HASH_EN, 6, 1)
+ FIELD(NWCFG, UNICAST_HASH_EN, 7, 1)
+ FIELD(NWCFG, RECV_1536_BYTE_FRAMES, 8, 1)
+ FIELD(NWCFG, EXTERNAL_ADDR_MATCH_EN, 9, 1)
+ FIELD(NWCFG, GIGABIT_MODE_ENABLE, 10, 1)
+ FIELD(NWCFG, PCS_SELECT, 11, 1)
+ FIELD(NWCFG, RETRY_TEST, 12, 1)
+ FIELD(NWCFG, PAUSE_ENABLE, 13, 1)
+ FIELD(NWCFG, RECV_BUF_OFFSET, 14, 2)
+ FIELD(NWCFG, LEN_ERR_DISCARD, 16, 1)
+ FIELD(NWCFG, FCS_REMOVE, 17, 1)
+ FIELD(NWCFG, MDC_CLOCK_DIV, 18, 3)
+ FIELD(NWCFG, DATA_BUS_WIDTH, 21, 2)
+ FIELD(NWCFG, DISABLE_COPY_PAUSE_FRAMES, 23, 1)
+ FIELD(NWCFG, RECV_CSUM_OFFLOAD_EN, 24, 1)
+ FIELD(NWCFG, EN_HALF_DUPLEX_RX, 25, 1)
+ FIELD(NWCFG, IGNORE_RX_FCS, 26, 1)
+ FIELD(NWCFG, SGMII_MODE_ENABLE, 27, 1)
+ FIELD(NWCFG, IPG_STRETCH_ENABLE, 28, 1)
+ FIELD(NWCFG, NSP_ACCEPT, 29, 1)
+ FIELD(NWCFG, IGNORE_IPG_RX_ER, 30, 1)
+ FIELD(NWCFG, UNI_DIRECTION_ENABLE, 31, 1)
+
REG32(NWSTATUS, 0x8) /* Network Status reg */
REG32(USERIO, 0xc) /* User IO reg */
REG32(DMACFG, 0x10) /* DMA Control reg */
REG32(TXSTATUS, 0x14) /* TX Status reg */
REG32(RXQBASE, 0x18) /* RX Q Base address reg */
@@ -234,21 +263,10 @@ REG32(TYPE2_COMPARE_0_WORD_1, 0x704)
FIELD(TYPE2_COMPARE_0_WORD_1, COMPARE_OFFSET, 7, 2)
FIELD(TYPE2_COMPARE_0_WORD_1, DISABLE_MASK, 9, 1)
FIELD(TYPE2_COMPARE_0_WORD_1, COMPARE_VLAN_ID, 10, 1)
/*****************************************/
-#define GEM_NWCFG_STRIP_FCS 0x00020000 /* Strip FCS field */
-#define GEM_NWCFG_LERR_DISC 0x00010000 /* Discard RX frames with len err */
-#define GEM_NWCFG_BUFF_OFST_M 0x0000C000 /* Receive buffer offset mask */
-#define GEM_NWCFG_BUFF_OFST_S 14 /* Receive buffer offset shift */
-#define GEM_NWCFG_RCV_1538 0x00000100 /* Receive 1538 bytes frame */
-#define GEM_NWCFG_UCAST_HASH 0x00000080 /* accept unicast if hash match */
-#define GEM_NWCFG_MCAST_HASH 0x00000040 /* accept multicast if hash match */
-#define GEM_NWCFG_BCAST_REJ 0x00000020 /* Reject broadcast packets */
-#define GEM_NWCFG_PROMISC 0x00000010 /* Accept all packets */
-#define GEM_NWCFG_JUMBO_FRAME 0x00000008 /* Jumbo Frames enable */
-
#define GEM_DMACFG_ADDR_64B (1U << 30)
#define GEM_DMACFG_TX_BD_EXT (1U << 29)
#define GEM_DMACFG_RX_BD_EXT (1U << 28)
#define GEM_DMACFG_RBUFSZ_M 0x00FF0000 /* DMA RX Buffer Size mask */
#define GEM_DMACFG_RBUFSZ_S 16 /* DMA RX Buffer Size shift */
@@ -480,21 +498,22 @@ static inline void rx_desc_set_sar(uint32_t *desc, int sar_idx)
static const uint8_t broadcast_addr[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
static uint32_t gem_get_max_buf_len(CadenceGEMState *s, bool tx)
{
uint32_t size;
- if (s->regs[R_NWCFG] & GEM_NWCFG_JUMBO_FRAME) {
+ if (FIELD_EX32(s->regs[R_NWCFG], NWCFG, JUMBO_FRAMES)) {
size = s->regs[R_JUMBO_MAX_LEN];
if (size > s->jumbo_max_len) {
size = s->jumbo_max_len;
qemu_log_mask(LOG_GUEST_ERROR, "GEM_JUMBO_MAX_LEN reg cannot be"
" greater than 0x%" PRIx32 "\n", s->jumbo_max_len);
}
} else if (tx) {
size = 1518;
} else {
- size = s->regs[R_NWCFG] & GEM_NWCFG_RCV_1538 ? 1538 : 1518;
+ size = FIELD_EX32(s->regs[R_NWCFG],
+ NWCFG, RECV_1536_BYTE_FRAMES) ? 1538 : 1518;
}
return size;
}
static void gem_set_isr(CadenceGEMState *s, int q, uint32_t flag)
@@ -730,26 +749,26 @@ static int gem_mac_address_filter(CadenceGEMState *s, const uint8_t *packet)
{
uint8_t *gem_spaddr;
int i, is_mc;
/* Promiscuous mode? */
- if (s->regs[R_NWCFG] & GEM_NWCFG_PROMISC) {
+ if (FIELD_EX32(s->regs[R_NWCFG], NWCFG, PROMISC)) {
return GEM_RX_PROMISCUOUS_ACCEPT;
}
if (!memcmp(packet, broadcast_addr, 6)) {
/* Reject broadcast packets? */
- if (s->regs[R_NWCFG] & GEM_NWCFG_BCAST_REJ) {
+ if (FIELD_EX32(s->regs[R_NWCFG], NWCFG, NO_BROADCAST)) {
return GEM_RX_REJECT;
}
return GEM_RX_BROADCAST_ACCEPT;
}
/* Accept packets -w- hash match? */
is_mc = is_multicast_ether_addr(packet);
- if ((is_mc && (s->regs[R_NWCFG] & GEM_NWCFG_MCAST_HASH)) ||
- (!is_mc && (s->regs[R_NWCFG] & GEM_NWCFG_UCAST_HASH))) {
+ if ((is_mc && (FIELD_EX32(s->regs[R_NWCFG], NWCFG, MULTICAST_HASH_EN))) ||
+ (!is_mc && FIELD_EX32(s->regs[R_NWCFG], NWCFG, UNICAST_HASH_EN))) {
uint64_t buckets;
unsigned hash_index;
hash_index = calc_mac_hash(packet);
buckets = ((uint64_t)s->regs[R_HASHHI] << 32) | s->regs[R_HASHLO];
@@ -981,11 +1000,11 @@ static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size)
if (maf == GEM_RX_REJECT) {
return size; /* no, drop silently b/c it's not an error */
}
/* Discard packets with receive length error enabled ? */
- if (s->regs[R_NWCFG] & GEM_NWCFG_LERR_DISC) {
+ if (FIELD_EX32(s->regs[R_NWCFG], NWCFG, LEN_ERR_DISCARD)) {
unsigned type_len;
/* Fish the ethertype / length field out of the RX packet */
type_len = buf[12] << 8 | buf[13];
/* It is a length field, not an ethertype */
@@ -998,12 +1017,11 @@ static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size)
}
/*
* Determine configured receive buffer offset (probably 0)
*/
- rxbuf_offset = (s->regs[R_NWCFG] & GEM_NWCFG_BUFF_OFST_M) >>
- GEM_NWCFG_BUFF_OFST_S;
+ rxbuf_offset = FIELD_EX32(s->regs[R_NWCFG], NWCFG, RECV_BUF_OFFSET);
/* The configure size of each receive buffer. Determines how many
* buffers needed to hold this packet.
*/
rxbufsize = ((s->regs[R_DMACFG] & GEM_DMACFG_RBUFSZ_M) >>
@@ -1024,11 +1042,11 @@ static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size)
if (size < 60) {
size = 60;
}
/* Strip of FCS field ? (usually yes) */
- if (s->regs[R_NWCFG] & GEM_NWCFG_STRIP_FCS) {
+ if (FIELD_EX32(s->regs[R_NWCFG], NWCFG, FCS_REMOVE)) {
rxbuf_ptr = (void *)buf;
} else {
unsigned crc_val;
if (size > MAX_FRAME_SIZE - sizeof(crc_val)) {
--
2.39.2
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH 05/11] hw/net/cadence_gem: use FIELD to describe DMACFG register fields
2023-10-17 19:44 [PATCH 00/11] Various updates for the Cadence GEM model Luc Michel
` (3 preceding siblings ...)
2023-10-17 19:44 ` [PATCH 04/11] hw/net/cadence_gem: use FIELD to describe NWCFG " Luc Michel
@ 2023-10-17 19:44 ` Luc Michel
2023-10-18 10:20 ` Boddu, Sai Pavan
2023-10-17 19:44 ` [PATCH 06/11] hw/net/cadence_gem: use FIELD to describe [TX|RX]STATUS " Luc Michel
` (6 subsequent siblings)
11 siblings, 1 reply; 25+ messages in thread
From: Luc Michel @ 2023-10-17 19:44 UTC (permalink / raw)
To: qemu-devel
Cc: Luc Michel, qemu-arm, Edgar E . Iglesias, Alistair Francis,
Peter Maydell, Jason Wang, Philippe Mathieu-Daudé,
Francisco Iglesias, Frederic Konrad, Sai Pavan Boddu
Use de FIELD macro to describe the DMACFG register fields.
Signed-off-by: Luc Michel <luc.michel@amd.com>
---
hw/net/cadence_gem.c | 48 ++++++++++++++++++++++++++++----------------
1 file changed, 31 insertions(+), 17 deletions(-)
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index 09f570b6fb..5c386adff2 100644
--- a/hw/net/cadence_gem.c
+++ b/hw/net/cadence_gem.c
@@ -108,11 +108,31 @@ REG32(NWCFG, 0x4) /* Network Config reg */
FIELD(NWCFG, IGNORE_IPG_RX_ER, 30, 1)
FIELD(NWCFG, UNI_DIRECTION_ENABLE, 31, 1)
REG32(NWSTATUS, 0x8) /* Network Status reg */
REG32(USERIO, 0xc) /* User IO reg */
+
REG32(DMACFG, 0x10) /* DMA Control reg */
+ FIELD(DMACFG, SEND_BCAST_TO_ALL_QS, 31, 1)
+ FIELD(DMACFG, DMA_ADDR_BUS_WIDTH, 30, 1)
+ FIELD(DMACFG, TX_BD_EXT_MODE_EN , 29, 1)
+ FIELD(DMACFG, RX_BD_EXT_MODE_EN , 28, 1)
+ FIELD(DMACFG, FORCE_MAX_AMBA_BURST_TX, 26, 1)
+ FIELD(DMACFG, FORCE_MAX_AMBA_BURST_RX, 25, 1)
+ FIELD(DMACFG, FORCE_DISCARD_ON_ERR, 24, 1)
+ FIELD(DMACFG, RX_BUF_SIZE, 16, 8)
+ FIELD(DMACFG, CRC_ERROR_REPORT, 13, 1)
+ FIELD(DMACFG, INF_LAST_DBUF_SIZE_EN, 12, 1)
+ FIELD(DMACFG, TX_PBUF_CSUM_OFFLOAD, 11, 1)
+ FIELD(DMACFG, TX_PBUF_SIZE, 10, 1)
+ FIELD(DMACFG, RX_PBUF_SIZE, 8, 2)
+ FIELD(DMACFG, ENDIAN_SWAP_PACKET, 7, 1)
+ FIELD(DMACFG, ENDIAN_SWAP_MGNT, 6, 1)
+ FIELD(DMACFG, HDR_DATA_SPLIT_EN, 5, 1)
+ FIELD(DMACFG, AMBA_BURST_LEN , 0, 5)
+#define GEM_DMACFG_RBUFSZ_MUL 64 /* DMA RX Buffer Size multiplier */
+
REG32(TXSTATUS, 0x14) /* TX Status reg */
REG32(RXQBASE, 0x18) /* RX Q Base address reg */
REG32(TXQBASE, 0x1c) /* TX Q Base address reg */
REG32(RXSTATUS, 0x20) /* RX Status reg */
REG32(ISR, 0x24) /* Interrupt Status reg */
@@ -263,17 +283,10 @@ REG32(TYPE2_COMPARE_0_WORD_1, 0x704)
FIELD(TYPE2_COMPARE_0_WORD_1, COMPARE_OFFSET, 7, 2)
FIELD(TYPE2_COMPARE_0_WORD_1, DISABLE_MASK, 9, 1)
FIELD(TYPE2_COMPARE_0_WORD_1, COMPARE_VLAN_ID, 10, 1)
/*****************************************/
-#define GEM_DMACFG_ADDR_64B (1U << 30)
-#define GEM_DMACFG_TX_BD_EXT (1U << 29)
-#define GEM_DMACFG_RX_BD_EXT (1U << 28)
-#define GEM_DMACFG_RBUFSZ_M 0x00FF0000 /* DMA RX Buffer Size mask */
-#define GEM_DMACFG_RBUFSZ_S 16 /* DMA RX Buffer Size shift */
-#define GEM_DMACFG_RBUFSZ_MUL 64 /* DMA RX Buffer Size multiplier */
-#define GEM_DMACFG_TXCSUM_OFFL 0x00000800 /* Transmit checksum offload */
#define GEM_TXSTATUS_TXCMPL 0x00000020 /* Transmit Complete */
#define GEM_TXSTATUS_USED 0x00000001 /* sw owned descriptor encountered */
#define GEM_RXSTATUS_FRMRCVD 0x00000002 /* Frame received */
@@ -367,11 +380,11 @@ REG32(TYPE2_COMPARE_0_WORD_1, 0x704)
static inline uint64_t tx_desc_get_buffer(CadenceGEMState *s, uint32_t *desc)
{
uint64_t ret = desc[0];
- if (s->regs[R_DMACFG] & GEM_DMACFG_ADDR_64B) {
+ if (FIELD_EX32(s->regs[R_DMACFG], DMACFG, DMA_ADDR_BUS_WIDTH)) {
ret |= (uint64_t)desc[2] << 32;
}
return ret;
}
@@ -412,25 +425,25 @@ static inline void print_gem_tx_desc(uint32_t *desc, uint8_t queue)
static inline uint64_t rx_desc_get_buffer(CadenceGEMState *s, uint32_t *desc)
{
uint64_t ret = desc[0] & ~0x3UL;
- if (s->regs[R_DMACFG] & GEM_DMACFG_ADDR_64B) {
+ if (FIELD_EX32(s->regs[R_DMACFG], DMACFG, DMA_ADDR_BUS_WIDTH)) {
ret |= (uint64_t)desc[2] << 32;
}
return ret;
}
static inline int gem_get_desc_len(CadenceGEMState *s, bool rx_n_tx)
{
int ret = 2;
- if (s->regs[R_DMACFG] & GEM_DMACFG_ADDR_64B) {
+ if (FIELD_EX32(s->regs[R_DMACFG], DMACFG, DMA_ADDR_BUS_WIDTH)) {
ret += 2;
}
- if (s->regs[R_DMACFG] & (rx_n_tx ? GEM_DMACFG_RX_BD_EXT
- : GEM_DMACFG_TX_BD_EXT)) {
+ if (s->regs[R_DMACFG] & (rx_n_tx ? R_DMACFG_RX_BD_EXT_MODE_EN_MASK
+ : R_DMACFG_TX_BD_EXT_MODE_EN_MASK)) {
ret += 2;
}
assert(ret <= DESC_MAX_NUM_WORDS);
return ret;
@@ -940,11 +953,11 @@ static inline uint32_t gem_get_rx_queue_base_addr(CadenceGEMState *s, int q)
static hwaddr gem_get_desc_addr(CadenceGEMState *s, bool tx, int q)
{
hwaddr desc_addr = 0;
- if (s->regs[R_DMACFG] & GEM_DMACFG_ADDR_64B) {
+ if (FIELD_EX32(s->regs[R_DMACFG], DMACFG, DMA_ADDR_BUS_WIDTH)) {
desc_addr = s->regs[tx ? R_TBQPH : R_RBQPH];
}
desc_addr <<= 32;
desc_addr |= tx ? s->tx_desc_addr[q] : s->rx_desc_addr[q];
return desc_addr;
@@ -1022,12 +1035,13 @@ static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size)
rxbuf_offset = FIELD_EX32(s->regs[R_NWCFG], NWCFG, RECV_BUF_OFFSET);
/* The configure size of each receive buffer. Determines how many
* buffers needed to hold this packet.
*/
- rxbufsize = ((s->regs[R_DMACFG] & GEM_DMACFG_RBUFSZ_M) >>
- GEM_DMACFG_RBUFSZ_S) * GEM_DMACFG_RBUFSZ_MUL;
+ rxbufsize = FIELD_EX32(s->regs[R_DMACFG], DMACFG, RX_BUF_SIZE);
+ rxbufsize *= GEM_DMACFG_RBUFSZ_MUL;
+
bytes_to_copy = size;
/* Hardware allows a zero value here but warns against it. To avoid QEMU
* indefinite loops we enforce a minimum value here
*/
@@ -1306,11 +1320,11 @@ static void gem_transmit(CadenceGEMState *s)
/* Handle interrupt consequences */
gem_update_int_status(s);
/* Is checksum offload enabled? */
- if (s->regs[R_DMACFG] & GEM_DMACFG_TXCSUM_OFFL) {
+ if (FIELD_EX32(s->regs[R_DMACFG], DMACFG, TX_PBUF_CSUM_OFFLOAD)) {
net_checksum_calculate(s->tx_packet, total_bytes, CSUM_ALL);
}
/* Update MAC statistics */
gem_transmit_updatestats(s, s->tx_packet, total_bytes);
@@ -1330,11 +1344,11 @@ static void gem_transmit(CadenceGEMState *s)
total_bytes = 0;
}
/* read next descriptor */
if (tx_desc_get_wrap(desc)) {
- if (s->regs[R_DMACFG] & GEM_DMACFG_ADDR_64B) {
+ if (FIELD_EX32(s->regs[R_DMACFG], DMACFG, DMA_ADDR_BUS_WIDTH)) {
packet_desc_addr = s->regs[R_TBQPH];
packet_desc_addr <<= 32;
} else {
packet_desc_addr = 0;
}
--
2.39.2
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH 06/11] hw/net/cadence_gem: use FIELD to describe [TX|RX]STATUS register fields
2023-10-17 19:44 [PATCH 00/11] Various updates for the Cadence GEM model Luc Michel
` (4 preceding siblings ...)
2023-10-17 19:44 ` [PATCH 05/11] hw/net/cadence_gem: use FIELD to describe DMACFG " Luc Michel
@ 2023-10-17 19:44 ` Luc Michel
2023-10-18 10:21 ` Boddu, Sai Pavan
2023-10-17 19:44 ` [PATCH 07/11] hw/net/cadence_gem: use FIELD to describe IRQ " Luc Michel
` (5 subsequent siblings)
11 siblings, 1 reply; 25+ messages in thread
From: Luc Michel @ 2023-10-17 19:44 UTC (permalink / raw)
To: qemu-devel
Cc: Luc Michel, qemu-arm, Edgar E . Iglesias, Alistair Francis,
Peter Maydell, Jason Wang, Philippe Mathieu-Daudé,
Francisco Iglesias, Frederic Konrad, Sai Pavan Boddu
Use de FIELD macro to describe the TXSTATUS and RXSTATUS register
fields.
Signed-off-by: Luc Michel <luc.michel@amd.com>
---
hw/net/cadence_gem.c | 34 +++++++++++++++++++++++++---------
1 file changed, 25 insertions(+), 9 deletions(-)
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index 5c386adff2..0acee1d544 100644
--- a/hw/net/cadence_gem.c
+++ b/hw/net/cadence_gem.c
@@ -130,13 +130,34 @@ REG32(DMACFG, 0x10) /* DMA Control reg */
FIELD(DMACFG, HDR_DATA_SPLIT_EN, 5, 1)
FIELD(DMACFG, AMBA_BURST_LEN , 0, 5)
#define GEM_DMACFG_RBUFSZ_MUL 64 /* DMA RX Buffer Size multiplier */
REG32(TXSTATUS, 0x14) /* TX Status reg */
+ FIELD(TXSTATUS, TX_USED_BIT_READ_MIDFRAME, 12, 1)
+ FIELD(TXSTATUS, TX_FRAME_TOO_LARGE, 11, 1)
+ FIELD(TXSTATUS, TX_DMA_LOCKUP, 10, 1)
+ FIELD(TXSTATUS, TX_MAC_LOCKUP, 9, 1)
+ FIELD(TXSTATUS, RESP_NOT_OK, 8, 1)
+ FIELD(TXSTATUS, LATE_COLLISION, 7, 1)
+ FIELD(TXSTATUS, TRANSMIT_UNDER_RUN, 6, 1)
+ FIELD(TXSTATUS, TRANSMIT_COMPLETE, 5, 1)
+ FIELD(TXSTATUS, AMBA_ERROR, 4, 1)
+ FIELD(TXSTATUS, TRANSMIT_GO, 3, 1)
+ FIELD(TXSTATUS, RETRY_LIMIT, 2, 1)
+ FIELD(TXSTATUS, COLLISION, 1, 1)
+ FIELD(TXSTATUS, USED_BIT_READ, 0, 1)
+
REG32(RXQBASE, 0x18) /* RX Q Base address reg */
REG32(TXQBASE, 0x1c) /* TX Q Base address reg */
REG32(RXSTATUS, 0x20) /* RX Status reg */
+ FIELD(RXSTATUS, RX_DMA_LOCKUP, 5, 1)
+ FIELD(RXSTATUS, RX_MAC_LOCKUP, 4, 1)
+ FIELD(RXSTATUS, RESP_NOT_OK, 3, 1)
+ FIELD(RXSTATUS, RECEIVE_OVERRUN, 2, 1)
+ FIELD(RXSTATUS, FRAME_RECEIVED, 1, 1)
+ FIELD(RXSTATUS, BUF_NOT_AVAILABLE, 0, 1)
+
REG32(ISR, 0x24) /* Interrupt Status reg */
REG32(IER, 0x28) /* Interrupt Enable reg */
REG32(IDR, 0x2c) /* Interrupt Disable reg */
REG32(IMR, 0x30) /* Interrupt Mask reg */
REG32(PHYMNTNC, 0x34) /* Phy Maintenance reg */
@@ -284,15 +305,10 @@ REG32(TYPE2_COMPARE_0_WORD_1, 0x704)
FIELD(TYPE2_COMPARE_0_WORD_1, DISABLE_MASK, 9, 1)
FIELD(TYPE2_COMPARE_0_WORD_1, COMPARE_VLAN_ID, 10, 1)
/*****************************************/
-#define GEM_TXSTATUS_TXCMPL 0x00000020 /* Transmit Complete */
-#define GEM_TXSTATUS_USED 0x00000001 /* sw owned descriptor encountered */
-
-#define GEM_RXSTATUS_FRMRCVD 0x00000002 /* Frame received */
-#define GEM_RXSTATUS_NOBUF 0x00000001 /* Buffer unavailable */
/* GEM_ISR GEM_IER GEM_IDR GEM_IMR */
#define GEM_INT_TXCMPL 0x00000080 /* Transmit Complete */
#define GEM_INT_AMBA_ERR 0x00000040
#define GEM_INT_TXUSED 0x00000008
@@ -985,11 +1001,11 @@ static void gem_get_rx_desc(CadenceGEMState *s, int q)
sizeof(uint32_t) * gem_get_desc_len(s, true));
/* Descriptor owned by software ? */
if (rx_desc_get_ownership(s->rx_desc[q]) == 1) {
DB_PRINT("descriptor 0x%" HWADDR_PRIx " owned by sw.\n", desc_addr);
- s->regs[R_RXSTATUS] |= GEM_RXSTATUS_NOBUF;
+ s->regs[R_RXSTATUS] |= R_RXSTATUS_BUF_NOT_AVAILABLE_MASK;
gem_set_isr(s, q, GEM_INT_RXUSED);
/* Handle interrupt consequences */
gem_update_int_status(s);
}
}
@@ -1162,11 +1178,11 @@ static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size)
}
/* Count it */
gem_receive_updatestats(s, buf, size);
- s->regs[R_RXSTATUS] |= GEM_RXSTATUS_FRMRCVD;
+ s->regs[R_RXSTATUS] |= R_RXSTATUS_FRAME_RECEIVED_MASK;
gem_set_isr(s, q, GEM_INT_RXCMPL);
/* Handle interrupt consequences */
gem_update_int_status(s);
@@ -1313,11 +1329,11 @@ static void gem_transmit(CadenceGEMState *s)
s->tx_desc_addr[q] = packet_desc_addr +
4 * gem_get_desc_len(s, false);
}
DB_PRINT("TX descriptor next: 0x%08x\n", s->tx_desc_addr[q]);
- s->regs[R_TXSTATUS] |= GEM_TXSTATUS_TXCMPL;
+ s->regs[R_TXSTATUS] |= R_TXSTATUS_TRANSMIT_COMPLETE_MASK;
gem_set_isr(s, q, GEM_INT_TXCMPL);
/* Handle interrupt consequences */
gem_update_int_status(s);
@@ -1361,11 +1377,11 @@ static void gem_transmit(CadenceGEMState *s)
MEMTXATTRS_UNSPECIFIED, desc,
sizeof(uint32_t) * gem_get_desc_len(s, false));
}
if (tx_desc_get_used(desc)) {
- s->regs[R_TXSTATUS] |= GEM_TXSTATUS_USED;
+ s->regs[R_TXSTATUS] |= R_TXSTATUS_USED_BIT_READ_MASK;
/* IRQ TXUSED is defined only for queue 0 */
if (q == 0) {
gem_set_isr(s, 0, GEM_INT_TXUSED);
}
gem_update_int_status(s);
--
2.39.2
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH 07/11] hw/net/cadence_gem: use FIELD to describe IRQ register fields
2023-10-17 19:44 [PATCH 00/11] Various updates for the Cadence GEM model Luc Michel
` (5 preceding siblings ...)
2023-10-17 19:44 ` [PATCH 06/11] hw/net/cadence_gem: use FIELD to describe [TX|RX]STATUS " Luc Michel
@ 2023-10-17 19:44 ` Luc Michel
2023-10-18 10:22 ` Boddu, Sai Pavan
2023-10-17 19:44 ` [PATCH 08/11] hw/net/cadence_gem: use FIELD to describe DESCONF6 " Luc Michel
` (4 subsequent siblings)
11 siblings, 1 reply; 25+ messages in thread
From: Luc Michel @ 2023-10-17 19:44 UTC (permalink / raw)
To: qemu-devel
Cc: Luc Michel, qemu-arm, Edgar E . Iglesias, Alistair Francis,
Peter Maydell, Jason Wang, Philippe Mathieu-Daudé,
Francisco Iglesias, Frederic Konrad, Sai Pavan Boddu
Use de FIELD macro to describe the IRQ related register fields.
Signed-off-by: Luc Michel <luc.michel@amd.com>
---
hw/net/cadence_gem.c | 51 +++++++++++++++++++++++++++++++++-----------
1 file changed, 39 insertions(+), 12 deletions(-)
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index 0acee1d544..6d084a3b31 100644
--- a/hw/net/cadence_gem.c
+++ b/hw/net/cadence_gem.c
@@ -155,13 +155,46 @@ REG32(RXSTATUS, 0x20) /* RX Status reg */
FIELD(RXSTATUS, RECEIVE_OVERRUN, 2, 1)
FIELD(RXSTATUS, FRAME_RECEIVED, 1, 1)
FIELD(RXSTATUS, BUF_NOT_AVAILABLE, 0, 1)
REG32(ISR, 0x24) /* Interrupt Status reg */
+ FIELD(ISR, TX_LOCKUP, 31, 1)
+ FIELD(ISR, RX_LOCKUP, 30, 1)
+ FIELD(ISR, TSU_TIMER, 29, 1)
+ FIELD(ISR, WOL, 28, 1)
+ FIELD(ISR, RECV_LPI, 27, 1)
+ FIELD(ISR, TSU_SEC_INCR, 26, 1)
+ FIELD(ISR, PTP_PDELAY_RESP_XMIT, 25, 1)
+ FIELD(ISR, PTP_PDELAY_REQ_XMIT, 24, 1)
+ FIELD(ISR, PTP_PDELAY_RESP_RECV, 23, 1)
+ FIELD(ISR, PTP_PDELAY_REQ_RECV, 22, 1)
+ FIELD(ISR, PTP_SYNC_XMIT, 21, 1)
+ FIELD(ISR, PTP_DELAY_REQ_XMIT, 20, 1)
+ FIELD(ISR, PTP_SYNC_RECV, 19, 1)
+ FIELD(ISR, PTP_DELAY_REQ_RECV, 18, 1)
+ FIELD(ISR, PCS_LP_PAGE_RECV, 17, 1)
+ FIELD(ISR, PCS_AN_COMPLETE, 16, 1)
+ FIELD(ISR, EXT_IRQ, 15, 1)
+ FIELD(ISR, PAUSE_FRAME_XMIT, 14, 1)
+ FIELD(ISR, PAUSE_TIME_ELAPSED, 13, 1)
+ FIELD(ISR, PAUSE_FRAME_RECV, 12, 1)
+ FIELD(ISR, RESP_NOT_OK, 11, 1)
+ FIELD(ISR, RECV_OVERRUN, 10, 1)
+ FIELD(ISR, LINK_CHANGE, 9, 1)
+ FIELD(ISR, USXGMII_INT, 8, 1)
+ FIELD(ISR, XMIT_COMPLETE, 7, 1)
+ FIELD(ISR, AMBA_ERROR, 6, 1)
+ FIELD(ISR, RETRY_EXCEEDED, 5, 1)
+ FIELD(ISR, XMIT_UNDER_RUN, 4, 1)
+ FIELD(ISR, TX_USED, 3, 1)
+ FIELD(ISR, RX_USED, 2, 1)
+ FIELD(ISR, RECV_COMPLETE, 1, 1)
+ FIELD(ISR, MGNT_FRAME_SENT, 0, 1)
REG32(IER, 0x28) /* Interrupt Enable reg */
REG32(IDR, 0x2c) /* Interrupt Disable reg */
REG32(IMR, 0x30) /* Interrupt Mask reg */
+
REG32(PHYMNTNC, 0x34) /* Phy Maintenance reg */
REG32(RXPAUSE, 0x38) /* RX Pause Time reg */
REG32(TXPAUSE, 0x3c) /* TX Pause Time reg */
REG32(TXPARTIALSF, 0x40) /* TX Partial Store and Forward */
REG32(RXPARTIALSF, 0x44) /* RX Partial Store and Forward */
@@ -306,16 +339,10 @@ REG32(TYPE2_COMPARE_0_WORD_1, 0x704)
FIELD(TYPE2_COMPARE_0_WORD_1, COMPARE_VLAN_ID, 10, 1)
/*****************************************/
-/* GEM_ISR GEM_IER GEM_IDR GEM_IMR */
-#define GEM_INT_TXCMPL 0x00000080 /* Transmit Complete */
-#define GEM_INT_AMBA_ERR 0x00000040
-#define GEM_INT_TXUSED 0x00000008
-#define GEM_INT_RXUSED 0x00000004
-#define GEM_INT_RXCMPL 0x00000002
#define GEM_PHYMNTNC_OP_R 0x20000000 /* read operation */
#define GEM_PHYMNTNC_OP_W 0x10000000 /* write operation */
#define GEM_PHYMNTNC_ADDR 0x0F800000 /* Address bits */
#define GEM_PHYMNTNC_ADDR_SHFT 23
@@ -1002,11 +1029,11 @@ static void gem_get_rx_desc(CadenceGEMState *s, int q)
/* Descriptor owned by software ? */
if (rx_desc_get_ownership(s->rx_desc[q]) == 1) {
DB_PRINT("descriptor 0x%" HWADDR_PRIx " owned by sw.\n", desc_addr);
s->regs[R_RXSTATUS] |= R_RXSTATUS_BUF_NOT_AVAILABLE_MASK;
- gem_set_isr(s, q, GEM_INT_RXUSED);
+ gem_set_isr(s, q, R_ISR_RX_USED_MASK);
/* Handle interrupt consequences */
gem_update_int_status(s);
}
}
@@ -1102,11 +1129,11 @@ static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size)
/* Find which queue we are targeting */
q = get_queue_from_screen(s, rxbuf_ptr, rxbufsize);
if (size > gem_get_max_buf_len(s, false)) {
qemu_log_mask(LOG_GUEST_ERROR, "rx frame too long\n");
- gem_set_isr(s, q, GEM_INT_AMBA_ERR);
+ gem_set_isr(s, q, R_ISR_AMBA_ERROR_MASK);
return -1;
}
while (bytes_to_copy) {
hwaddr desc_addr;
@@ -1179,11 +1206,11 @@ static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size)
/* Count it */
gem_receive_updatestats(s, buf, size);
s->regs[R_RXSTATUS] |= R_RXSTATUS_FRAME_RECEIVED_MASK;
- gem_set_isr(s, q, GEM_INT_RXCMPL);
+ gem_set_isr(s, q, R_ISR_RECV_COMPLETE_MASK);
/* Handle interrupt consequences */
gem_update_int_status(s);
return size;
@@ -1292,11 +1319,11 @@ static void gem_transmit(CadenceGEMState *s)
(p - s->tx_packet)) {
qemu_log_mask(LOG_GUEST_ERROR, "TX descriptor @ 0x%" \
HWADDR_PRIx " too large: size 0x%x space 0x%zx\n",
packet_desc_addr, tx_desc_get_length(desc),
gem_get_max_buf_len(s, true) - (p - s->tx_packet));
- gem_set_isr(s, q, GEM_INT_AMBA_ERR);
+ gem_set_isr(s, q, R_ISR_AMBA_ERROR_MASK);
break;
}
/* Gather this fragment of the packet from "dma memory" to our
* contig buffer.
@@ -1330,11 +1357,11 @@ static void gem_transmit(CadenceGEMState *s)
4 * gem_get_desc_len(s, false);
}
DB_PRINT("TX descriptor next: 0x%08x\n", s->tx_desc_addr[q]);
s->regs[R_TXSTATUS] |= R_TXSTATUS_TRANSMIT_COMPLETE_MASK;
- gem_set_isr(s, q, GEM_INT_TXCMPL);
+ gem_set_isr(s, q, R_ISR_XMIT_COMPLETE_MASK);
/* Handle interrupt consequences */
gem_update_int_status(s);
/* Is checksum offload enabled? */
@@ -1380,11 +1407,11 @@ static void gem_transmit(CadenceGEMState *s)
if (tx_desc_get_used(desc)) {
s->regs[R_TXSTATUS] |= R_TXSTATUS_USED_BIT_READ_MASK;
/* IRQ TXUSED is defined only for queue 0 */
if (q == 0) {
- gem_set_isr(s, 0, GEM_INT_TXUSED);
+ gem_set_isr(s, 0, R_ISR_TX_USED_MASK);
}
gem_update_int_status(s);
}
}
}
--
2.39.2
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH 08/11] hw/net/cadence_gem: use FIELD to describe DESCONF6 register fields
2023-10-17 19:44 [PATCH 00/11] Various updates for the Cadence GEM model Luc Michel
` (6 preceding siblings ...)
2023-10-17 19:44 ` [PATCH 07/11] hw/net/cadence_gem: use FIELD to describe IRQ " Luc Michel
@ 2023-10-17 19:44 ` Luc Michel
2023-10-18 9:22 ` Philippe Mathieu-Daudé
2023-10-17 19:44 ` [PATCH 09/11] hw/net/cadence_gem: use FIELD to describe PHYMNTNC " Luc Michel
` (3 subsequent siblings)
11 siblings, 1 reply; 25+ messages in thread
From: Luc Michel @ 2023-10-17 19:44 UTC (permalink / raw)
To: qemu-devel
Cc: Luc Michel, qemu-arm, Edgar E . Iglesias, Alistair Francis,
Peter Maydell, Jason Wang, Philippe Mathieu-Daudé,
Francisco Iglesias, Frederic Konrad, Sai Pavan Boddu
Use the FIELD macro to describe the DESCONF6 register fields.
Signed-off-by: Luc Michel <luc.michel@amd.com>
---
hw/net/cadence_gem.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index 6d084a3b31..955a8da134 100644
--- a/hw/net/cadence_gem.c
+++ b/hw/net/cadence_gem.c
@@ -281,11 +281,11 @@ REG32(DESCONF, 0x280)
REG32(DESCONF2, 0x284)
REG32(DESCONF3, 0x288)
REG32(DESCONF4, 0x28c)
REG32(DESCONF5, 0x290)
REG32(DESCONF6, 0x294)
-#define GEM_DESCONF6_64B_MASK (1U << 23)
+ FIELD(DESCONF6, DMA_ADDR_64B, 23, 1)
REG32(DESCONF7, 0x298)
REG32(INT_Q1_STATUS, 0x400)
REG32(INT_Q1_MASK, 0x640)
@@ -1461,11 +1461,11 @@ static void gem_reset(DeviceState *d)
s->regs[R_RXPARTIALSF] = 0x000003ff;
s->regs[R_MODID] = s->revision;
s->regs[R_DESCONF] = 0x02D00111;
s->regs[R_DESCONF2] = 0x2ab10000 | s->jumbo_max_len;
s->regs[R_DESCONF5] = 0x002f2045;
- s->regs[R_DESCONF6] = GEM_DESCONF6_64B_MASK;
+ s->regs[R_DESCONF6] = R_DESCONF6_DMA_ADDR_64B_MASK;
s->regs[R_INT_Q1_MASK] = 0x00000CE6;
s->regs[R_JUMBO_MAX_LEN] = s->jumbo_max_len;
if (s->num_priority_queues > 1) {
queues_mask = MAKE_64BIT_MASK(1, s->num_priority_queues - 1);
--
2.39.2
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH 09/11] hw/net/cadence_gem: use FIELD to describe PHYMNTNC register fields
2023-10-17 19:44 [PATCH 00/11] Various updates for the Cadence GEM model Luc Michel
` (7 preceding siblings ...)
2023-10-17 19:44 ` [PATCH 08/11] hw/net/cadence_gem: use FIELD to describe DESCONF6 " Luc Michel
@ 2023-10-17 19:44 ` Luc Michel
2023-10-18 10:23 ` Boddu, Sai Pavan
2023-10-17 19:44 ` [PATCH 10/11] hw/net/cadence_gem: perform PHY access on write only Luc Michel
` (2 subsequent siblings)
11 siblings, 1 reply; 25+ messages in thread
From: Luc Michel @ 2023-10-17 19:44 UTC (permalink / raw)
To: qemu-devel
Cc: Luc Michel, qemu-arm, Edgar E . Iglesias, Alistair Francis,
Peter Maydell, Jason Wang, Philippe Mathieu-Daudé,
Francisco Iglesias, Frederic Konrad, Sai Pavan Boddu
Use the FIELD macro to describe the PHYMNTNC register fields.
Signed-off-by: Luc Michel <luc.michel@amd.com>
---
hw/net/cadence_gem.c | 27 ++++++++++++++-------------
1 file changed, 14 insertions(+), 13 deletions(-)
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index 955a8da134..4c5fe10316 100644
--- a/hw/net/cadence_gem.c
+++ b/hw/net/cadence_gem.c
@@ -192,10 +192,18 @@ REG32(ISR, 0x24) /* Interrupt Status reg */
REG32(IER, 0x28) /* Interrupt Enable reg */
REG32(IDR, 0x2c) /* Interrupt Disable reg */
REG32(IMR, 0x30) /* Interrupt Mask reg */
REG32(PHYMNTNC, 0x34) /* Phy Maintenance reg */
+ FIELD(PHYMNTNC, DATA, 0, 16)
+ FIELD(PHYMNTNC, REG_ADDR, 18, 5)
+ FIELD(PHYMNTNC, PHY_ADDR, 23, 5)
+ FIELD(PHYMNTNC, OP, 28, 2)
+ FIELD(PHYMNTNC, ST, 30, 2)
+#define MDIO_OP_READ 0x3
+#define MDIO_OP_WRITE 0x2
+
REG32(RXPAUSE, 0x38) /* RX Pause Time reg */
REG32(TXPAUSE, 0x3c) /* TX Pause Time reg */
REG32(TXPARTIALSF, 0x40) /* TX Partial Store and Forward */
REG32(RXPARTIALSF, 0x44) /* RX Partial Store and Forward */
REG32(JUMBO_MAX_LEN, 0x48) /* Max Jumbo Frame Size */
@@ -340,17 +348,10 @@ REG32(TYPE2_COMPARE_0_WORD_1, 0x704)
/*****************************************/
-#define GEM_PHYMNTNC_OP_R 0x20000000 /* read operation */
-#define GEM_PHYMNTNC_OP_W 0x10000000 /* write operation */
-#define GEM_PHYMNTNC_ADDR 0x0F800000 /* Address bits */
-#define GEM_PHYMNTNC_ADDR_SHFT 23
-#define GEM_PHYMNTNC_REG 0x007C0000 /* register bits */
-#define GEM_PHYMNTNC_REG_SHIFT 18
-
/* Marvell PHY definitions */
#define BOARD_PHY_ADDRESS 0 /* PHY address we will emulate a device at */
#define PHY_REG_CONTROL 0
#define PHY_REG_STATUS 1
@@ -1539,16 +1540,16 @@ static uint64_t gem_read(void *opaque, hwaddr offset, unsigned size)
case R_ISR:
DB_PRINT("lowering irqs on ISR read\n");
/* The interrupts get updated at the end of the function. */
break;
case R_PHYMNTNC:
- if (retval & GEM_PHYMNTNC_OP_R) {
+ if (FIELD_EX32(retval, PHYMNTNC, OP) == MDIO_OP_READ) {
uint32_t phy_addr, reg_num;
- phy_addr = (retval & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT;
+ phy_addr = FIELD_EX32(retval, PHYMNTNC, PHY_ADDR);
if (phy_addr == s->phy_addr) {
- reg_num = (retval & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT;
+ reg_num = FIELD_EX32(retval, PHYMNTNC, REG_ADDR);
retval &= 0xFFFF0000;
retval |= gem_phy_read(s, reg_num);
} else {
retval |= 0xFFFF; /* No device at this address */
}
@@ -1662,16 +1663,16 @@ static void gem_write(void *opaque, hwaddr offset, uint64_t val,
case R_SPADDR3HI:
case R_SPADDR4HI:
s->sar_active[(offset - R_SPADDR1HI) / 2] = true;
break;
case R_PHYMNTNC:
- if (val & GEM_PHYMNTNC_OP_W) {
+ if (FIELD_EX32(val, PHYMNTNC, OP) == MDIO_OP_WRITE) {
uint32_t phy_addr, reg_num;
- phy_addr = (val & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT;
+ phy_addr = FIELD_EX32(val, PHYMNTNC, PHY_ADDR);
if (phy_addr == s->phy_addr) {
- reg_num = (val & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT;
+ reg_num = FIELD_EX32(val, PHYMNTNC, REG_ADDR);
gem_phy_write(s, reg_num, val);
}
}
break;
}
--
2.39.2
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH 10/11] hw/net/cadence_gem: perform PHY access on write only
2023-10-17 19:44 [PATCH 00/11] Various updates for the Cadence GEM model Luc Michel
` (8 preceding siblings ...)
2023-10-17 19:44 ` [PATCH 09/11] hw/net/cadence_gem: use FIELD to describe PHYMNTNC " Luc Michel
@ 2023-10-17 19:44 ` Luc Michel
2023-10-18 10:35 ` Boddu, Sai Pavan
2023-10-17 19:44 ` [PATCH 11/11] hw/net/cadence_gem: enforce 32 bits variable size for CRC Luc Michel
2023-10-27 12:16 ` [PATCH 00/11] Various updates for the Cadence GEM model Peter Maydell
11 siblings, 1 reply; 25+ messages in thread
From: Luc Michel @ 2023-10-17 19:44 UTC (permalink / raw)
To: qemu-devel
Cc: Luc Michel, qemu-arm, Edgar E . Iglesias, Alistair Francis,
Peter Maydell, Jason Wang, Philippe Mathieu-Daudé,
Francisco Iglesias, Frederic Konrad, Sai Pavan Boddu
The MDIO access is done only on a write to the PHYMNTNC register. A
subsequent read is used to retrieve the result but does not trigger an
MDIO access by itself.
Refactor the PHY access logic to perform all accesses (MDIO reads and
writes) at PHYMNTNC write time.
Signed-off-by: Luc Michel <luc.michel@amd.com>
---
hw/net/cadence_gem.c | 56 ++++++++++++++++++++++++++------------------
1 file changed, 33 insertions(+), 23 deletions(-)
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index 4c5fe10316..21146f4242 100644
--- a/hw/net/cadence_gem.c
+++ b/hw/net/cadence_gem.c
@@ -1519,10 +1519,42 @@ static void gem_phy_write(CadenceGEMState *s, unsigned reg_num, uint16_t val)
break;
}
s->phy_regs[reg_num] = val;
}
+static void gem_handle_phy_access(CadenceGEMState *s)
+{
+ uint32_t val = s->regs[R_PHYMNTNC];
+ uint32_t phy_addr, reg_num;
+
+ phy_addr = FIELD_EX32(val, PHYMNTNC, PHY_ADDR);
+
+ if (phy_addr != s->phy_addr) {
+ /* no phy at this address */
+ if (FIELD_EX32(val, PHYMNTNC, OP) == MDIO_OP_READ) {
+ s->regs[R_PHYMNTNC] = FIELD_DP32(val, PHYMNTNC, DATA, 0xffff);
+ }
+ return;
+ }
+
+ reg_num = FIELD_EX32(val, PHYMNTNC, REG_ADDR);
+
+ switch (FIELD_EX32(val, PHYMNTNC, OP)) {
+ case MDIO_OP_READ:
+ s->regs[R_PHYMNTNC] = FIELD_DP32(val, PHYMNTNC, DATA,
+ gem_phy_read(s, reg_num));
+ break;
+
+ case MDIO_OP_WRITE:
+ gem_phy_write(s, reg_num, val);
+ break;
+
+ default:
+ break; /* only clause 22 operations are supported */
+ }
+}
+
/*
* gem_read32:
* Read a GEM register.
*/
static uint64_t gem_read(void *opaque, hwaddr offset, unsigned size)
@@ -1539,24 +1571,10 @@ static uint64_t gem_read(void *opaque, hwaddr offset, unsigned size)
switch (offset) {
case R_ISR:
DB_PRINT("lowering irqs on ISR read\n");
/* The interrupts get updated at the end of the function. */
break;
- case R_PHYMNTNC:
- if (FIELD_EX32(retval, PHYMNTNC, OP) == MDIO_OP_READ) {
- uint32_t phy_addr, reg_num;
-
- phy_addr = FIELD_EX32(retval, PHYMNTNC, PHY_ADDR);
- if (phy_addr == s->phy_addr) {
- reg_num = FIELD_EX32(retval, PHYMNTNC, REG_ADDR);
- retval &= 0xFFFF0000;
- retval |= gem_phy_read(s, reg_num);
- } else {
- retval |= 0xFFFF; /* No device at this address */
- }
- }
- break;
}
/* Squash read to clear bits */
s->regs[offset] &= ~(s->regs_rtc[offset]);
@@ -1663,19 +1681,11 @@ static void gem_write(void *opaque, hwaddr offset, uint64_t val,
case R_SPADDR3HI:
case R_SPADDR4HI:
s->sar_active[(offset - R_SPADDR1HI) / 2] = true;
break;
case R_PHYMNTNC:
- if (FIELD_EX32(val, PHYMNTNC, OP) == MDIO_OP_WRITE) {
- uint32_t phy_addr, reg_num;
-
- phy_addr = FIELD_EX32(val, PHYMNTNC, PHY_ADDR);
- if (phy_addr == s->phy_addr) {
- reg_num = FIELD_EX32(val, PHYMNTNC, REG_ADDR);
- gem_phy_write(s, reg_num, val);
- }
- }
+ gem_handle_phy_access(s);
break;
}
DB_PRINT("newval: 0x%08x\n", s->regs[offset]);
}
--
2.39.2
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH 11/11] hw/net/cadence_gem: enforce 32 bits variable size for CRC
2023-10-17 19:44 [PATCH 00/11] Various updates for the Cadence GEM model Luc Michel
` (9 preceding siblings ...)
2023-10-17 19:44 ` [PATCH 10/11] hw/net/cadence_gem: perform PHY access on write only Luc Michel
@ 2023-10-17 19:44 ` Luc Michel
2023-10-18 9:23 ` Philippe Mathieu-Daudé
2023-10-18 10:36 ` Boddu, Sai Pavan
2023-10-27 12:16 ` [PATCH 00/11] Various updates for the Cadence GEM model Peter Maydell
11 siblings, 2 replies; 25+ messages in thread
From: Luc Michel @ 2023-10-17 19:44 UTC (permalink / raw)
To: qemu-devel
Cc: Luc Michel, qemu-arm, Edgar E . Iglesias, Alistair Francis,
Peter Maydell, Jason Wang, Philippe Mathieu-Daudé,
Francisco Iglesias, Frederic Konrad, Sai Pavan Boddu
The CRC was stored in an unsigned variable in gem_receive. Change it for
a uint32_t to ensure we have the correct variable size here.
Signed-off-by: Luc Michel <luc.michel@amd.com>
---
hw/net/cadence_gem.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index 21146f4242..d52530bae4 100644
--- a/hw/net/cadence_gem.c
+++ b/hw/net/cadence_gem.c
@@ -1103,11 +1103,11 @@ static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size)
/* Strip of FCS field ? (usually yes) */
if (FIELD_EX32(s->regs[R_NWCFG], NWCFG, FCS_REMOVE)) {
rxbuf_ptr = (void *)buf;
} else {
- unsigned crc_val;
+ uint32_t crc_val;
if (size > MAX_FRAME_SIZE - sizeof(crc_val)) {
size = MAX_FRAME_SIZE - sizeof(crc_val);
}
bytes_to_copy = size;
--
2.39.2
^ permalink raw reply related [flat|nested] 25+ messages in thread
* RE: [PATCH 01/11] hw/net/cadence_gem: use REG32 macro for register definitions
2023-10-17 19:44 ` [PATCH 01/11] hw/net/cadence_gem: use REG32 macro for register definitions Luc Michel
@ 2023-10-18 6:22 ` Boddu, Sai Pavan
0 siblings, 0 replies; 25+ messages in thread
From: Boddu, Sai Pavan @ 2023-10-18 6:22 UTC (permalink / raw)
To: Michel, Luc, qemu-devel@nongnu.org
Cc: Michel, Luc, qemu-arm@nongnu.org, Edgar E . Iglesias,
Alistair Francis, Peter Maydell, Jason Wang,
Philippe Mathieu-Daudé, Iglesias, Francisco,
Konrad, Frederic
Reviewed-by: sai.pavan.boddu@amd.com
Regards,
Sai Pavan
>-----Original Message-----
>From: Luc Michel <luc.michel@amd.com>
>Sent: Wednesday, October 18, 2023 1:14 AM
>To: qemu-devel@nongnu.org
>Cc: Michel, Luc <Luc.Michel@amd.com>; qemu-arm@nongnu.org; Edgar E .
>Iglesias <edgar.iglesias@gmail.com>; Alistair Francis <alistair@alistair23.me>;
>Peter Maydell <peter.maydell@linaro.org>; Jason Wang
><jasowang@redhat.com>; Philippe Mathieu-Daudé <philmd@linaro.org>;
>Iglesias, Francisco <francisco.iglesias@amd.com>; Konrad, Frederic
><Frederic.Konrad@amd.com>; Boddu, Sai Pavan
><sai.pavan.boddu@amd.com>
>Subject: [PATCH 01/11] hw/net/cadence_gem: use REG32 macro for register
>definitions
>
>Replace register defines with the REG32 macro from registerfields.h in the
>Cadence GEM device.
>
>Signed-off-by: Luc Michel <luc.michel@amd.com>
>---
> hw/net/cadence_gem.c | 527 +++++++++++++++++++++----------------------
> 1 file changed, 261 insertions(+), 266 deletions(-)
>
>diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c index
>f445d8bb5e..0e5744ecd7 100644
>--- a/hw/net/cadence_gem.c
>+++ b/hw/net/cadence_gem.c
>@@ -26,10 +26,11 @@
> #include <zlib.h> /* For crc32 */
>
> #include "hw/irq.h"
> #include "hw/net/cadence_gem.h"
> #include "hw/qdev-properties.h"
>+#include "hw/registerfields.h"
> #include "migration/vmstate.h"
> #include "qapi/error.h"
> #include "qemu/log.h"
> #include "qemu/module.h"
> #include "sysemu/dma.h"
>@@ -42,151 +43,146 @@
> qemu_log(": %s: ", __func__); \
> qemu_log(__VA_ARGS__); \
> } \
> } while (0)
>
>-#define GEM_NWCTRL (0x00000000 / 4) /* Network Control reg */
>-#define GEM_NWCFG (0x00000004 / 4) /* Network Config reg */
>-#define GEM_NWSTATUS (0x00000008 / 4) /* Network Status reg */
>-#define GEM_USERIO (0x0000000C / 4) /* User IO reg */
>-#define GEM_DMACFG (0x00000010 / 4) /* DMA Control reg */
>-#define GEM_TXSTATUS (0x00000014 / 4) /* TX Status reg */
>-#define GEM_RXQBASE (0x00000018 / 4) /* RX Q Base address reg */
>-#define GEM_TXQBASE (0x0000001C / 4) /* TX Q Base address reg */
>-#define GEM_RXSTATUS (0x00000020 / 4) /* RX Status reg */
>-#define GEM_ISR (0x00000024 / 4) /* Interrupt Status reg */
>-#define GEM_IER (0x00000028 / 4) /* Interrupt Enable reg */
>-#define GEM_IDR (0x0000002C / 4) /* Interrupt Disable reg */
>-#define GEM_IMR (0x00000030 / 4) /* Interrupt Mask reg */
>-#define GEM_PHYMNTNC (0x00000034 / 4) /* Phy Maintenance reg */
>-#define GEM_RXPAUSE (0x00000038 / 4) /* RX Pause Time reg */
>-#define GEM_TXPAUSE (0x0000003C / 4) /* TX Pause Time reg */
>-#define GEM_TXPARTIALSF (0x00000040 / 4) /* TX Partial Store and Forward
>*/
>-#define GEM_RXPARTIALSF (0x00000044 / 4) /* RX Partial Store and Forward
>*/
>-#define GEM_JUMBO_MAX_LEN (0x00000048 / 4) /* Max Jumbo Frame Size
>*/
>-#define GEM_HASHLO (0x00000080 / 4) /* Hash Low address reg */
>-#define GEM_HASHHI (0x00000084 / 4) /* Hash High address reg */
>-#define GEM_SPADDR1LO (0x00000088 / 4) /* Specific addr 1 low reg */
>-#define GEM_SPADDR1HI (0x0000008C / 4) /* Specific addr 1 high reg */
>-#define GEM_SPADDR2LO (0x00000090 / 4) /* Specific addr 2 low reg */
>-#define GEM_SPADDR2HI (0x00000094 / 4) /* Specific addr 2 high reg */
>-#define GEM_SPADDR3LO (0x00000098 / 4) /* Specific addr 3 low reg */
>-#define GEM_SPADDR3HI (0x0000009C / 4) /* Specific addr 3 high reg */
>-#define GEM_SPADDR4LO (0x000000A0 / 4) /* Specific addr 4 low reg */
>-#define GEM_SPADDR4HI (0x000000A4 / 4) /* Specific addr 4 high reg */
>-#define GEM_TIDMATCH1 (0x000000A8 / 4) /* Type ID1 Match reg */
>-#define GEM_TIDMATCH2 (0x000000AC / 4) /* Type ID2 Match reg */
>-#define GEM_TIDMATCH3 (0x000000B0 / 4) /* Type ID3 Match reg */
>-#define GEM_TIDMATCH4 (0x000000B4 / 4) /* Type ID4 Match reg */
>-#define GEM_WOLAN (0x000000B8 / 4) /* Wake on LAN reg */
>-#define GEM_IPGSTRETCH (0x000000BC / 4) /* IPG Stretch reg */
>-#define GEM_SVLAN (0x000000C0 / 4) /* Stacked VLAN reg */
>-#define GEM_MODID (0x000000FC / 4) /* Module ID reg */
>-#define GEM_OCTTXLO (0x00000100 / 4) /* Octets transmitted Low reg */
>-#define GEM_OCTTXHI (0x00000104 / 4) /* Octets transmitted High reg */
>-#define GEM_TXCNT (0x00000108 / 4) /* Error-free Frames transmitted
>*/
>-#define GEM_TXBCNT (0x0000010C / 4) /* Error-free Broadcast Frames */
>-#define GEM_TXMCNT (0x00000110 / 4) /* Error-free Multicast Frame */
>-#define GEM_TXPAUSECNT (0x00000114 / 4) /* Pause Frames Transmitted
>*/
>-#define GEM_TX64CNT (0x00000118 / 4) /* Error-free 64 TX */
>-#define GEM_TX65CNT (0x0000011C / 4) /* Error-free 65-127 TX */
>-#define GEM_TX128CNT (0x00000120 / 4) /* Error-free 128-255 TX */
>-#define GEM_TX256CNT (0x00000124 / 4) /* Error-free 256-511 */
>-#define GEM_TX512CNT (0x00000128 / 4) /* Error-free 512-1023 TX */
>-#define GEM_TX1024CNT (0x0000012C / 4) /* Error-free 1024-1518 TX */
>-#define GEM_TX1519CNT (0x00000130 / 4) /* Error-free larger than 1519
>TX */
>-#define GEM_TXURUNCNT (0x00000134 / 4) /* TX under run error counter
>*/
>-#define GEM_SINGLECOLLCNT (0x00000138 / 4) /* Single Collision Frames */
>-#define GEM_MULTCOLLCNT (0x0000013C / 4) /* Multiple Collision Frames
>*/
>-#define GEM_EXCESSCOLLCNT (0x00000140 / 4) /* Excessive Collision Frames
>*/
>-#define GEM_LATECOLLCNT (0x00000144 / 4) /* Late Collision Frames */
>-#define GEM_DEFERTXCNT (0x00000148 / 4) /* Deferred Transmission
>Frames */
>-#define GEM_CSENSECNT (0x0000014C / 4) /* Carrier Sense Error Counter
>*/
>-#define GEM_OCTRXLO (0x00000150 / 4) /* Octets Received register Low
>*/
>-#define GEM_OCTRXHI (0x00000154 / 4) /* Octets Received register High
>*/
>-#define GEM_RXCNT (0x00000158 / 4) /* Error-free Frames Received */
>-#define GEM_RXBROADCNT (0x0000015C / 4) /* Error-free Broadcast
>Frames RX */
>-#define GEM_RXMULTICNT (0x00000160 / 4) /* Error-free Multicast Frames
>RX */
>-#define GEM_RXPAUSECNT (0x00000164 / 4) /* Pause Frames Received
>Counter */
>-#define GEM_RX64CNT (0x00000168 / 4) /* Error-free 64 byte Frames RX
>*/
>-#define GEM_RX65CNT (0x0000016C / 4) /* Error-free 65-127B Frames RX
>*/
>-#define GEM_RX128CNT (0x00000170 / 4) /* Error-free 128-255B Frames
>RX */
>-#define GEM_RX256CNT (0x00000174 / 4) /* Error-free 256-512B Frames
>RX */
>-#define GEM_RX512CNT (0x00000178 / 4) /* Error-free 512-1023B
>Frames RX */
>-#define GEM_RX1024CNT (0x0000017C / 4) /* Error-free 1024-1518B
>Frames RX */
>-#define GEM_RX1519CNT (0x00000180 / 4) /* Error-free 1519-max Frames
>RX */
>-#define GEM_RXUNDERCNT (0x00000184 / 4) /* Undersize Frames Received
>*/
>-#define GEM_RXOVERCNT (0x00000188 / 4) /* Oversize Frames Received */
>-#define GEM_RXJABCNT (0x0000018C / 4) /* Jabbers Received Counter */
>-#define GEM_RXFCSCNT (0x00000190 / 4) /* Frame Check seq. Error
>Counter */
>-#define GEM_RXLENERRCNT (0x00000194 / 4) /* Length Field Error Counter
>*/
>-#define GEM_RXSYMERRCNT (0x00000198 / 4) /* Symbol Error Counter */
>-#define GEM_RXALIGNERRCNT (0x0000019C / 4) /* Alignment Error Counter
>*/
>-#define GEM_RXRSCERRCNT (0x000001A0 / 4) /* Receive Resource Error
>Counter */
>-#define GEM_RXORUNCNT (0x000001A4 / 4) /* Receive Overrun Counter */
>-#define GEM_RXIPCSERRCNT (0x000001A8 / 4) /* IP header Checksum Err
>Counter */
>-#define GEM_RXTCPCCNT (0x000001AC / 4) /* TCP Checksum Error
>Counter */
>-#define GEM_RXUDPCCNT (0x000001B0 / 4) /* UDP Checksum Error
>Counter */
>+REG32(NWCTRL, 0x0) /* Network Control reg */ REG32(NWCFG, 0x4) /*
>+Network Config reg */ REG32(NWSTATUS, 0x8) /* Network Status reg */
>+REG32(USERIO, 0xc) /* User IO reg */ REG32(DMACFG, 0x10) /* DMA Control
>+reg */ REG32(TXSTATUS, 0x14) /* TX Status reg */ REG32(RXQBASE, 0x18)
>+/* RX Q Base address reg */ REG32(TXQBASE, 0x1c) /* TX Q Base address
>+reg */ REG32(RXSTATUS, 0x20) /* RX Status reg */ REG32(ISR, 0x24) /*
>+Interrupt Status reg */ REG32(IER, 0x28) /* Interrupt Enable reg */
>+REG32(IDR, 0x2c) /* Interrupt Disable reg */ REG32(IMR, 0x30) /*
>+Interrupt Mask reg */ REG32(PHYMNTNC, 0x34) /* Phy Maintenance reg */
>+REG32(RXPAUSE, 0x38) /* RX Pause Time reg */ REG32(TXPAUSE, 0x3c) /* TX
>+Pause Time reg */ REG32(TXPARTIALSF, 0x40) /* TX Partial Store and
>+Forward */ REG32(RXPARTIALSF, 0x44) /* RX Partial Store and Forward */
>+REG32(JUMBO_MAX_LEN, 0x48) /* Max Jumbo Frame Size */
>REG32(HASHLO,
>+0x80) /* Hash Low address reg */ REG32(HASHHI, 0x84) /* Hash High
>+address reg */ REG32(SPADDR1LO, 0x88) /* Specific addr 1 low reg */
>+REG32(SPADDR1HI, 0x8c) /* Specific addr 1 high reg */ REG32(SPADDR2LO,
>+0x90) /* Specific addr 2 low reg */ REG32(SPADDR2HI, 0x94) /* Specific
>+addr 2 high reg */ REG32(SPADDR3LO, 0x98) /* Specific addr 3 low reg */
>+REG32(SPADDR3HI, 0x9c) /* Specific addr 3 high reg */ REG32(SPADDR4LO,
>+0xa0) /* Specific addr 4 low reg */ REG32(SPADDR4HI, 0xa4) /* Specific
>+addr 4 high reg */ REG32(TIDMATCH1, 0xa8) /* Type ID1 Match reg */
>+REG32(TIDMATCH2, 0xac) /* Type ID2 Match reg */ REG32(TIDMATCH3,
>0xb0)
>+/* Type ID3 Match reg */ REG32(TIDMATCH4, 0xb4) /* Type ID4 Match reg
>+*/ REG32(WOLAN, 0xb8) /* Wake on LAN reg */ REG32(IPGSTRETCH, 0xbc) /*
>+IPG Stretch reg */ REG32(SVLAN, 0xc0) /* Stacked VLAN reg */
>+REG32(MODID, 0xfc) /* Module ID reg */ REG32(OCTTXLO, 0x100) /* Octects
>+transmitted Low reg */ REG32(OCTTXHI, 0x104) /* Octects transmitted
>+High reg */ REG32(TXCNT, 0x108) /* Error-free Frames transmitted */
>+REG32(TXBCNT, 0x10c) /* Error-free Broadcast Frames */ REG32(TXMCNT,
>+0x110) /* Error-free Multicast Frame */ REG32(TXPAUSECNT, 0x114) /*
>+Pause Frames Transmitted */ REG32(TX64CNT, 0x118) /* Error-free 64 TX
>+*/ REG32(TX65CNT, 0x11c) /* Error-free 65-127 TX */ REG32(TX128CNT,
>+0x120) /* Error-free 128-255 TX */ REG32(TX256CNT, 0x124) /* Error-free
>+256-511 */ REG32(TX512CNT, 0x128) /* Error-free 512-1023 TX */
>+REG32(TX1024CNT, 0x12c) /* Error-free 1024-1518 TX */
>REG32(TX1519CNT,
>+0x130) /* Error-free larger than 1519 TX */ REG32(TXURUNCNT, 0x134) /*
>+TX under run error counter */ REG32(SINGLECOLLCNT, 0x138) /* Single
>+Collision Frames */ REG32(MULTCOLLCNT, 0x13c) /* Multiple Collision
>+Frames */ REG32(EXCESSCOLLCNT, 0x140) /* Excessive Collision Frames */
>+REG32(LATECOLLCNT, 0x144) /* Late Collision Frames */ REG32(DEFERTXCNT,
>+0x148) /* Deferred Transmission Frames */ REG32(CSENSECNT, 0x14c) /*
>+Carrier Sense Error Counter */ REG32(OCTRXLO, 0x150) /* Octects
>+Received register Low */ REG32(OCTRXHI, 0x154) /* Octects Received
>+register High */ REG32(RXCNT, 0x158) /* Error-free Frames Received */
>+REG32(RXBROADCNT, 0x15c) /* Error-free Broadcast Frames RX */
>+REG32(RXMULTICNT, 0x160) /* Error-free Multicast Frames RX */
>+REG32(RXPAUSECNT, 0x164) /* Pause Frames Received Counter */
>+REG32(RX64CNT, 0x168) /* Error-free 64 byte Frames RX */ REG32(RX65CNT,
>+0x16c) /* Error-free 65-127B Frames RX */ REG32(RX128CNT, 0x170) /*
>+Error-free 128-255B Frames RX */ REG32(RX256CNT, 0x174) /* Error-free
>+256-512B Frames RX */ REG32(RX512CNT, 0x178) /* Error-free 512-1023B
>+Frames RX */ REG32(RX1024CNT, 0x17c) /* Error-free 1024-1518B Frames
>RX
>+*/ REG32(RX1519CNT, 0x180) /* Error-free 1519-max Frames RX */
>+REG32(RXUNDERCNT, 0x184) /* Undersize Frames Received */
>+REG32(RXOVERCNT, 0x188) /* Oversize Frames Received */
>REG32(RXJABCNT,
>+0x18c) /* Jabbers Received Counter */ REG32(RXFCSCNT, 0x190) /* Frame
>+Check seq. Error Counter */ REG32(RXLENERRCNT, 0x194) /* Length Field
>+Error Counter */ REG32(RXSYMERRCNT, 0x198) /* Symbol Error Counter */
>+REG32(RXALIGNERRCNT, 0x19c) /* Alignment Error Counter */
>+REG32(RXRSCERRCNT, 0x1a0) /* Receive Resource Error Counter */
>+REG32(RXORUNCNT, 0x1a4) /* Receive Overrun Counter */
>+REG32(RXIPCSERRCNT, 0x1a8) /* IP header Checksum Err Counter */
>+REG32(RXTCPCCNT, 0x1ac) /* TCP Checksum Error Counter */
>+REG32(RXUDPCCNT, 0x1b0) /* UDP Checksum Error Counter */
>
>-#define GEM_1588S (0x000001D0 / 4) /* 1588 Timer Seconds */
>-#define GEM_1588NS (0x000001D4 / 4) /* 1588 Timer Nanoseconds */
>-#define GEM_1588ADJ (0x000001D8 / 4) /* 1588 Timer Adjust */
>-#define GEM_1588INC (0x000001DC / 4) /* 1588 Timer Increment */
>-#define GEM_PTPETXS (0x000001E0 / 4) /* PTP Event Frame Transmitted
>(s) */
>-#define GEM_PTPETXNS (0x000001E4 / 4) /*
>- * PTP Event Frame Transmitted (ns)
>- */
>-#define GEM_PTPERXS (0x000001E8 / 4) /* PTP Event Frame Received (s)
>*/
>-#define GEM_PTPERXNS (0x000001EC / 4) /* PTP Event Frame Received
>(ns) */
>-#define GEM_PTPPTXS (0x000001E0 / 4) /* PTP Peer Frame Transmitted (s)
>*/
>-#define GEM_PTPPTXNS (0x000001E4 / 4) /* PTP Peer Frame Transmitted
>(ns) */
>-#define GEM_PTPPRXS (0x000001E8 / 4) /* PTP Peer Frame Received (s) */
>-#define GEM_PTPPRXNS (0x000001EC / 4) /* PTP Peer Frame Received (ns)
>*/
>+REG32(1588S, 0x1d0) /* 1588 Timer Seconds */ REG32(1588NS, 0x1d4) /*
>+1588 Timer Nanoseconds */ REG32(1588ADJ, 0x1d8) /* 1588 Timer Adjust
>*/
>+REG32(1588INC, 0x1dc) /* 1588 Timer Increment */ REG32(PTPETXS, 0x1e0)
>+/* PTP Event Frame Transmitted (s) */ REG32(PTPETXNS, 0x1e4) /* PTP
>+Event Frame Transmitted (ns) */ REG32(PTPERXS, 0x1e8) /* PTP Event
>+Frame Received (s) */ REG32(PTPERXNS, 0x1ec) /* PTP Event Frame
>+Received (ns) */ REG32(PTPPTXS, 0x1e0) /* PTP Peer Frame Transmitted
>+(s) */ REG32(PTPPTXNS, 0x1e4) /* PTP Peer Frame Transmitted (ns) */
>+REG32(PTPPRXS, 0x1e8) /* PTP Peer Frame Received (s) */ REG32(PTPPRXNS,
>+0x1ec) /* PTP Peer Frame Received (ns) */
>
> /* Design Configuration Registers */
>-#define GEM_DESCONF (0x00000280 / 4)
>-#define GEM_DESCONF2 (0x00000284 / 4)
>-#define GEM_DESCONF3 (0x00000288 / 4)
>-#define GEM_DESCONF4 (0x0000028C / 4)
>-#define GEM_DESCONF5 (0x00000290 / 4)
>-#define GEM_DESCONF6 (0x00000294 / 4)
>+REG32(DESCONF, 0x280)
>+REG32(DESCONF2, 0x284)
>+REG32(DESCONF3, 0x288)
>+REG32(DESCONF4, 0x28c)
>+REG32(DESCONF5, 0x290)
>+REG32(DESCONF6, 0x294)
> #define GEM_DESCONF6_64B_MASK (1U << 23)
>-#define GEM_DESCONF7 (0x00000298 / 4)
>+REG32(DESCONF7, 0x298)
>
>-#define GEM_INT_Q1_STATUS (0x00000400 / 4)
>-#define GEM_INT_Q1_MASK (0x00000640 / 4)
>+REG32(INT_Q1_STATUS, 0x400)
>+REG32(INT_Q1_MASK, 0x640)
>
>-#define GEM_TRANSMIT_Q1_PTR (0x00000440 / 4)
>-#define GEM_TRANSMIT_Q7_PTR (GEM_TRANSMIT_Q1_PTR + 6)
>+REG32(TRANSMIT_Q1_PTR, 0x440)
>+REG32(TRANSMIT_Q7_PTR, 0x458)
>
>-#define GEM_RECEIVE_Q1_PTR (0x00000480 / 4)
>-#define GEM_RECEIVE_Q7_PTR (GEM_RECEIVE_Q1_PTR + 6)
>+REG32(RECEIVE_Q1_PTR, 0x480)
>+REG32(RECEIVE_Q7_PTR, 0x498)
>
>-#define GEM_TBQPH (0x000004C8 / 4)
>-#define GEM_RBQPH (0x000004D4 / 4)
>+REG32(TBQPH, 0x4c8)
>+REG32(RBQPH, 0x4d4)
>
>-#define GEM_INT_Q1_ENABLE (0x00000600 / 4)
>-#define GEM_INT_Q7_ENABLE (GEM_INT_Q1_ENABLE + 6)
>+REG32(INT_Q1_ENABLE, 0x600)
>+REG32(INT_Q7_ENABLE, 0x618)
>
>-#define GEM_INT_Q1_DISABLE (0x00000620 / 4)
>-#define GEM_INT_Q7_DISABLE (GEM_INT_Q1_DISABLE + 6)
>+REG32(INT_Q1_DISABLE, 0x620)
>+REG32(INT_Q7_DISABLE, 0x638)
>
>-#define GEM_INT_Q1_MASK (0x00000640 / 4)
>-#define GEM_INT_Q7_MASK (GEM_INT_Q1_MASK + 6)
>-
>-#define GEM_SCREENING_TYPE1_REGISTER_0 (0x00000500 / 4)
>+REG32(SCREENING_TYPE1_REG0, 0x500)
>
> #define GEM_ST1R_UDP_PORT_MATCH_ENABLE (1 << 29)
> #define GEM_ST1R_DSTC_ENABLE (1 << 28)
> #define GEM_ST1R_UDP_PORT_MATCH_SHIFT (12)
> #define GEM_ST1R_UDP_PORT_MATCH_WIDTH (27 -
>GEM_ST1R_UDP_PORT_MATCH_SHIFT + 1)
> #define GEM_ST1R_DSTC_MATCH_SHIFT (4)
> #define GEM_ST1R_DSTC_MATCH_WIDTH (11 -
>GEM_ST1R_DSTC_MATCH_SHIFT + 1)
> #define GEM_ST1R_QUEUE_SHIFT (0)
> #define GEM_ST1R_QUEUE_WIDTH (3 - GEM_ST1R_QUEUE_SHIFT + 1)
>
>-#define GEM_SCREENING_TYPE2_REGISTER_0 (0x00000540 / 4)
>+REG32(SCREENING_TYPE2_REG0, 0x540)
>
> #define GEM_ST2R_COMPARE_A_ENABLE (1 << 18)
> #define GEM_ST2R_COMPARE_A_SHIFT (13)
> #define GEM_ST2R_COMPARE_WIDTH (17 -
>GEM_ST2R_COMPARE_A_SHIFT + 1)
> #define GEM_ST2R_ETHERTYPE_ENABLE (1 << 12)
>@@ -194,12 +190,12 @@
> #define GEM_ST2R_ETHERTYPE_INDEX_WIDTH (11 -
>GEM_ST2R_ETHERTYPE_INDEX_SHIFT \
> + 1)
> #define GEM_ST2R_QUEUE_SHIFT (0)
> #define GEM_ST2R_QUEUE_WIDTH (3 - GEM_ST2R_QUEUE_SHIFT + 1)
>
>-#define GEM_SCREENING_TYPE2_ETHERTYPE_REG_0 (0x000006e0 / 4)
>-#define GEM_TYPE2_COMPARE_0_WORD_0 (0x00000700 / 4)
>+REG32(SCREENING_TYPE2_ETHERTYPE_REG0, 0x6e0)
>+REG32(TYPE2_COMPARE_0_WORD_0, 0x700)
>
> #define GEM_T2CW1_COMPARE_OFFSET_SHIFT (7) #define
>GEM_T2CW1_COMPARE_OFFSET_WIDTH (8 -
>GEM_T2CW1_COMPARE_OFFSET_SHIFT + 1)
> #define GEM_T2CW1_OFFSET_VALUE_SHIFT (0)
> #define GEM_T2CW1_OFFSET_VALUE_WIDTH (6 -
>GEM_T2CW1_OFFSET_VALUE_SHIFT + 1)
>@@ -323,11 +319,11 @@
>
> static inline uint64_t tx_desc_get_buffer(CadenceGEMState *s, uint32_t *desc)
>{
> uint64_t ret = desc[0];
>
>- if (s->regs[GEM_DMACFG] & GEM_DMACFG_ADDR_64B) {
>+ if (s->regs[R_DMACFG] & GEM_DMACFG_ADDR_64B) {
> ret |= (uint64_t)desc[2] << 32;
> }
> return ret;
> }
>
>@@ -368,24 +364,24 @@ static inline void print_gem_tx_desc(uint32_t *desc,
>uint8_t queue)
>
> static inline uint64_t rx_desc_get_buffer(CadenceGEMState *s, uint32_t *desc)
>{
> uint64_t ret = desc[0] & ~0x3UL;
>
>- if (s->regs[GEM_DMACFG] & GEM_DMACFG_ADDR_64B) {
>+ if (s->regs[R_DMACFG] & GEM_DMACFG_ADDR_64B) {
> ret |= (uint64_t)desc[2] << 32;
> }
> return ret;
> }
>
> static inline int gem_get_desc_len(CadenceGEMState *s, bool rx_n_tx) {
> int ret = 2;
>
>- if (s->regs[GEM_DMACFG] & GEM_DMACFG_ADDR_64B) {
>+ if (s->regs[R_DMACFG] & GEM_DMACFG_ADDR_64B) {
> ret += 2;
> }
>- if (s->regs[GEM_DMACFG] & (rx_n_tx ? GEM_DMACFG_RX_BD_EXT
>+ if (s->regs[R_DMACFG] & (rx_n_tx ? GEM_DMACFG_RX_BD_EXT
> : GEM_DMACFG_TX_BD_EXT)) {
> ret += 2;
> }
>
> assert(ret <= DESC_MAX_NUM_WORDS);
>@@ -454,32 +450,32 @@ static inline void rx_desc_set_sar(uint32_t *desc, int
>sar_idx) static const uint8_t broadcast_addr[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
>0xFF };
>
> static uint32_t gem_get_max_buf_len(CadenceGEMState *s, bool tx) {
> uint32_t size;
>- if (s->regs[GEM_NWCFG] & GEM_NWCFG_JUMBO_FRAME) {
>- size = s->regs[GEM_JUMBO_MAX_LEN];
>+ if (s->regs[R_NWCFG] & GEM_NWCFG_JUMBO_FRAME) {
>+ size = s->regs[R_JUMBO_MAX_LEN];
> if (size > s->jumbo_max_len) {
> size = s->jumbo_max_len;
> qemu_log_mask(LOG_GUEST_ERROR, "GEM_JUMBO_MAX_LEN reg
>cannot be"
> " greater than 0x%" PRIx32 "\n", s->jumbo_max_len);
> }
> } else if (tx) {
> size = 1518;
> } else {
>- size = s->regs[GEM_NWCFG] & GEM_NWCFG_RCV_1538 ? 1538 : 1518;
>+ size = s->regs[R_NWCFG] & GEM_NWCFG_RCV_1538 ? 1538 : 1518;
> }
> return size;
> }
>
> static void gem_set_isr(CadenceGEMState *s, int q, uint32_t flag) {
> if (q == 0) {
>- s->regs[GEM_ISR] |= flag & ~(s->regs[GEM_IMR]);
>+ s->regs[R_ISR] |= flag & ~(s->regs[R_IMR]);
> } else {
>- s->regs[GEM_INT_Q1_STATUS + q - 1] |= flag &
>- ~(s->regs[GEM_INT_Q1_MASK + q - 1]);
>+ s->regs[R_INT_Q1_STATUS + q - 1] |= flag &
>+ ~(s->regs[R_INT_Q1_MASK + q -
>+ 1]);
> }
> }
>
> /*
> * gem_init_register_masks:
>@@ -489,47 +485,47 @@ static void gem_set_isr(CadenceGEMState *s, int q,
>uint32_t flag) static void gem_init_register_masks(CadenceGEMState *s) {
> unsigned int i;
> /* Mask of register bits which are read only */
> memset(&s->regs_ro[0], 0, sizeof(s->regs_ro));
>- s->regs_ro[GEM_NWCTRL] = 0xFFF80000;
>- s->regs_ro[GEM_NWSTATUS] = 0xFFFFFFFF;
>- s->regs_ro[GEM_DMACFG] = 0x8E00F000;
>- s->regs_ro[GEM_TXSTATUS] = 0xFFFFFE08;
>- s->regs_ro[GEM_RXQBASE] = 0x00000003;
>- s->regs_ro[GEM_TXQBASE] = 0x00000003;
>- s->regs_ro[GEM_RXSTATUS] = 0xFFFFFFF0;
>- s->regs_ro[GEM_ISR] = 0xFFFFFFFF;
>- s->regs_ro[GEM_IMR] = 0xFFFFFFFF;
>- s->regs_ro[GEM_MODID] = 0xFFFFFFFF;
>+ s->regs_ro[R_NWCTRL] = 0xFFF80000;
>+ s->regs_ro[R_NWSTATUS] = 0xFFFFFFFF;
>+ s->regs_ro[R_DMACFG] = 0x8E00F000;
>+ s->regs_ro[R_TXSTATUS] = 0xFFFFFE08;
>+ s->regs_ro[R_RXQBASE] = 0x00000003;
>+ s->regs_ro[R_TXQBASE] = 0x00000003;
>+ s->regs_ro[R_RXSTATUS] = 0xFFFFFFF0;
>+ s->regs_ro[R_ISR] = 0xFFFFFFFF;
>+ s->regs_ro[R_IMR] = 0xFFFFFFFF;
>+ s->regs_ro[R_MODID] = 0xFFFFFFFF;
> for (i = 0; i < s->num_priority_queues; i++) {
>- s->regs_ro[GEM_INT_Q1_STATUS + i] = 0xFFFFFFFF;
>- s->regs_ro[GEM_INT_Q1_ENABLE + i] = 0xFFFFF319;
>- s->regs_ro[GEM_INT_Q1_DISABLE + i] = 0xFFFFF319;
>- s->regs_ro[GEM_INT_Q1_MASK + i] = 0xFFFFFFFF;
>+ s->regs_ro[R_INT_Q1_STATUS + i] = 0xFFFFFFFF;
>+ s->regs_ro[R_INT_Q1_ENABLE + i] = 0xFFFFF319;
>+ s->regs_ro[R_INT_Q1_DISABLE + i] = 0xFFFFF319;
>+ s->regs_ro[R_INT_Q1_MASK + i] = 0xFFFFFFFF;
> }
>
> /* Mask of register bits which are clear on read */
> memset(&s->regs_rtc[0], 0, sizeof(s->regs_rtc));
>- s->regs_rtc[GEM_ISR] = 0xFFFFFFFF;
>+ s->regs_rtc[R_ISR] = 0xFFFFFFFF;
> for (i = 0; i < s->num_priority_queues; i++) {
>- s->regs_rtc[GEM_INT_Q1_STATUS + i] = 0x00000CE6;
>+ s->regs_rtc[R_INT_Q1_STATUS + i] = 0x00000CE6;
> }
>
> /* Mask of register bits which are write 1 to clear */
> memset(&s->regs_w1c[0], 0, sizeof(s->regs_w1c));
>- s->regs_w1c[GEM_TXSTATUS] = 0x000001F7;
>- s->regs_w1c[GEM_RXSTATUS] = 0x0000000F;
>+ s->regs_w1c[R_TXSTATUS] = 0x000001F7;
>+ s->regs_w1c[R_RXSTATUS] = 0x0000000F;
>
> /* Mask of register bits which are write only */
> memset(&s->regs_wo[0], 0, sizeof(s->regs_wo));
>- s->regs_wo[GEM_NWCTRL] = 0x00073E60;
>- s->regs_wo[GEM_IER] = 0x07FFFFFF;
>- s->regs_wo[GEM_IDR] = 0x07FFFFFF;
>+ s->regs_wo[R_NWCTRL] = 0x00073E60;
>+ s->regs_wo[R_IER] = 0x07FFFFFF;
>+ s->regs_wo[R_IDR] = 0x07FFFFFF;
> for (i = 0; i < s->num_priority_queues; i++) {
>- s->regs_wo[GEM_INT_Q1_ENABLE + i] = 0x00000CE6;
>- s->regs_wo[GEM_INT_Q1_DISABLE + i] = 0x00000CE6;
>+ s->regs_wo[R_INT_Q1_ENABLE + i] = 0x00000CE6;
>+ s->regs_wo[R_INT_Q1_DISABLE + i] = 0x00000CE6;
> }
> }
>
> /*
> * phy_update_link:
>@@ -559,11 +555,11 @@ static bool gem_can_receive(NetClientState *nc)
> int i;
>
> s = qemu_get_nic_opaque(nc);
>
> /* Do nothing if receive is not enabled. */
>- if (!(s->regs[GEM_NWCTRL] & GEM_NWCTRL_RXENA)) {
>+ if (!(s->regs[R_NWCTRL] & GEM_NWCTRL_RXENA)) {
> if (s->can_rx_state != 1) {
> s->can_rx_state = 1;
> DB_PRINT("can't receive - no enable\n");
> }
> return false;
>@@ -596,14 +592,14 @@ static bool gem_can_receive(NetClientState *nc)
> */
> static void gem_update_int_status(CadenceGEMState *s) {
> int i;
>
>- qemu_set_irq(s->irq[0], !!s->regs[GEM_ISR]);
>+ qemu_set_irq(s->irq[0], !!s->regs[R_ISR]);
>
> for (i = 1; i < s->num_priority_queues; ++i) {
>- qemu_set_irq(s->irq[i], !!s->regs[GEM_INT_Q1_STATUS + i - 1]);
>+ qemu_set_irq(s->irq[i], !!s->regs[R_INT_Q1_STATUS + i - 1]);
> }
> }
>
> /*
> * gem_receive_updatestats:
>@@ -613,43 +609,43 @@ static void
>gem_receive_updatestats(CadenceGEMState *s, const uint8_t *packet,
> unsigned bytes) {
> uint64_t octets;
>
> /* Total octets (bytes) received */
>- octets = ((uint64_t)(s->regs[GEM_OCTRXLO]) << 32) |
>- s->regs[GEM_OCTRXHI];
>+ octets = ((uint64_t)(s->regs[R_OCTRXLO]) << 32) |
>+ s->regs[R_OCTRXHI];
> octets += bytes;
>- s->regs[GEM_OCTRXLO] = octets >> 32;
>- s->regs[GEM_OCTRXHI] = octets;
>+ s->regs[R_OCTRXLO] = octets >> 32;
>+ s->regs[R_OCTRXHI] = octets;
>
> /* Error-free Frames received */
>- s->regs[GEM_RXCNT]++;
>+ s->regs[R_RXCNT]++;
>
> /* Error-free Broadcast Frames counter */
> if (!memcmp(packet, broadcast_addr, 6)) {
>- s->regs[GEM_RXBROADCNT]++;
>+ s->regs[R_RXBROADCNT]++;
> }
>
> /* Error-free Multicast Frames counter */
> if (packet[0] == 0x01) {
>- s->regs[GEM_RXMULTICNT]++;
>+ s->regs[R_RXMULTICNT]++;
> }
>
> if (bytes <= 64) {
>- s->regs[GEM_RX64CNT]++;
>+ s->regs[R_RX64CNT]++;
> } else if (bytes <= 127) {
>- s->regs[GEM_RX65CNT]++;
>+ s->regs[R_RX65CNT]++;
> } else if (bytes <= 255) {
>- s->regs[GEM_RX128CNT]++;
>+ s->regs[R_RX128CNT]++;
> } else if (bytes <= 511) {
>- s->regs[GEM_RX256CNT]++;
>+ s->regs[R_RX256CNT]++;
> } else if (bytes <= 1023) {
>- s->regs[GEM_RX512CNT]++;
>+ s->regs[R_RX512CNT]++;
> } else if (bytes <= 1518) {
>- s->regs[GEM_RX1024CNT]++;
>+ s->regs[R_RX1024CNT]++;
> } else {
>- s->regs[GEM_RX1519CNT]++;
>+ s->regs[R_RX1519CNT]++;
> }
> }
>
> /*
> * Get the MAC Address bit from the specified position @@ -704,39 +700,39
>@@ static int gem_mac_address_filter(CadenceGEMState *s, const uint8_t
>*packet) {
> uint8_t *gem_spaddr;
> int i, is_mc;
>
> /* Promiscuous mode? */
>- if (s->regs[GEM_NWCFG] & GEM_NWCFG_PROMISC) {
>+ if (s->regs[R_NWCFG] & GEM_NWCFG_PROMISC) {
> return GEM_RX_PROMISCUOUS_ACCEPT;
> }
>
> if (!memcmp(packet, broadcast_addr, 6)) {
> /* Reject broadcast packets? */
>- if (s->regs[GEM_NWCFG] & GEM_NWCFG_BCAST_REJ) {
>+ if (s->regs[R_NWCFG] & GEM_NWCFG_BCAST_REJ) {
> return GEM_RX_REJECT;
> }
> return GEM_RX_BROADCAST_ACCEPT;
> }
>
> /* Accept packets -w- hash match? */
> is_mc = is_multicast_ether_addr(packet);
>- if ((is_mc && (s->regs[GEM_NWCFG] & GEM_NWCFG_MCAST_HASH)) ||
>- (!is_mc && (s->regs[GEM_NWCFG] & GEM_NWCFG_UCAST_HASH))) {
>+ if ((is_mc && (s->regs[R_NWCFG] & GEM_NWCFG_MCAST_HASH)) ||
>+ (!is_mc && (s->regs[R_NWCFG] & GEM_NWCFG_UCAST_HASH))) {
> uint64_t buckets;
> unsigned hash_index;
>
> hash_index = calc_mac_hash(packet);
>- buckets = ((uint64_t)s->regs[GEM_HASHHI] << 32) | s-
>>regs[GEM_HASHLO];
>+ buckets = ((uint64_t)s->regs[R_HASHHI] << 32) |
>+ s->regs[R_HASHLO];
> if ((buckets >> hash_index) & 1) {
> return is_mc ? GEM_RX_MULTICAST_HASH_ACCEPT
> : GEM_RX_UNICAST_HASH_ACCEPT;
> }
> }
>
> /* Check all 4 specific addresses */
>- gem_spaddr = (uint8_t *)&(s->regs[GEM_SPADDR1LO]);
>+ gem_spaddr = (uint8_t *)&(s->regs[R_SPADDR1LO]);
> for (i = 3; i >= 0; i--) {
> if (s->sar_active[i] && !memcmp(packet, gem_spaddr + 8 * i, 6)) {
> return GEM_RX_SAR_ACCEPT + i;
> }
> }
>@@ -752,11 +748,11 @@ static int
>get_queue_from_screen(CadenceGEMState *s, uint8_t *rxbuf_ptr,
> uint32_t reg;
> bool matched, mismatched;
> int i, j;
>
> for (i = 0; i < s->num_type1_screeners; i++) {
>- reg = s->regs[GEM_SCREENING_TYPE1_REGISTER_0 + i];
>+ reg = s->regs[R_SCREENING_TYPE1_REG0 + i];
> matched = false;
> mismatched = false;
>
> /* Screening is based on UDP Port */
> if (reg & GEM_ST1R_UDP_PORT_MATCH_ENABLE) { @@ -784,11 +780,11
>@@ static int get_queue_from_screen(CadenceGEMState *s, uint8_t
>*rxbuf_ptr,
> return extract32(reg, GEM_ST1R_QUEUE_SHIFT,
>GEM_ST1R_QUEUE_WIDTH);
> }
> }
>
> for (i = 0; i < s->num_type2_screeners; i++) {
>- reg = s->regs[GEM_SCREENING_TYPE2_REGISTER_0 + i];
>+ reg = s->regs[R_SCREENING_TYPE2_REG0 + i];
> matched = false;
> mismatched = false;
>
> if (reg & GEM_ST2R_ETHERTYPE_ENABLE) {
> uint16_t type = rxbuf_ptr[12] << 8 | rxbuf_ptr[13]; @@ -797,11
>+793,11 @@ static int get_queue_from_screen(CadenceGEMState *s, uint8_t
>*rxbuf_ptr,
>
> if (et_idx > s->num_type2_screeners) {
> qemu_log_mask(LOG_GUEST_ERROR, "Out of range ethertype "
> "register index: %d\n", et_idx);
> }
>- if (type == s->regs[GEM_SCREENING_TYPE2_ETHERTYPE_REG_0 +
>+ if (type == s->regs[R_SCREENING_TYPE2_ETHERTYPE_REG0 +
> et_idx]) {
> matched = true;
> } else {
> mismatched = true;
> }
>@@ -821,12 +817,12 @@ static int
>get_queue_from_screen(CadenceGEMState *s, uint8_t *rxbuf_ptr,
> if (cr_idx > s->num_type2_screeners) {
> qemu_log_mask(LOG_GUEST_ERROR, "Out of range compare "
> "register index: %d\n", cr_idx);
> }
>
>- cr0 = s->regs[GEM_TYPE2_COMPARE_0_WORD_0 + cr_idx * 2];
>- cr1 = s->regs[GEM_TYPE2_COMPARE_0_WORD_0 + cr_idx * 2 + 1];
>+ cr0 = s->regs[R_TYPE2_COMPARE_0_WORD_0 + cr_idx * 2];
>+ cr1 = s->regs[R_TYPE2_COMPARE_0_WORD_0 + cr_idx * 2 + 1];
> offset = extract32(cr1, GEM_T2CW1_OFFSET_VALUE_SHIFT,
> GEM_T2CW1_OFFSET_VALUE_WIDTH);
>
> switch (extract32(cr1, GEM_T2CW1_COMPARE_OFFSET_SHIFT,
> GEM_T2CW1_COMPARE_OFFSET_WIDTH)) { @@ -869,15
>+865,15 @@ static uint32_t gem_get_queue_base_addr(CadenceGEMState *s,
>bool tx, int q) {
> uint32_t base_addr = 0;
>
> switch (q) {
> case 0:
>- base_addr = s->regs[tx ? GEM_TXQBASE : GEM_RXQBASE];
>+ base_addr = s->regs[tx ? R_TXQBASE : R_RXQBASE];
> break;
> case 1 ... (MAX_PRIORITY_QUEUES - 1):
>- base_addr = s->regs[(tx ? GEM_TRANSMIT_Q1_PTR :
>- GEM_RECEIVE_Q1_PTR) + q - 1];
>+ base_addr = s->regs[(tx ? R_TRANSMIT_Q1_PTR :
>+ R_RECEIVE_Q1_PTR) + q - 1];
> break;
> default:
> g_assert_not_reached();
> };
>
>@@ -896,12 +892,12 @@ static inline uint32_t
>gem_get_rx_queue_base_addr(CadenceGEMState *s, int q)
>
> static hwaddr gem_get_desc_addr(CadenceGEMState *s, bool tx, int q) {
> hwaddr desc_addr = 0;
>
>- if (s->regs[GEM_DMACFG] & GEM_DMACFG_ADDR_64B) {
>- desc_addr = s->regs[tx ? GEM_TBQPH : GEM_RBQPH];
>+ if (s->regs[R_DMACFG] & GEM_DMACFG_ADDR_64B) {
>+ desc_addr = s->regs[tx ? R_TBQPH : R_RBQPH];
> }
> desc_addr <<= 32;
> desc_addr |= tx ? s->tx_desc_addr[q] : s->rx_desc_addr[q];
> return desc_addr;
> }
>@@ -928,11 +924,11 @@ static void gem_get_rx_desc(CadenceGEMState *s,
>int q)
> sizeof(uint32_t) * gem_get_desc_len(s, true));
>
> /* Descriptor owned by software ? */
> if (rx_desc_get_ownership(s->rx_desc[q]) == 1) {
> DB_PRINT("descriptor 0x%" HWADDR_PRIx " owned by sw.\n",
>desc_addr);
>- s->regs[GEM_RXSTATUS] |= GEM_RXSTATUS_NOBUF;
>+ s->regs[R_RXSTATUS] |= GEM_RXSTATUS_NOBUF;
> gem_set_isr(s, q, GEM_INT_RXUSED);
> /* Handle interrupt consequences */
> gem_update_int_status(s);
> }
> }
>@@ -956,11 +952,11 @@ static ssize_t gem_receive(NetClientState *nc, const
>uint8_t *buf, size_t size)
> if (maf == GEM_RX_REJECT) {
> return size; /* no, drop silently b/c it's not an error */
> }
>
> /* Discard packets with receive length error enabled ? */
>- if (s->regs[GEM_NWCFG] & GEM_NWCFG_LERR_DISC) {
>+ if (s->regs[R_NWCFG] & GEM_NWCFG_LERR_DISC) {
> unsigned type_len;
>
> /* Fish the ethertype / length field out of the RX packet */
> type_len = buf[12] << 8 | buf[13];
> /* It is a length field, not an ethertype */ @@ -973,17 +969,17 @@ static
>ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size)
> }
>
> /*
> * Determine configured receive buffer offset (probably 0)
> */
>- rxbuf_offset = (s->regs[GEM_NWCFG] & GEM_NWCFG_BUFF_OFST_M) >>
>+ rxbuf_offset = (s->regs[R_NWCFG] & GEM_NWCFG_BUFF_OFST_M) >>
> GEM_NWCFG_BUFF_OFST_S;
>
> /* The configure size of each receive buffer. Determines how many
> * buffers needed to hold this packet.
> */
>- rxbufsize = ((s->regs[GEM_DMACFG] & GEM_DMACFG_RBUFSZ_M) >>
>+ rxbufsize = ((s->regs[R_DMACFG] & GEM_DMACFG_RBUFSZ_M) >>
> GEM_DMACFG_RBUFSZ_S) * GEM_DMACFG_RBUFSZ_MUL;
> bytes_to_copy = size;
>
> /* Hardware allows a zero value here but warns against it. To avoid QEMU
> * indefinite loops we enforce a minimum value here @@ -999,11 +995,11
>@@ static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t
>size)
> if (size < 60) {
> size = 60;
> }
>
> /* Strip of FCS field ? (usually yes) */
>- if (s->regs[GEM_NWCFG] & GEM_NWCFG_STRIP_FCS) {
>+ if (s->regs[R_NWCFG] & GEM_NWCFG_STRIP_FCS) {
> rxbuf_ptr = (void *)buf;
> } else {
> unsigned crc_val;
>
> if (size > MAX_FRAME_SIZE - sizeof(crc_val)) { @@ -1105,11 +1101,11
>@@ static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t
>size)
> }
>
> /* Count it */
> gem_receive_updatestats(s, buf, size);
>
>- s->regs[GEM_RXSTATUS] |= GEM_RXSTATUS_FRMRCVD;
>+ s->regs[R_RXSTATUS] |= GEM_RXSTATUS_FRMRCVD;
> gem_set_isr(s, q, GEM_INT_RXCMPL);
>
> /* Handle interrupt consequences */
> gem_update_int_status(s);
>
>@@ -1124,43 +1120,43 @@ static void
>gem_transmit_updatestats(CadenceGEMState *s, const uint8_t *packet,
> unsigned bytes) {
> uint64_t octets;
>
> /* Total octets (bytes) transmitted */
>- octets = ((uint64_t)(s->regs[GEM_OCTTXLO]) << 32) |
>- s->regs[GEM_OCTTXHI];
>+ octets = ((uint64_t)(s->regs[R_OCTTXLO]) << 32) |
>+ s->regs[R_OCTTXHI];
> octets += bytes;
>- s->regs[GEM_OCTTXLO] = octets >> 32;
>- s->regs[GEM_OCTTXHI] = octets;
>+ s->regs[R_OCTTXLO] = octets >> 32;
>+ s->regs[R_OCTTXHI] = octets;
>
> /* Error-free Frames transmitted */
>- s->regs[GEM_TXCNT]++;
>+ s->regs[R_TXCNT]++;
>
> /* Error-free Broadcast Frames counter */
> if (!memcmp(packet, broadcast_addr, 6)) {
>- s->regs[GEM_TXBCNT]++;
>+ s->regs[R_TXBCNT]++;
> }
>
> /* Error-free Multicast Frames counter */
> if (packet[0] == 0x01) {
>- s->regs[GEM_TXMCNT]++;
>+ s->regs[R_TXMCNT]++;
> }
>
> if (bytes <= 64) {
>- s->regs[GEM_TX64CNT]++;
>+ s->regs[R_TX64CNT]++;
> } else if (bytes <= 127) {
>- s->regs[GEM_TX65CNT]++;
>+ s->regs[R_TX65CNT]++;
> } else if (bytes <= 255) {
>- s->regs[GEM_TX128CNT]++;
>+ s->regs[R_TX128CNT]++;
> } else if (bytes <= 511) {
>- s->regs[GEM_TX256CNT]++;
>+ s->regs[R_TX256CNT]++;
> } else if (bytes <= 1023) {
>- s->regs[GEM_TX512CNT]++;
>+ s->regs[R_TX512CNT]++;
> } else if (bytes <= 1518) {
>- s->regs[GEM_TX1024CNT]++;
>+ s->regs[R_TX1024CNT]++;
> } else {
>- s->regs[GEM_TX1519CNT]++;
>+ s->regs[R_TX1519CNT]++;
> }
> }
>
> /*
> * gem_transmit:
>@@ -1173,11 +1169,11 @@ static void gem_transmit(CadenceGEMState *s)
> uint8_t *p;
> unsigned total_bytes;
> int q = 0;
>
> /* Do nothing if transmit is not enabled. */
>- if (!(s->regs[GEM_NWCTRL] & GEM_NWCTRL_TXENA)) {
>+ if (!(s->regs[R_NWCTRL] & GEM_NWCTRL_TXENA)) {
> return;
> }
>
> DB_PRINT("\n");
>
>@@ -1198,11 +1194,11 @@ static void gem_transmit(CadenceGEMState *s)
> sizeof(uint32_t) * gem_get_desc_len(s, false));
> /* Handle all descriptors owned by hardware */
> while (tx_desc_get_used(desc) == 0) {
>
> /* Do nothing if transmit is not enabled. */
>- if (!(s->regs[GEM_NWCTRL] & GEM_NWCTRL_TXENA)) {
>+ if (!(s->regs[R_NWCTRL] & GEM_NWCTRL_TXENA)) {
> return;
> }
> print_gem_tx_desc(desc, q);
>
> /* The real hardware would eat this (and possibly crash).
>@@ -1256,26 +1252,26 @@ static void gem_transmit(CadenceGEMState *s)
> s->tx_desc_addr[q] = packet_desc_addr +
> 4 * gem_get_desc_len(s, false);
> }
> DB_PRINT("TX descriptor next: 0x%08x\n", s->tx_desc_addr[q]);
>
>- s->regs[GEM_TXSTATUS] |= GEM_TXSTATUS_TXCMPL;
>+ s->regs[R_TXSTATUS] |= GEM_TXSTATUS_TXCMPL;
> gem_set_isr(s, q, GEM_INT_TXCMPL);
>
> /* Handle interrupt consequences */
> gem_update_int_status(s);
>
> /* Is checksum offload enabled? */
>- if (s->regs[GEM_DMACFG] & GEM_DMACFG_TXCSUM_OFFL) {
>+ if (s->regs[R_DMACFG] & GEM_DMACFG_TXCSUM_OFFL) {
> net_checksum_calculate(s->tx_packet, total_bytes, CSUM_ALL);
> }
>
> /* Update MAC statistics */
> gem_transmit_updatestats(s, s->tx_packet, total_bytes);
>
> /* Send the packet somewhere */
>- if (s->phy_loop || (s->regs[GEM_NWCTRL] &
>+ if (s->phy_loop || (s->regs[R_NWCTRL] &
> GEM_NWCTRL_LOCALLOOP)) {
> qemu_receive_packet(qemu_get_queue(s->nic), s->tx_packet,
> total_bytes);
> } else {
> qemu_send_packet(qemu_get_queue(s->nic), s->tx_packet, @@ -
>1287,13 +1283,12 @@ static void gem_transmit(CadenceGEMState *s)
> total_bytes = 0;
> }
>
> /* read next descriptor */
> if (tx_desc_get_wrap(desc)) {
>-
>- if (s->regs[GEM_DMACFG] & GEM_DMACFG_ADDR_64B) {
>- packet_desc_addr = s->regs[GEM_TBQPH];
>+ if (s->regs[R_DMACFG] & GEM_DMACFG_ADDR_64B) {
>+ packet_desc_addr = s->regs[R_TBQPH];
> packet_desc_addr <<= 32;
> } else {
> packet_desc_addr = 0;
> }
> packet_desc_addr |= gem_get_tx_queue_base_addr(s, q); @@ -
>1305,11 +1300,11 @@ static void gem_transmit(CadenceGEMState *s)
> MEMTXATTRS_UNSPECIFIED, desc,
> sizeof(uint32_t) * gem_get_desc_len(s, false));
> }
>
> if (tx_desc_get_used(desc)) {
>- s->regs[GEM_TXSTATUS] |= GEM_TXSTATUS_USED;
>+ s->regs[R_TXSTATUS] |= GEM_TXSTATUS_USED;
> /* IRQ TXUSED is defined only for queue 0 */
> if (q == 0) {
> gem_set_isr(s, 0, GEM_INT_TXUSED);
> }
> gem_update_int_status(s);
>@@ -1351,34 +1346,34 @@ static void gem_reset(DeviceState *d)
>
> DB_PRINT("\n");
>
> /* Set post reset register values */
> memset(&s->regs[0], 0, sizeof(s->regs));
>- s->regs[GEM_NWCFG] = 0x00080000;
>- s->regs[GEM_NWSTATUS] = 0x00000006;
>- s->regs[GEM_DMACFG] = 0x00020784;
>- s->regs[GEM_IMR] = 0x07ffffff;
>- s->regs[GEM_TXPAUSE] = 0x0000ffff;
>- s->regs[GEM_TXPARTIALSF] = 0x000003ff;
>- s->regs[GEM_RXPARTIALSF] = 0x000003ff;
>- s->regs[GEM_MODID] = s->revision;
>- s->regs[GEM_DESCONF] = 0x02D00111;
>- s->regs[GEM_DESCONF2] = 0x2ab10000 | s->jumbo_max_len;
>- s->regs[GEM_DESCONF5] = 0x002f2045;
>- s->regs[GEM_DESCONF6] = GEM_DESCONF6_64B_MASK;
>- s->regs[GEM_INT_Q1_MASK] = 0x00000CE6;
>- s->regs[GEM_JUMBO_MAX_LEN] = s->jumbo_max_len;
>+ s->regs[R_NWCFG] = 0x00080000;
>+ s->regs[R_NWSTATUS] = 0x00000006;
>+ s->regs[R_DMACFG] = 0x00020784;
>+ s->regs[R_IMR] = 0x07ffffff;
>+ s->regs[R_TXPAUSE] = 0x0000ffff;
>+ s->regs[R_TXPARTIALSF] = 0x000003ff;
>+ s->regs[R_RXPARTIALSF] = 0x000003ff;
>+ s->regs[R_MODID] = s->revision;
>+ s->regs[R_DESCONF] = 0x02D00111;
>+ s->regs[R_DESCONF2] = 0x2ab10000 | s->jumbo_max_len;
>+ s->regs[R_DESCONF5] = 0x002f2045;
>+ s->regs[R_DESCONF6] = GEM_DESCONF6_64B_MASK;
>+ s->regs[R_INT_Q1_MASK] = 0x00000CE6;
>+ s->regs[R_JUMBO_MAX_LEN] = s->jumbo_max_len;
>
> if (s->num_priority_queues > 1) {
> queues_mask = MAKE_64BIT_MASK(1, s->num_priority_queues - 1);
>- s->regs[GEM_DESCONF6] |= queues_mask;
>+ s->regs[R_DESCONF6] |= queues_mask;
> }
>
> /* Set MAC address */
> a = &s->conf.macaddr.a[0];
>- s->regs[GEM_SPADDR1LO] = a[0] | (a[1] << 8) | (a[2] << 16) | (a[3] << 24);
>- s->regs[GEM_SPADDR1HI] = a[4] | (a[5] << 8);
>+ s->regs[R_SPADDR1LO] = a[0] | (a[1] << 8) | (a[2] << 16) | (a[3] << 24);
>+ s->regs[R_SPADDR1HI] = a[4] | (a[5] << 8);
>
> for (i = 0; i < 4; i++) {
> s->sar_active[i] = false;
> }
>
>@@ -1435,15 +1430,15 @@ static uint64_t gem_read(void *opaque, hwaddr
>offset, unsigned size)
> retval = s->regs[offset];
>
> DB_PRINT("offset: 0x%04x read: 0x%08x\n", (unsigned)offset*4, retval);
>
> switch (offset) {
>- case GEM_ISR:
>+ case R_ISR:
> DB_PRINT("lowering irqs on ISR read\n");
> /* The interrupts get updated at the end of the function. */
> break;
>- case GEM_PHYMNTNC:
>+ case R_PHYMNTNC:
> if (retval & GEM_PHYMNTNC_OP_R) {
> uint32_t phy_addr, reg_num;
>
> phy_addr = (retval & GEM_PHYMNTNC_ADDR) >>
>GEM_PHYMNTNC_ADDR_SHFT;
> if (phy_addr == s->phy_addr) { @@ -1493,11 +1488,11 @@ static void
>gem_write(void *opaque, hwaddr offset, uint64_t val,
> /* do w1c */
> s->regs[offset] &= ~(s->regs_w1c[offset] & val);
>
> /* Handle register write side effects */
> switch (offset) {
>- case GEM_NWCTRL:
>+ case R_NWCTRL:
> if (val & GEM_NWCTRL_RXENA) {
> for (i = 0; i < s->num_priority_queues; ++i) {
> gem_get_rx_desc(s, i);
> }
> }
>@@ -1513,60 +1508,60 @@ static void gem_write(void *opaque, hwaddr
>offset, uint64_t val,
> if (gem_can_receive(qemu_get_queue(s->nic))) {
> qemu_flush_queued_packets(qemu_get_queue(s->nic));
> }
> break;
>
>- case GEM_TXSTATUS:
>+ case R_TXSTATUS:
> gem_update_int_status(s);
> break;
>- case GEM_RXQBASE:
>+ case R_RXQBASE:
> s->rx_desc_addr[0] = val;
> break;
>- case GEM_RECEIVE_Q1_PTR ... GEM_RECEIVE_Q7_PTR:
>- s->rx_desc_addr[offset - GEM_RECEIVE_Q1_PTR + 1] = val;
>+ case R_RECEIVE_Q1_PTR ... R_RECEIVE_Q7_PTR:
>+ s->rx_desc_addr[offset - R_RECEIVE_Q1_PTR + 1] = val;
> break;
>- case GEM_TXQBASE:
>+ case R_TXQBASE:
> s->tx_desc_addr[0] = val;
> break;
>- case GEM_TRANSMIT_Q1_PTR ... GEM_TRANSMIT_Q7_PTR:
>- s->tx_desc_addr[offset - GEM_TRANSMIT_Q1_PTR + 1] = val;
>+ case R_TRANSMIT_Q1_PTR ... R_TRANSMIT_Q7_PTR:
>+ s->tx_desc_addr[offset - R_TRANSMIT_Q1_PTR + 1] = val;
> break;
>- case GEM_RXSTATUS:
>+ case R_RXSTATUS:
> gem_update_int_status(s);
> break;
>- case GEM_IER:
>- s->regs[GEM_IMR] &= ~val;
>+ case R_IER:
>+ s->regs[R_IMR] &= ~val;
> gem_update_int_status(s);
> break;
>- case GEM_JUMBO_MAX_LEN:
>- s->regs[GEM_JUMBO_MAX_LEN] = val &
>MAX_JUMBO_FRAME_SIZE_MASK;
>+ case R_JUMBO_MAX_LEN:
>+ s->regs[R_JUMBO_MAX_LEN] = val & MAX_JUMBO_FRAME_SIZE_MASK;
> break;
>- case GEM_INT_Q1_ENABLE ... GEM_INT_Q7_ENABLE:
>- s->regs[GEM_INT_Q1_MASK + offset - GEM_INT_Q1_ENABLE] &= ~val;
>+ case R_INT_Q1_ENABLE ... R_INT_Q7_ENABLE:
>+ s->regs[R_INT_Q1_MASK + offset - R_INT_Q1_ENABLE] &= ~val;
> gem_update_int_status(s);
> break;
>- case GEM_IDR:
>- s->regs[GEM_IMR] |= val;
>+ case R_IDR:
>+ s->regs[R_IMR] |= val;
> gem_update_int_status(s);
> break;
>- case GEM_INT_Q1_DISABLE ... GEM_INT_Q7_DISABLE:
>- s->regs[GEM_INT_Q1_MASK + offset - GEM_INT_Q1_DISABLE] |= val;
>+ case R_INT_Q1_DISABLE ... R_INT_Q7_DISABLE:
>+ s->regs[R_INT_Q1_MASK + offset - R_INT_Q1_DISABLE] |= val;
> gem_update_int_status(s);
> break;
>- case GEM_SPADDR1LO:
>- case GEM_SPADDR2LO:
>- case GEM_SPADDR3LO:
>- case GEM_SPADDR4LO:
>- s->sar_active[(offset - GEM_SPADDR1LO) / 2] = false;
>+ case R_SPADDR1LO:
>+ case R_SPADDR2LO:
>+ case R_SPADDR3LO:
>+ case R_SPADDR4LO:
>+ s->sar_active[(offset - R_SPADDR1LO) / 2] = false;
> break;
>- case GEM_SPADDR1HI:
>- case GEM_SPADDR2HI:
>- case GEM_SPADDR3HI:
>- case GEM_SPADDR4HI:
>- s->sar_active[(offset - GEM_SPADDR1HI) / 2] = true;
>+ case R_SPADDR1HI:
>+ case R_SPADDR2HI:
>+ case R_SPADDR3HI:
>+ case R_SPADDR4HI:
>+ s->sar_active[(offset - R_SPADDR1HI) / 2] = true;
> break;
>- case GEM_PHYMNTNC:
>+ case R_PHYMNTNC:
> if (val & GEM_PHYMNTNC_OP_W) {
> uint32_t phy_addr, reg_num;
>
> phy_addr = (val & GEM_PHYMNTNC_ADDR) >>
>GEM_PHYMNTNC_ADDR_SHFT;
> if (phy_addr == s->phy_addr) {
>--
>2.39.2
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 08/11] hw/net/cadence_gem: use FIELD to describe DESCONF6 register fields
2023-10-17 19:44 ` [PATCH 08/11] hw/net/cadence_gem: use FIELD to describe DESCONF6 " Luc Michel
@ 2023-10-18 9:22 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 25+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-10-18 9:22 UTC (permalink / raw)
To: Luc Michel, qemu-devel
Cc: qemu-arm, Edgar E . Iglesias, Alistair Francis, Peter Maydell,
Jason Wang, Francisco Iglesias, Frederic Konrad, Sai Pavan Boddu
On 17/10/23 21:44, Luc Michel wrote:
> Use the FIELD macro to describe the DESCONF6 register fields.
>
> Signed-off-by: Luc Michel <luc.michel@amd.com>
> ---
> hw/net/cadence_gem.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 11/11] hw/net/cadence_gem: enforce 32 bits variable size for CRC
2023-10-17 19:44 ` [PATCH 11/11] hw/net/cadence_gem: enforce 32 bits variable size for CRC Luc Michel
@ 2023-10-18 9:23 ` Philippe Mathieu-Daudé
2023-10-18 10:36 ` Boddu, Sai Pavan
1 sibling, 0 replies; 25+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-10-18 9:23 UTC (permalink / raw)
To: Luc Michel, qemu-devel
Cc: qemu-arm, Edgar E . Iglesias, Alistair Francis, Peter Maydell,
Jason Wang, Francisco Iglesias, Frederic Konrad, Sai Pavan Boddu
On 17/10/23 21:44, Luc Michel wrote:
> The CRC was stored in an unsigned variable in gem_receive. Change it for
> a uint32_t to ensure we have the correct variable size here.
>
Fixes: e9f186e514 ("cadence_gem: initial version of device model")
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> Signed-off-by: Luc Michel <luc.michel@amd.com>
> ---
> hw/net/cadence_gem.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
^ permalink raw reply [flat|nested] 25+ messages in thread
* RE: [PATCH 02/11] hw/net/cadence_gem: use FIELD for screening registers
2023-10-17 19:44 ` [PATCH 02/11] hw/net/cadence_gem: use FIELD for screening registers Luc Michel
@ 2023-10-18 10:14 ` Boddu, Sai Pavan
0 siblings, 0 replies; 25+ messages in thread
From: Boddu, Sai Pavan @ 2023-10-18 10:14 UTC (permalink / raw)
To: Michel, Luc, qemu-devel@nongnu.org
Cc: Michel, Luc, qemu-arm@nongnu.org, Edgar E . Iglesias,
Alistair Francis, Peter Maydell, Jason Wang,
Philippe Mathieu-Daudé, Iglesias, Francisco,
Konrad, Frederic
>-----Original Message-----
>From: Luc Michel <luc.michel@amd.com>
>Sent: Wednesday, October 18, 2023 1:14 AM
>To: qemu-devel@nongnu.org
>Cc: Michel, Luc <Luc.Michel@amd.com>; qemu-arm@nongnu.org; Edgar E .
>Iglesias <edgar.iglesias@gmail.com>; Alistair Francis <alistair@alistair23.me>;
>Peter Maydell <peter.maydell@linaro.org>; Jason Wang
><jasowang@redhat.com>; Philippe Mathieu-Daudé <philmd@linaro.org>;
>Iglesias, Francisco <francisco.iglesias@amd.com>; Konrad, Frederic
><Frederic.Konrad@amd.com>; Boddu, Sai Pavan
><sai.pavan.boddu@amd.com>
>Subject: [PATCH 02/11] hw/net/cadence_gem: use FIELD for screening registers
>
>Describe screening registers fields using the FIELD macros.
>
>Signed-off-by: Luc Michel <luc.michel@amd.com>
Reviewed-by: sai.pavan.boddu@amd.com
Regards,
Sai Pavan
>---
> hw/net/cadence_gem.c | 92 ++++++++++++++++++++++----------------------
> 1 file changed, 47 insertions(+), 45 deletions(-)
>
>diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c index
>0e5744ecd7..f01c81de97 100644
>--- a/hw/net/cadence_gem.c
>+++ b/hw/net/cadence_gem.c
>@@ -168,39 +168,42 @@ REG32(INT_Q7_ENABLE, 0x618)
>
> REG32(INT_Q1_DISABLE, 0x620)
> REG32(INT_Q7_DISABLE, 0x638)
>
> REG32(SCREENING_TYPE1_REG0, 0x500)
>-
>-#define GEM_ST1R_UDP_PORT_MATCH_ENABLE (1 << 29)
>-#define GEM_ST1R_DSTC_ENABLE (1 << 28)
>-#define GEM_ST1R_UDP_PORT_MATCH_SHIFT (12)
>-#define GEM_ST1R_UDP_PORT_MATCH_WIDTH (27 -
>GEM_ST1R_UDP_PORT_MATCH_SHIFT + 1)
>-#define GEM_ST1R_DSTC_MATCH_SHIFT (4)
>-#define GEM_ST1R_DSTC_MATCH_WIDTH (11 -
>GEM_ST1R_DSTC_MATCH_SHIFT + 1)
>-#define GEM_ST1R_QUEUE_SHIFT (0)
>-#define GEM_ST1R_QUEUE_WIDTH (3 - GEM_ST1R_QUEUE_SHIFT + 1)
>+ FIELD(SCREENING_TYPE1_REG0, QUEUE_NUM, 0, 4)
>+ FIELD(SCREENING_TYPE1_REG0, DSTC_MATCH, 4, 8)
>+ FIELD(SCREENING_TYPE1_REG0, UDP_PORT_MATCH, 12, 16)
>+ FIELD(SCREENING_TYPE1_REG0, DSTC_ENABLE, 28, 1)
>+ FIELD(SCREENING_TYPE1_REG0, UDP_PORT_MATCH_EN, 29, 1)
>+ FIELD(SCREENING_TYPE1_REG0, DROP_ON_MATCH, 30, 1)
>
> REG32(SCREENING_TYPE2_REG0, 0x540)
>-
>-#define GEM_ST2R_COMPARE_A_ENABLE (1 << 18)
>-#define GEM_ST2R_COMPARE_A_SHIFT (13)
>-#define GEM_ST2R_COMPARE_WIDTH (17 -
>GEM_ST2R_COMPARE_A_SHIFT + 1)
>-#define GEM_ST2R_ETHERTYPE_ENABLE (1 << 12)
>-#define GEM_ST2R_ETHERTYPE_INDEX_SHIFT (9) -#define
>GEM_ST2R_ETHERTYPE_INDEX_WIDTH (11 -
>GEM_ST2R_ETHERTYPE_INDEX_SHIFT \
>- + 1)
>-#define GEM_ST2R_QUEUE_SHIFT (0)
>-#define GEM_ST2R_QUEUE_WIDTH (3 - GEM_ST2R_QUEUE_SHIFT + 1)
>+ FIELD(SCREENING_TYPE2_REG0, QUEUE_NUM, 0, 4)
>+ FIELD(SCREENING_TYPE2_REG0, VLAN_PRIORITY, 4, 3)
>+ FIELD(SCREENING_TYPE2_REG0, VLAN_ENABLE, 8, 1)
>+ FIELD(SCREENING_TYPE2_REG0, ETHERTYPE_REG_INDEX, 9, 3)
>+ FIELD(SCREENING_TYPE2_REG0, ETHERTYPE_ENABLE, 12, 1)
>+ FIELD(SCREENING_TYPE2_REG0, COMPARE_A, 13, 5)
>+ FIELD(SCREENING_TYPE2_REG0, COMPARE_A_ENABLE, 18, 1)
>+ FIELD(SCREENING_TYPE2_REG0, COMPARE_B, 19, 5)
>+ FIELD(SCREENING_TYPE2_REG0, COMPARE_B_ENABLE, 24, 1)
>+ FIELD(SCREENING_TYPE2_REG0, COMPARE_C, 25, 5)
>+ FIELD(SCREENING_TYPE2_REG0, COMPARE_C_ENABLE, 30, 1)
>+ FIELD(SCREENING_TYPE2_REG0, DROP_ON_MATCH, 31, 1)
>
> REG32(SCREENING_TYPE2_ETHERTYPE_REG0, 0x6e0)
>+
> REG32(TYPE2_COMPARE_0_WORD_0, 0x700)
>+ FIELD(TYPE2_COMPARE_0_WORD_0, MASK_VALUE, 0, 16)
>+ FIELD(TYPE2_COMPARE_0_WORD_0, COMPARE_VALUE, 16, 16)
>
>-#define GEM_T2CW1_COMPARE_OFFSET_SHIFT (7) -#define
>GEM_T2CW1_COMPARE_OFFSET_WIDTH (8 -
>GEM_T2CW1_COMPARE_OFFSET_SHIFT + 1)
>-#define GEM_T2CW1_OFFSET_VALUE_SHIFT (0)
>-#define GEM_T2CW1_OFFSET_VALUE_WIDTH (6 -
>GEM_T2CW1_OFFSET_VALUE_SHIFT + 1)
>+REG32(TYPE2_COMPARE_0_WORD_1, 0x704)
>+ FIELD(TYPE2_COMPARE_0_WORD_1, OFFSET_VALUE, 0, 7)
>+ FIELD(TYPE2_COMPARE_0_WORD_1, COMPARE_OFFSET, 7, 2)
>+ FIELD(TYPE2_COMPARE_0_WORD_1, DISABLE_MASK, 9, 1)
>+ FIELD(TYPE2_COMPARE_0_WORD_1, COMPARE_VLAN_ID, 10, 1)
>
> /*****************************************/
> #define GEM_NWCTRL_TXSTART 0x00000200 /* Transmit Enable */
> #define GEM_NWCTRL_TXENA 0x00000008 /* Transmit Enable */
> #define GEM_NWCTRL_RXENA 0x00000004 /* Receive Enable */
>@@ -753,45 +756,43 @@ static int
>get_queue_from_screen(CadenceGEMState *s, uint8_t *rxbuf_ptr,
> reg = s->regs[R_SCREENING_TYPE1_REG0 + i];
> matched = false;
> mismatched = false;
>
> /* Screening is based on UDP Port */
>- if (reg & GEM_ST1R_UDP_PORT_MATCH_ENABLE) {
>+ if (FIELD_EX32(reg, SCREENING_TYPE1_REG0, UDP_PORT_MATCH_EN)) {
> uint16_t udp_port = rxbuf_ptr[14 + 22] << 8 | rxbuf_ptr[14 + 23];
>- if (udp_port == extract32(reg, GEM_ST1R_UDP_PORT_MATCH_SHIFT,
>- GEM_ST1R_UDP_PORT_MATCH_WIDTH)) {
>+ if (udp_port == FIELD_EX32(reg, SCREENING_TYPE1_REG0,
>+ UDP_PORT_MATCH)) {
> matched = true;
> } else {
> mismatched = true;
> }
> }
>
> /* Screening is based on DS/TC */
>- if (reg & GEM_ST1R_DSTC_ENABLE) {
>+ if (FIELD_EX32(reg, SCREENING_TYPE1_REG0, DSTC_ENABLE)) {
> uint8_t dscp = rxbuf_ptr[14 + 1];
>- if (dscp == extract32(reg, GEM_ST1R_DSTC_MATCH_SHIFT,
>- GEM_ST1R_DSTC_MATCH_WIDTH)) {
>+ if (dscp == FIELD_EX32(reg, SCREENING_TYPE1_REG0,
>+ DSTC_MATCH)) {
> matched = true;
> } else {
> mismatched = true;
> }
> }
>
> if (matched && !mismatched) {
>- return extract32(reg, GEM_ST1R_QUEUE_SHIFT,
>GEM_ST1R_QUEUE_WIDTH);
>+ return FIELD_EX32(reg, SCREENING_TYPE1_REG0, QUEUE_NUM);
> }
> }
>
> for (i = 0; i < s->num_type2_screeners; i++) {
> reg = s->regs[R_SCREENING_TYPE2_REG0 + i];
> matched = false;
> mismatched = false;
>
>- if (reg & GEM_ST2R_ETHERTYPE_ENABLE) {
>+ if (FIELD_EX32(reg, SCREENING_TYPE2_REG0, ETHERTYPE_ENABLE)) {
> uint16_t type = rxbuf_ptr[12] << 8 | rxbuf_ptr[13];
>- int et_idx = extract32(reg, GEM_ST2R_ETHERTYPE_INDEX_SHIFT,
>- GEM_ST2R_ETHERTYPE_INDEX_WIDTH);
>+ int et_idx = FIELD_EX32(reg, SCREENING_TYPE2_REG0,
>+ ETHERTYPE_REG_INDEX);
>
> if (et_idx > s->num_type2_screeners) {
> qemu_log_mask(LOG_GUEST_ERROR, "Out of range ethertype "
> "register index: %d\n", et_idx);
> }
>@@ -803,31 +804,31 @@ static int
>get_queue_from_screen(CadenceGEMState *s, uint8_t *rxbuf_ptr,
> }
> }
>
> /* Compare A, B, C */
> for (j = 0; j < 3; j++) {
>- uint32_t cr0, cr1, mask;
>+ uint32_t cr0, cr1, mask, compare;
> uint16_t rx_cmp;
> int offset;
>- int cr_idx = extract32(reg, GEM_ST2R_COMPARE_A_SHIFT + j * 6,
>- GEM_ST2R_COMPARE_WIDTH);
>+ int cr_idx = extract32(reg,
>R_SCREENING_TYPE2_REG0_COMPARE_A_SHIFT + j * 6,
>+
>+ R_SCREENING_TYPE2_REG0_COMPARE_A_LENGTH);
>
>- if (!(reg & (GEM_ST2R_COMPARE_A_ENABLE << (j * 6)))) {
>+ if (!extract32(reg,
>R_SCREENING_TYPE2_REG0_COMPARE_A_ENABLE_SHIFT + j * 6,
>+
>+ R_SCREENING_TYPE2_REG0_COMPARE_A_ENABLE_LENGTH)) {
> continue;
> }
>+
> if (cr_idx > s->num_type2_screeners) {
> qemu_log_mask(LOG_GUEST_ERROR, "Out of range compare "
> "register index: %d\n", cr_idx);
> }
>
> cr0 = s->regs[R_TYPE2_COMPARE_0_WORD_0 + cr_idx * 2];
>- cr1 = s->regs[R_TYPE2_COMPARE_0_WORD_0 + cr_idx * 2 + 1];
>- offset = extract32(cr1, GEM_T2CW1_OFFSET_VALUE_SHIFT,
>- GEM_T2CW1_OFFSET_VALUE_WIDTH);
>+ cr1 = s->regs[R_TYPE2_COMPARE_0_WORD_1 + cr_idx * 2];
>+ offset = FIELD_EX32(cr1, TYPE2_COMPARE_0_WORD_1,
>+ OFFSET_VALUE);
>
>- switch (extract32(cr1, GEM_T2CW1_COMPARE_OFFSET_SHIFT,
>- GEM_T2CW1_COMPARE_OFFSET_WIDTH)) {
>+ switch (FIELD_EX32(cr1, TYPE2_COMPARE_0_WORD_1,
>+ COMPARE_OFFSET)) {
> case 3: /* Skip UDP header */
> qemu_log_mask(LOG_UNIMP, "TCP compare offsets"
> "unimplemented - assuming UDP\n");
> offset += 8;
> /* Fallthrough */
>@@ -841,21 +842,22 @@ static int
>get_queue_from_screen(CadenceGEMState *s, uint8_t *rxbuf_ptr,
> /* Offset from start of frame */
> break;
> }
>
> rx_cmp = rxbuf_ptr[offset] << 8 | rxbuf_ptr[offset];
>- mask = extract32(cr0, 0, 16);
>+ mask = FIELD_EX32(cr0, TYPE2_COMPARE_0_WORD_0, MASK_VALUE);
>+ compare = FIELD_EX32(cr0, TYPE2_COMPARE_0_WORD_0,
>+ COMPARE_VALUE);
>
>- if ((rx_cmp & mask) == (extract32(cr0, 16, 16) & mask)) {
>+ if ((rx_cmp & mask) == (compare & mask)) {
> matched = true;
> } else {
> mismatched = true;
> }
> }
>
> if (matched && !mismatched) {
>- return extract32(reg, GEM_ST2R_QUEUE_SHIFT,
>GEM_ST2R_QUEUE_WIDTH);
>+ return FIELD_EX32(reg, SCREENING_TYPE2_REG0, QUEUE_NUM);
> }
> }
>
> /* We made it here, assume it's queue 0 */
> return 0;
>--
>2.39.2
^ permalink raw reply [flat|nested] 25+ messages in thread
* RE: [PATCH 03/11] hw/net/cadence_gem: use FIELD to describe NWCTRL register fields
2023-10-17 19:44 ` [PATCH 03/11] hw/net/cadence_gem: use FIELD to describe NWCTRL register fields Luc Michel
@ 2023-10-18 10:15 ` Boddu, Sai Pavan
0 siblings, 0 replies; 25+ messages in thread
From: Boddu, Sai Pavan @ 2023-10-18 10:15 UTC (permalink / raw)
To: Michel, Luc, qemu-devel@nongnu.org
Cc: Michel, Luc, qemu-arm@nongnu.org, Edgar E . Iglesias,
Alistair Francis, Peter Maydell, Jason Wang,
Philippe Mathieu-Daudé, Iglesias, Francisco,
Konrad, Frederic
>-----Original Message-----
>From: Luc Michel <luc.michel@amd.com>
>Sent: Wednesday, October 18, 2023 1:14 AM
>To: qemu-devel@nongnu.org
>Cc: Michel, Luc <Luc.Michel@amd.com>; qemu-arm@nongnu.org; Edgar E .
>Iglesias <edgar.iglesias@gmail.com>; Alistair Francis <alistair@alistair23.me>;
>Peter Maydell <peter.maydell@linaro.org>; Jason Wang
><jasowang@redhat.com>; Philippe Mathieu-Daudé <philmd@linaro.org>;
>Iglesias, Francisco <francisco.iglesias@amd.com>; Konrad, Frederic
><Frederic.Konrad@amd.com>; Boddu, Sai Pavan
><sai.pavan.boddu@amd.com>
>Subject: [PATCH 03/11] hw/net/cadence_gem: use FIELD to describe NWCTRL
>register fields
>
>Use the FIELD macro to describe the NWCTRL register fields.
>
>Signed-off-by: Luc Michel <luc.michel@amd.com>
Reviewed-by: sai.pavan.boddu@amd.com
Regards,
Sai Pavan
>---
> hw/net/cadence_gem.c | 53 +++++++++++++++++++++++++++++++++-------
>----
> 1 file changed, 40 insertions(+), 13 deletions(-)
>
>diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c index
>f01c81de97..2864f0940e 100644
>--- a/hw/net/cadence_gem.c
>+++ b/hw/net/cadence_gem.c
>@@ -44,10 +44,42 @@
> qemu_log(__VA_ARGS__); \
> } \
> } while (0)
>
> REG32(NWCTRL, 0x0) /* Network Control reg */
>+ FIELD(NWCTRL, LOOPBACK , 0, 1)
>+ FIELD(NWCTRL, LOOPBACK_LOCAL , 1, 1)
>+ FIELD(NWCTRL, ENABLE_RECEIVE, 2, 1)
>+ FIELD(NWCTRL, ENABLE_TRANSMIT, 3, 1)
>+ FIELD(NWCTRL, MAN_PORT_EN , 4, 1)
>+ FIELD(NWCTRL, CLEAR_ALL_STATS_REGS , 5, 1)
>+ FIELD(NWCTRL, INC_ALL_STATS_REGS, 6, 1)
>+ FIELD(NWCTRL, STATS_WRITE_EN, 7, 1)
>+ FIELD(NWCTRL, BACK_PRESSURE, 8, 1)
>+ FIELD(NWCTRL, TRANSMIT_START , 9, 1)
>+ FIELD(NWCTRL, TRANSMIT_HALT, 10, 1)
>+ FIELD(NWCTRL, TX_PAUSE_FRAME_RE, 11, 1)
>+ FIELD(NWCTRL, TX_PAUSE_FRAME_ZE, 12, 1)
>+ FIELD(NWCTRL, STATS_TAKE_SNAP, 13, 1)
>+ FIELD(NWCTRL, STATS_READ_SNAP, 14, 1)
>+ FIELD(NWCTRL, STORE_RX_TS, 15, 1)
>+ FIELD(NWCTRL, PFC_ENABLE, 16, 1)
>+ FIELD(NWCTRL, PFC_PRIO_BASED, 17, 1)
>+ FIELD(NWCTRL, FLUSH_RX_PKT_PCLK , 18, 1)
>+ FIELD(NWCTRL, TX_LPI_EN, 19, 1)
>+ FIELD(NWCTRL, PTP_UNICAST_ENA, 20, 1)
>+ FIELD(NWCTRL, ALT_SGMII_MODE, 21, 1)
>+ FIELD(NWCTRL, STORE_UDP_OFFSET, 22, 1)
>+ FIELD(NWCTRL, EXT_TSU_PORT_EN, 23, 1)
>+ FIELD(NWCTRL, ONE_STEP_SYNC_MO, 24, 1)
>+ FIELD(NWCTRL, PFC_CTRL , 25, 1)
>+ FIELD(NWCTRL, EXT_RXQ_SEL_EN , 26, 1)
>+ FIELD(NWCTRL, OSS_CORRECTION_FIELD, 27, 1)
>+ FIELD(NWCTRL, SEL_MII_ON_RGMII, 28, 1)
>+ FIELD(NWCTRL, TWO_PT_FIVE_GIG, 29, 1)
>+ FIELD(NWCTRL, IFG_EATS_QAV_CREDIT, 30, 1)
>+
> REG32(NWCFG, 0x4) /* Network Config reg */ REG32(NWSTATUS, 0x8) /*
>Network Status reg */ REG32(USERIO, 0xc) /* User IO reg */ REG32(DMACFG,
>0x10) /* DMA Control reg */ REG32(TXSTATUS, 0x14) /* TX Status reg */ @@ -
>202,15 +234,10 @@ REG32(TYPE2_COMPARE_0_WORD_1, 0x704)
> FIELD(TYPE2_COMPARE_0_WORD_1, COMPARE_OFFSET, 7, 2)
> FIELD(TYPE2_COMPARE_0_WORD_1, DISABLE_MASK, 9, 1)
> FIELD(TYPE2_COMPARE_0_WORD_1, COMPARE_VLAN_ID, 10, 1)
>
> /*****************************************/
>-#define GEM_NWCTRL_TXSTART 0x00000200 /* Transmit Enable */
>-#define GEM_NWCTRL_TXENA 0x00000008 /* Transmit Enable */
>-#define GEM_NWCTRL_RXENA 0x00000004 /* Receive Enable */
>-#define GEM_NWCTRL_LOCALLOOP 0x00000002 /* Local Loopback */
>-
> #define GEM_NWCFG_STRIP_FCS 0x00020000 /* Strip FCS field */
> #define GEM_NWCFG_LERR_DISC 0x00010000 /* Discard RX frames with len
>err */
> #define GEM_NWCFG_BUFF_OFST_M 0x0000C000 /* Receive buffer offset
>mask */
> #define GEM_NWCFG_BUFF_OFST_S 14 /* Receive buffer offset shift */
> #define GEM_NWCFG_RCV_1538 0x00000100 /* Receive 1538 bytes frame
>*/
>@@ -558,11 +585,11 @@ static bool gem_can_receive(NetClientState *nc)
> int i;
>
> s = qemu_get_nic_opaque(nc);
>
> /* Do nothing if receive is not enabled. */
>- if (!(s->regs[R_NWCTRL] & GEM_NWCTRL_RXENA)) {
>+ if (!FIELD_EX32(s->regs[R_NWCTRL], NWCTRL, ENABLE_RECEIVE)) {
> if (s->can_rx_state != 1) {
> s->can_rx_state = 1;
> DB_PRINT("can't receive - no enable\n");
> }
> return false;
>@@ -1171,11 +1198,11 @@ static void gem_transmit(CadenceGEMState *s)
> uint8_t *p;
> unsigned total_bytes;
> int q = 0;
>
> /* Do nothing if transmit is not enabled. */
>- if (!(s->regs[R_NWCTRL] & GEM_NWCTRL_TXENA)) {
>+ if (!FIELD_EX32(s->regs[R_NWCTRL], NWCTRL, ENABLE_TRANSMIT)) {
> return;
> }
>
> DB_PRINT("\n");
>
>@@ -1196,11 +1223,11 @@ static void gem_transmit(CadenceGEMState *s)
> sizeof(uint32_t) * gem_get_desc_len(s, false));
> /* Handle all descriptors owned by hardware */
> while (tx_desc_get_used(desc) == 0) {
>
> /* Do nothing if transmit is not enabled. */
>- if (!(s->regs[R_NWCTRL] & GEM_NWCTRL_TXENA)) {
>+ if (!FIELD_EX32(s->regs[R_NWCTRL], NWCTRL,
>+ ENABLE_TRANSMIT)) {
> return;
> }
> print_gem_tx_desc(desc, q);
>
> /* The real hardware would eat this (and possibly crash).
>@@ -1269,12 +1296,12 @@ static void gem_transmit(CadenceGEMState *s)
>
> /* Update MAC statistics */
> gem_transmit_updatestats(s, s->tx_packet, total_bytes);
>
> /* Send the packet somewhere */
>- if (s->phy_loop || (s->regs[R_NWCTRL] &
>- GEM_NWCTRL_LOCALLOOP)) {
>+ if (s->phy_loop || FIELD_EX32(s->regs[R_NWCTRL], NWCTRL,
>+ LOOPBACK_LOCAL)) {
> qemu_receive_packet(qemu_get_queue(s->nic), s->tx_packet,
> total_bytes);
> } else {
> qemu_send_packet(qemu_get_queue(s->nic), s->tx_packet,
> total_bytes); @@ -1491,19 +1518,19 @@ static void
>gem_write(void *opaque, hwaddr offset, uint64_t val,
> s->regs[offset] &= ~(s->regs_w1c[offset] & val);
>
> /* Handle register write side effects */
> switch (offset) {
> case R_NWCTRL:
>- if (val & GEM_NWCTRL_RXENA) {
>+ if (FIELD_EX32(val, NWCTRL, ENABLE_RECEIVE)) {
> for (i = 0; i < s->num_priority_queues; ++i) {
> gem_get_rx_desc(s, i);
> }
> }
>- if (val & GEM_NWCTRL_TXSTART) {
>+ if (FIELD_EX32(val, NWCTRL, TRANSMIT_START)) {
> gem_transmit(s);
> }
>- if (!(val & GEM_NWCTRL_TXENA)) {
>+ if (!(FIELD_EX32(val, NWCTRL, ENABLE_TRANSMIT))) {
> /* Reset to start of Q when transmit disabled. */
> for (i = 0; i < s->num_priority_queues; i++) {
> s->tx_desc_addr[i] = gem_get_tx_queue_base_addr(s, i);
> }
> }
>--
>2.39.2
^ permalink raw reply [flat|nested] 25+ messages in thread
* RE: [PATCH 04/11] hw/net/cadence_gem: use FIELD to describe NWCFG register fields
2023-10-17 19:44 ` [PATCH 04/11] hw/net/cadence_gem: use FIELD to describe NWCFG " Luc Michel
@ 2023-10-18 10:18 ` Boddu, Sai Pavan
0 siblings, 0 replies; 25+ messages in thread
From: Boddu, Sai Pavan @ 2023-10-18 10:18 UTC (permalink / raw)
To: Michel, Luc, qemu-devel@nongnu.org
Cc: Michel, Luc, qemu-arm@nongnu.org, Edgar E . Iglesias,
Alistair Francis, Peter Maydell, Jason Wang,
Philippe Mathieu-Daudé, Iglesias, Francisco,
Konrad, Frederic
>-----Original Message-----
>From: Luc Michel <luc.michel@amd.com>
>Sent: Wednesday, October 18, 2023 1:14 AM
>To: qemu-devel@nongnu.org
>Cc: Michel, Luc <Luc.Michel@amd.com>; qemu-arm@nongnu.org; Edgar E .
>Iglesias <edgar.iglesias@gmail.com>; Alistair Francis <alistair@alistair23.me>;
>Peter Maydell <peter.maydell@linaro.org>; Jason Wang
><jasowang@redhat.com>; Philippe Mathieu-Daudé <philmd@linaro.org>;
>Iglesias, Francisco <francisco.iglesias@amd.com>; Konrad, Frederic
><Frederic.Konrad@amd.com>; Boddu, Sai Pavan
><sai.pavan.boddu@amd.com>
>Subject: [PATCH 04/11] hw/net/cadence_gem: use FIELD to describe NWCFG
>register fields
>
>Use de FIELD macro to describe the NWCFG register fields.
>
>Signed-off-by: Luc Michel <luc.michel@amd.com>
Reviewed-by: sai.pavan.boddu@amd.com
Regards,
Sai Pavan
>---
> hw/net/cadence_gem.c | 60 ++++++++++++++++++++++++++++---------------
>-
> 1 file changed, 39 insertions(+), 21 deletions(-)
>
>diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c index
>2864f0940e..09f570b6fb 100644
>--- a/hw/net/cadence_gem.c
>+++ b/hw/net/cadence_gem.c
>@@ -77,10 +77,39 @@ REG32(NWCTRL, 0x0) /* Network Control reg */
> FIELD(NWCTRL, SEL_MII_ON_RGMII, 28, 1)
> FIELD(NWCTRL, TWO_PT_FIVE_GIG, 29, 1)
> FIELD(NWCTRL, IFG_EATS_QAV_CREDIT, 30, 1)
>
> REG32(NWCFG, 0x4) /* Network Config reg */
>+ FIELD(NWCFG, SPEED, 0, 1)
>+ FIELD(NWCFG, FULL_DUPLEX, 1, 1)
>+ FIELD(NWCFG, DISCARD_NON_VLAN_FRAMES, 2, 1)
>+ FIELD(NWCFG, JUMBO_FRAMES, 3, 1)
>+ FIELD(NWCFG, PROMISC, 4, 1)
>+ FIELD(NWCFG, NO_BROADCAST, 5, 1)
>+ FIELD(NWCFG, MULTICAST_HASH_EN, 6, 1)
>+ FIELD(NWCFG, UNICAST_HASH_EN, 7, 1)
>+ FIELD(NWCFG, RECV_1536_BYTE_FRAMES, 8, 1)
>+ FIELD(NWCFG, EXTERNAL_ADDR_MATCH_EN, 9, 1)
>+ FIELD(NWCFG, GIGABIT_MODE_ENABLE, 10, 1)
>+ FIELD(NWCFG, PCS_SELECT, 11, 1)
>+ FIELD(NWCFG, RETRY_TEST, 12, 1)
>+ FIELD(NWCFG, PAUSE_ENABLE, 13, 1)
>+ FIELD(NWCFG, RECV_BUF_OFFSET, 14, 2)
>+ FIELD(NWCFG, LEN_ERR_DISCARD, 16, 1)
>+ FIELD(NWCFG, FCS_REMOVE, 17, 1)
>+ FIELD(NWCFG, MDC_CLOCK_DIV, 18, 3)
>+ FIELD(NWCFG, DATA_BUS_WIDTH, 21, 2)
>+ FIELD(NWCFG, DISABLE_COPY_PAUSE_FRAMES, 23, 1)
>+ FIELD(NWCFG, RECV_CSUM_OFFLOAD_EN, 24, 1)
>+ FIELD(NWCFG, EN_HALF_DUPLEX_RX, 25, 1)
>+ FIELD(NWCFG, IGNORE_RX_FCS, 26, 1)
>+ FIELD(NWCFG, SGMII_MODE_ENABLE, 27, 1)
>+ FIELD(NWCFG, IPG_STRETCH_ENABLE, 28, 1)
>+ FIELD(NWCFG, NSP_ACCEPT, 29, 1)
>+ FIELD(NWCFG, IGNORE_IPG_RX_ER, 30, 1)
>+ FIELD(NWCFG, UNI_DIRECTION_ENABLE, 31, 1)
>+
> REG32(NWSTATUS, 0x8) /* Network Status reg */ REG32(USERIO, 0xc) /*
>User IO reg */ REG32(DMACFG, 0x10) /* DMA Control reg */
>REG32(TXSTATUS, 0x14) /* TX Status reg */ REG32(RXQBASE, 0x18) /* RX Q
>Base address reg */ @@ -234,21 +263,10 @@
>REG32(TYPE2_COMPARE_0_WORD_1, 0x704)
> FIELD(TYPE2_COMPARE_0_WORD_1, COMPARE_OFFSET, 7, 2)
> FIELD(TYPE2_COMPARE_0_WORD_1, DISABLE_MASK, 9, 1)
> FIELD(TYPE2_COMPARE_0_WORD_1, COMPARE_VLAN_ID, 10, 1)
>
> /*****************************************/
>-#define GEM_NWCFG_STRIP_FCS 0x00020000 /* Strip FCS field */
>-#define GEM_NWCFG_LERR_DISC 0x00010000 /* Discard RX frames with len
>err */
>-#define GEM_NWCFG_BUFF_OFST_M 0x0000C000 /* Receive buffer offset
>mask */
>-#define GEM_NWCFG_BUFF_OFST_S 14 /* Receive buffer offset shift */
>-#define GEM_NWCFG_RCV_1538 0x00000100 /* Receive 1538 bytes frame
>*/
>-#define GEM_NWCFG_UCAST_HASH 0x00000080 /* accept unicast if hash
>match */
>-#define GEM_NWCFG_MCAST_HASH 0x00000040 /* accept multicast if hash
>match */
>-#define GEM_NWCFG_BCAST_REJ 0x00000020 /* Reject broadcast packets
>*/
>-#define GEM_NWCFG_PROMISC 0x00000010 /* Accept all packets */
>-#define GEM_NWCFG_JUMBO_FRAME 0x00000008 /* Jumbo Frames enable
>*/
>-
> #define GEM_DMACFG_ADDR_64B (1U << 30)
> #define GEM_DMACFG_TX_BD_EXT (1U << 29)
> #define GEM_DMACFG_RX_BD_EXT (1U << 28)
> #define GEM_DMACFG_RBUFSZ_M 0x00FF0000 /* DMA RX Buffer Size mask
>*/
> #define GEM_DMACFG_RBUFSZ_S 16 /* DMA RX Buffer Size shift */
>@@ -480,21 +498,22 @@ static inline void rx_desc_set_sar(uint32_t *desc, int
>sar_idx) static const uint8_t broadcast_addr[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
>0xFF };
>
> static uint32_t gem_get_max_buf_len(CadenceGEMState *s, bool tx) {
> uint32_t size;
>- if (s->regs[R_NWCFG] & GEM_NWCFG_JUMBO_FRAME) {
>+ if (FIELD_EX32(s->regs[R_NWCFG], NWCFG, JUMBO_FRAMES)) {
> size = s->regs[R_JUMBO_MAX_LEN];
> if (size > s->jumbo_max_len) {
> size = s->jumbo_max_len;
> qemu_log_mask(LOG_GUEST_ERROR, "GEM_JUMBO_MAX_LEN reg
>cannot be"
> " greater than 0x%" PRIx32 "\n", s->jumbo_max_len);
> }
> } else if (tx) {
> size = 1518;
> } else {
>- size = s->regs[R_NWCFG] & GEM_NWCFG_RCV_1538 ? 1538 : 1518;
>+ size = FIELD_EX32(s->regs[R_NWCFG],
>+ NWCFG, RECV_1536_BYTE_FRAMES) ? 1538 : 1518;
> }
> return size;
> }
>
> static void gem_set_isr(CadenceGEMState *s, int q, uint32_t flag) @@ -730,26
>+749,26 @@ static int gem_mac_address_filter(CadenceGEMState *s, const
>uint8_t *packet) {
> uint8_t *gem_spaddr;
> int i, is_mc;
>
> /* Promiscuous mode? */
>- if (s->regs[R_NWCFG] & GEM_NWCFG_PROMISC) {
>+ if (FIELD_EX32(s->regs[R_NWCFG], NWCFG, PROMISC)) {
> return GEM_RX_PROMISCUOUS_ACCEPT;
> }
>
> if (!memcmp(packet, broadcast_addr, 6)) {
> /* Reject broadcast packets? */
>- if (s->regs[R_NWCFG] & GEM_NWCFG_BCAST_REJ) {
>+ if (FIELD_EX32(s->regs[R_NWCFG], NWCFG, NO_BROADCAST)) {
> return GEM_RX_REJECT;
> }
> return GEM_RX_BROADCAST_ACCEPT;
> }
>
> /* Accept packets -w- hash match? */
> is_mc = is_multicast_ether_addr(packet);
>- if ((is_mc && (s->regs[R_NWCFG] & GEM_NWCFG_MCAST_HASH)) ||
>- (!is_mc && (s->regs[R_NWCFG] & GEM_NWCFG_UCAST_HASH))) {
>+ if ((is_mc && (FIELD_EX32(s->regs[R_NWCFG], NWCFG,
>MULTICAST_HASH_EN))) ||
>+ (!is_mc && FIELD_EX32(s->regs[R_NWCFG], NWCFG,
>+ UNICAST_HASH_EN))) {
> uint64_t buckets;
> unsigned hash_index;
>
> hash_index = calc_mac_hash(packet);
> buckets = ((uint64_t)s->regs[R_HASHHI] << 32) | s->regs[R_HASHLO]; @@
>-981,11 +1000,11 @@ static ssize_t gem_receive(NetClientState *nc, const
>uint8_t *buf, size_t size)
> if (maf == GEM_RX_REJECT) {
> return size; /* no, drop silently b/c it's not an error */
> }
>
> /* Discard packets with receive length error enabled ? */
>- if (s->regs[R_NWCFG] & GEM_NWCFG_LERR_DISC) {
>+ if (FIELD_EX32(s->regs[R_NWCFG], NWCFG, LEN_ERR_DISCARD)) {
> unsigned type_len;
>
> /* Fish the ethertype / length field out of the RX packet */
> type_len = buf[12] << 8 | buf[13];
> /* It is a length field, not an ethertype */ @@ -998,12 +1017,11 @@ static
>ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size)
> }
>
> /*
> * Determine configured receive buffer offset (probably 0)
> */
>- rxbuf_offset = (s->regs[R_NWCFG] & GEM_NWCFG_BUFF_OFST_M) >>
>- GEM_NWCFG_BUFF_OFST_S;
>+ rxbuf_offset = FIELD_EX32(s->regs[R_NWCFG], NWCFG,
>+ RECV_BUF_OFFSET);
>
> /* The configure size of each receive buffer. Determines how many
> * buffers needed to hold this packet.
> */
> rxbufsize = ((s->regs[R_DMACFG] & GEM_DMACFG_RBUFSZ_M) >> @@ -
>1024,11 +1042,11 @@ static ssize_t gem_receive(NetClientState *nc, const
>uint8_t *buf, size_t size)
> if (size < 60) {
> size = 60;
> }
>
> /* Strip of FCS field ? (usually yes) */
>- if (s->regs[R_NWCFG] & GEM_NWCFG_STRIP_FCS) {
>+ if (FIELD_EX32(s->regs[R_NWCFG], NWCFG, FCS_REMOVE)) {
> rxbuf_ptr = (void *)buf;
> } else {
> unsigned crc_val;
>
> if (size > MAX_FRAME_SIZE - sizeof(crc_val)) {
>--
>2.39.2
^ permalink raw reply [flat|nested] 25+ messages in thread
* RE: [PATCH 05/11] hw/net/cadence_gem: use FIELD to describe DMACFG register fields
2023-10-17 19:44 ` [PATCH 05/11] hw/net/cadence_gem: use FIELD to describe DMACFG " Luc Michel
@ 2023-10-18 10:20 ` Boddu, Sai Pavan
0 siblings, 0 replies; 25+ messages in thread
From: Boddu, Sai Pavan @ 2023-10-18 10:20 UTC (permalink / raw)
To: Michel, Luc, qemu-devel@nongnu.org
Cc: Michel, Luc, qemu-arm@nongnu.org, Edgar E . Iglesias,
Alistair Francis, Peter Maydell, Jason Wang,
Philippe Mathieu-Daudé, Iglesias, Francisco,
Konrad, Frederic
>-----Original Message-----
>From: Luc Michel <luc.michel@amd.com>
>Sent: Wednesday, October 18, 2023 1:14 AM
>To: qemu-devel@nongnu.org
>Cc: Michel, Luc <Luc.Michel@amd.com>; qemu-arm@nongnu.org; Edgar E .
>Iglesias <edgar.iglesias@gmail.com>; Alistair Francis <alistair@alistair23.me>;
>Peter Maydell <peter.maydell@linaro.org>; Jason Wang
><jasowang@redhat.com>; Philippe Mathieu-Daudé <philmd@linaro.org>;
>Iglesias, Francisco <francisco.iglesias@amd.com>; Konrad, Frederic
><Frederic.Konrad@amd.com>; Boddu, Sai Pavan
><sai.pavan.boddu@amd.com>
>Subject: [PATCH 05/11] hw/net/cadence_gem: use FIELD to describe DMACFG
>register fields
>
>Use de FIELD macro to describe the DMACFG register fields.
>
>Signed-off-by: Luc Michel <luc.michel@amd.com>
Reviewed-by: sai.pavan.boddu@amd.com
>---
> hw/net/cadence_gem.c | 48 ++++++++++++++++++++++++++++---------------
>-
> 1 file changed, 31 insertions(+), 17 deletions(-)
>
>diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c index
>09f570b6fb..5c386adff2 100644
>--- a/hw/net/cadence_gem.c
>+++ b/hw/net/cadence_gem.c
>@@ -108,11 +108,31 @@ REG32(NWCFG, 0x4) /* Network Config reg */
> FIELD(NWCFG, IGNORE_IPG_RX_ER, 30, 1)
> FIELD(NWCFG, UNI_DIRECTION_ENABLE, 31, 1)
>
> REG32(NWSTATUS, 0x8) /* Network Status reg */ REG32(USERIO, 0xc) /*
>User IO reg */
>+
> REG32(DMACFG, 0x10) /* DMA Control reg */
>+ FIELD(DMACFG, SEND_BCAST_TO_ALL_QS, 31, 1)
>+ FIELD(DMACFG, DMA_ADDR_BUS_WIDTH, 30, 1)
>+ FIELD(DMACFG, TX_BD_EXT_MODE_EN , 29, 1)
>+ FIELD(DMACFG, RX_BD_EXT_MODE_EN , 28, 1)
>+ FIELD(DMACFG, FORCE_MAX_AMBA_BURST_TX, 26, 1)
>+ FIELD(DMACFG, FORCE_MAX_AMBA_BURST_RX, 25, 1)
>+ FIELD(DMACFG, FORCE_DISCARD_ON_ERR, 24, 1)
>+ FIELD(DMACFG, RX_BUF_SIZE, 16, 8)
>+ FIELD(DMACFG, CRC_ERROR_REPORT, 13, 1)
>+ FIELD(DMACFG, INF_LAST_DBUF_SIZE_EN, 12, 1)
>+ FIELD(DMACFG, TX_PBUF_CSUM_OFFLOAD, 11, 1)
>+ FIELD(DMACFG, TX_PBUF_SIZE, 10, 1)
>+ FIELD(DMACFG, RX_PBUF_SIZE, 8, 2)
>+ FIELD(DMACFG, ENDIAN_SWAP_PACKET, 7, 1)
>+ FIELD(DMACFG, ENDIAN_SWAP_MGNT, 6, 1)
>+ FIELD(DMACFG, HDR_DATA_SPLIT_EN, 5, 1)
>+ FIELD(DMACFG, AMBA_BURST_LEN , 0, 5)
>+#define GEM_DMACFG_RBUFSZ_MUL 64 /* DMA RX Buffer Size multiplier
>*/
>+
> REG32(TXSTATUS, 0x14) /* TX Status reg */ REG32(RXQBASE, 0x18) /* RX Q
>Base address reg */ REG32(TXQBASE, 0x1c) /* TX Q Base address reg */
>REG32(RXSTATUS, 0x20) /* RX Status reg */ REG32(ISR, 0x24) /* Interrupt
>Status reg */ @@ -263,17 +283,10 @@ REG32(TYPE2_COMPARE_0_WORD_1,
>0x704)
> FIELD(TYPE2_COMPARE_0_WORD_1, COMPARE_OFFSET, 7, 2)
> FIELD(TYPE2_COMPARE_0_WORD_1, DISABLE_MASK, 9, 1)
> FIELD(TYPE2_COMPARE_0_WORD_1, COMPARE_VLAN_ID, 10, 1)
>
> /*****************************************/
>-#define GEM_DMACFG_ADDR_64B (1U << 30)
>-#define GEM_DMACFG_TX_BD_EXT (1U << 29)
>-#define GEM_DMACFG_RX_BD_EXT (1U << 28)
>-#define GEM_DMACFG_RBUFSZ_M 0x00FF0000 /* DMA RX Buffer Size mask
>*/
>-#define GEM_DMACFG_RBUFSZ_S 16 /* DMA RX Buffer Size shift */
>-#define GEM_DMACFG_RBUFSZ_MUL 64 /* DMA RX Buffer Size multiplier
>*/
>-#define GEM_DMACFG_TXCSUM_OFFL 0x00000800 /* Transmit checksum
>offload */
>
> #define GEM_TXSTATUS_TXCMPL 0x00000020 /* Transmit Complete */
> #define GEM_TXSTATUS_USED 0x00000001 /* sw owned descriptor
>encountered */
>
> #define GEM_RXSTATUS_FRMRCVD 0x00000002 /* Frame received */
>@@ -367,11 +380,11 @@ REG32(TYPE2_COMPARE_0_WORD_1, 0x704)
>
> static inline uint64_t tx_desc_get_buffer(CadenceGEMState *s, uint32_t *desc)
>{
> uint64_t ret = desc[0];
>
>- if (s->regs[R_DMACFG] & GEM_DMACFG_ADDR_64B) {
>+ if (FIELD_EX32(s->regs[R_DMACFG], DMACFG, DMA_ADDR_BUS_WIDTH)) {
> ret |= (uint64_t)desc[2] << 32;
> }
> return ret;
> }
>
>@@ -412,25 +425,25 @@ static inline void print_gem_tx_desc(uint32_t *desc,
>uint8_t queue)
>
> static inline uint64_t rx_desc_get_buffer(CadenceGEMState *s, uint32_t *desc)
>{
> uint64_t ret = desc[0] & ~0x3UL;
>
>- if (s->regs[R_DMACFG] & GEM_DMACFG_ADDR_64B) {
>+ if (FIELD_EX32(s->regs[R_DMACFG], DMACFG, DMA_ADDR_BUS_WIDTH)) {
> ret |= (uint64_t)desc[2] << 32;
> }
> return ret;
> }
>
> static inline int gem_get_desc_len(CadenceGEMState *s, bool rx_n_tx) {
> int ret = 2;
>
>- if (s->regs[R_DMACFG] & GEM_DMACFG_ADDR_64B) {
>+ if (FIELD_EX32(s->regs[R_DMACFG], DMACFG, DMA_ADDR_BUS_WIDTH)) {
> ret += 2;
> }
>- if (s->regs[R_DMACFG] & (rx_n_tx ? GEM_DMACFG_RX_BD_EXT
>- : GEM_DMACFG_TX_BD_EXT)) {
>+ if (s->regs[R_DMACFG] & (rx_n_tx ?
>R_DMACFG_RX_BD_EXT_MODE_EN_MASK
>+ :
>+ R_DMACFG_TX_BD_EXT_MODE_EN_MASK)) {
> ret += 2;
> }
>
> assert(ret <= DESC_MAX_NUM_WORDS);
> return ret;
>@@ -940,11 +953,11 @@ static inline uint32_t
>gem_get_rx_queue_base_addr(CadenceGEMState *s, int q)
>
> static hwaddr gem_get_desc_addr(CadenceGEMState *s, bool tx, int q) {
> hwaddr desc_addr = 0;
>
>- if (s->regs[R_DMACFG] & GEM_DMACFG_ADDR_64B) {
>+ if (FIELD_EX32(s->regs[R_DMACFG], DMACFG, DMA_ADDR_BUS_WIDTH)) {
> desc_addr = s->regs[tx ? R_TBQPH : R_RBQPH];
> }
> desc_addr <<= 32;
> desc_addr |= tx ? s->tx_desc_addr[q] : s->rx_desc_addr[q];
> return desc_addr;
>@@ -1022,12 +1035,13 @@ static ssize_t gem_receive(NetClientState *nc,
>const uint8_t *buf, size_t size)
> rxbuf_offset = FIELD_EX32(s->regs[R_NWCFG], NWCFG,
>RECV_BUF_OFFSET);
>
> /* The configure size of each receive buffer. Determines how many
> * buffers needed to hold this packet.
> */
>- rxbufsize = ((s->regs[R_DMACFG] & GEM_DMACFG_RBUFSZ_M) >>
>- GEM_DMACFG_RBUFSZ_S) * GEM_DMACFG_RBUFSZ_MUL;
>+ rxbufsize = FIELD_EX32(s->regs[R_DMACFG], DMACFG, RX_BUF_SIZE);
>+ rxbufsize *= GEM_DMACFG_RBUFSZ_MUL;
>+
> bytes_to_copy = size;
>
> /* Hardware allows a zero value here but warns against it. To avoid QEMU
> * indefinite loops we enforce a minimum value here
> */
>@@ -1306,11 +1320,11 @@ static void gem_transmit(CadenceGEMState *s)
>
> /* Handle interrupt consequences */
> gem_update_int_status(s);
>
> /* Is checksum offload enabled? */
>- if (s->regs[R_DMACFG] & GEM_DMACFG_TXCSUM_OFFL) {
>+ if (FIELD_EX32(s->regs[R_DMACFG], DMACFG,
>+ TX_PBUF_CSUM_OFFLOAD)) {
> net_checksum_calculate(s->tx_packet, total_bytes, CSUM_ALL);
> }
>
> /* Update MAC statistics */
> gem_transmit_updatestats(s, s->tx_packet, total_bytes); @@ -
>1330,11 +1344,11 @@ static void gem_transmit(CadenceGEMState *s)
> total_bytes = 0;
> }
>
> /* read next descriptor */
> if (tx_desc_get_wrap(desc)) {
>- if (s->regs[R_DMACFG] & GEM_DMACFG_ADDR_64B) {
>+ if (FIELD_EX32(s->regs[R_DMACFG], DMACFG,
>+ DMA_ADDR_BUS_WIDTH)) {
> packet_desc_addr = s->regs[R_TBQPH];
> packet_desc_addr <<= 32;
> } else {
> packet_desc_addr = 0;
> }
>--
>2.39.2
^ permalink raw reply [flat|nested] 25+ messages in thread
* RE: [PATCH 06/11] hw/net/cadence_gem: use FIELD to describe [TX|RX]STATUS register fields
2023-10-17 19:44 ` [PATCH 06/11] hw/net/cadence_gem: use FIELD to describe [TX|RX]STATUS " Luc Michel
@ 2023-10-18 10:21 ` Boddu, Sai Pavan
0 siblings, 0 replies; 25+ messages in thread
From: Boddu, Sai Pavan @ 2023-10-18 10:21 UTC (permalink / raw)
To: Michel, Luc, qemu-devel@nongnu.org
Cc: Michel, Luc, qemu-arm@nongnu.org, Edgar E . Iglesias,
Alistair Francis, Peter Maydell, Jason Wang,
Philippe Mathieu-Daudé, Iglesias, Francisco,
Konrad, Frederic
>-----Original Message-----
>From: Luc Michel <luc.michel@amd.com>
>Sent: Wednesday, October 18, 2023 1:14 AM
>To: qemu-devel@nongnu.org
>Cc: Michel, Luc <Luc.Michel@amd.com>; qemu-arm@nongnu.org; Edgar E .
>Iglesias <edgar.iglesias@gmail.com>; Alistair Francis <alistair@alistair23.me>;
>Peter Maydell <peter.maydell@linaro.org>; Jason Wang
><jasowang@redhat.com>; Philippe Mathieu-Daudé <philmd@linaro.org>;
>Iglesias, Francisco <francisco.iglesias@amd.com>; Konrad, Frederic
><Frederic.Konrad@amd.com>; Boddu, Sai Pavan
><sai.pavan.boddu@amd.com>
>Subject: [PATCH 06/11] hw/net/cadence_gem: use FIELD to describe
>[TX|RX]STATUS register fields
>
>Use de FIELD macro to describe the TXSTATUS and RXSTATUS register fields.
>
>Signed-off-by: Luc Michel <luc.michel@amd.com>
Reviewed-by: sai.pavan.boddu@amd.com
>---
> hw/net/cadence_gem.c | 34 +++++++++++++++++++++++++---------
> 1 file changed, 25 insertions(+), 9 deletions(-)
>
>diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c index
>5c386adff2..0acee1d544 100644
>--- a/hw/net/cadence_gem.c
>+++ b/hw/net/cadence_gem.c
>@@ -130,13 +130,34 @@ REG32(DMACFG, 0x10) /* DMA Control reg */
> FIELD(DMACFG, HDR_DATA_SPLIT_EN, 5, 1)
> FIELD(DMACFG, AMBA_BURST_LEN , 0, 5)
> #define GEM_DMACFG_RBUFSZ_MUL 64 /* DMA RX Buffer Size multiplier
>*/
>
> REG32(TXSTATUS, 0x14) /* TX Status reg */
>+ FIELD(TXSTATUS, TX_USED_BIT_READ_MIDFRAME, 12, 1)
>+ FIELD(TXSTATUS, TX_FRAME_TOO_LARGE, 11, 1)
>+ FIELD(TXSTATUS, TX_DMA_LOCKUP, 10, 1)
>+ FIELD(TXSTATUS, TX_MAC_LOCKUP, 9, 1)
>+ FIELD(TXSTATUS, RESP_NOT_OK, 8, 1)
>+ FIELD(TXSTATUS, LATE_COLLISION, 7, 1)
>+ FIELD(TXSTATUS, TRANSMIT_UNDER_RUN, 6, 1)
>+ FIELD(TXSTATUS, TRANSMIT_COMPLETE, 5, 1)
>+ FIELD(TXSTATUS, AMBA_ERROR, 4, 1)
>+ FIELD(TXSTATUS, TRANSMIT_GO, 3, 1)
>+ FIELD(TXSTATUS, RETRY_LIMIT, 2, 1)
>+ FIELD(TXSTATUS, COLLISION, 1, 1)
>+ FIELD(TXSTATUS, USED_BIT_READ, 0, 1)
>+
> REG32(RXQBASE, 0x18) /* RX Q Base address reg */ REG32(TXQBASE, 0x1c) /*
>TX Q Base address reg */ REG32(RXSTATUS, 0x20) /* RX Status reg */
>+ FIELD(RXSTATUS, RX_DMA_LOCKUP, 5, 1)
>+ FIELD(RXSTATUS, RX_MAC_LOCKUP, 4, 1)
>+ FIELD(RXSTATUS, RESP_NOT_OK, 3, 1)
>+ FIELD(RXSTATUS, RECEIVE_OVERRUN, 2, 1)
>+ FIELD(RXSTATUS, FRAME_RECEIVED, 1, 1)
>+ FIELD(RXSTATUS, BUF_NOT_AVAILABLE, 0, 1)
>+
> REG32(ISR, 0x24) /* Interrupt Status reg */ REG32(IER, 0x28) /* Interrupt
>Enable reg */ REG32(IDR, 0x2c) /* Interrupt Disable reg */ REG32(IMR, 0x30)
>/* Interrupt Mask reg */ REG32(PHYMNTNC, 0x34) /* Phy Maintenance reg */
>@@ -284,15 +305,10 @@ REG32(TYPE2_COMPARE_0_WORD_1, 0x704)
> FIELD(TYPE2_COMPARE_0_WORD_1, DISABLE_MASK, 9, 1)
> FIELD(TYPE2_COMPARE_0_WORD_1, COMPARE_VLAN_ID, 10, 1)
>
> /*****************************************/
>
>-#define GEM_TXSTATUS_TXCMPL 0x00000020 /* Transmit Complete */
>-#define GEM_TXSTATUS_USED 0x00000001 /* sw owned descriptor
>encountered */
>-
>-#define GEM_RXSTATUS_FRMRCVD 0x00000002 /* Frame received */
>-#define GEM_RXSTATUS_NOBUF 0x00000001 /* Buffer unavailable */
>
> /* GEM_ISR GEM_IER GEM_IDR GEM_IMR */
> #define GEM_INT_TXCMPL 0x00000080 /* Transmit Complete */
> #define GEM_INT_AMBA_ERR 0x00000040
> #define GEM_INT_TXUSED 0x00000008
>@@ -985,11 +1001,11 @@ static void gem_get_rx_desc(CadenceGEMState *s,
>int q)
> sizeof(uint32_t) * gem_get_desc_len(s, true));
>
> /* Descriptor owned by software ? */
> if (rx_desc_get_ownership(s->rx_desc[q]) == 1) {
> DB_PRINT("descriptor 0x%" HWADDR_PRIx " owned by sw.\n",
>desc_addr);
>- s->regs[R_RXSTATUS] |= GEM_RXSTATUS_NOBUF;
>+ s->regs[R_RXSTATUS] |= R_RXSTATUS_BUF_NOT_AVAILABLE_MASK;
> gem_set_isr(s, q, GEM_INT_RXUSED);
> /* Handle interrupt consequences */
> gem_update_int_status(s);
> }
> }
>@@ -1162,11 +1178,11 @@ static ssize_t gem_receive(NetClientState *nc,
>const uint8_t *buf, size_t size)
> }
>
> /* Count it */
> gem_receive_updatestats(s, buf, size);
>
>- s->regs[R_RXSTATUS] |= GEM_RXSTATUS_FRMRCVD;
>+ s->regs[R_RXSTATUS] |= R_RXSTATUS_FRAME_RECEIVED_MASK;
> gem_set_isr(s, q, GEM_INT_RXCMPL);
>
> /* Handle interrupt consequences */
> gem_update_int_status(s);
>
>@@ -1313,11 +1329,11 @@ static void gem_transmit(CadenceGEMState *s)
> s->tx_desc_addr[q] = packet_desc_addr +
> 4 * gem_get_desc_len(s, false);
> }
> DB_PRINT("TX descriptor next: 0x%08x\n", s->tx_desc_addr[q]);
>
>- s->regs[R_TXSTATUS] |= GEM_TXSTATUS_TXCMPL;
>+ s->regs[R_TXSTATUS] |=
>+ R_TXSTATUS_TRANSMIT_COMPLETE_MASK;
> gem_set_isr(s, q, GEM_INT_TXCMPL);
>
> /* Handle interrupt consequences */
> gem_update_int_status(s);
>
>@@ -1361,11 +1377,11 @@ static void gem_transmit(CadenceGEMState *s)
> MEMTXATTRS_UNSPECIFIED, desc,
> sizeof(uint32_t) * gem_get_desc_len(s, false));
> }
>
> if (tx_desc_get_used(desc)) {
>- s->regs[R_TXSTATUS] |= GEM_TXSTATUS_USED;
>+ s->regs[R_TXSTATUS] |= R_TXSTATUS_USED_BIT_READ_MASK;
> /* IRQ TXUSED is defined only for queue 0 */
> if (q == 0) {
> gem_set_isr(s, 0, GEM_INT_TXUSED);
> }
> gem_update_int_status(s);
>--
>2.39.2
^ permalink raw reply [flat|nested] 25+ messages in thread
* RE: [PATCH 07/11] hw/net/cadence_gem: use FIELD to describe IRQ register fields
2023-10-17 19:44 ` [PATCH 07/11] hw/net/cadence_gem: use FIELD to describe IRQ " Luc Michel
@ 2023-10-18 10:22 ` Boddu, Sai Pavan
0 siblings, 0 replies; 25+ messages in thread
From: Boddu, Sai Pavan @ 2023-10-18 10:22 UTC (permalink / raw)
To: Michel, Luc, qemu-devel@nongnu.org
Cc: Michel, Luc, qemu-arm@nongnu.org, Edgar E . Iglesias,
Alistair Francis, Peter Maydell, Jason Wang,
Philippe Mathieu-Daudé, Iglesias, Francisco,
Konrad, Frederic
>-----Original Message-----
>From: Luc Michel <luc.michel@amd.com>
>Sent: Wednesday, October 18, 2023 1:14 AM
>To: qemu-devel@nongnu.org
>Cc: Michel, Luc <Luc.Michel@amd.com>; qemu-arm@nongnu.org; Edgar E .
>Iglesias <edgar.iglesias@gmail.com>; Alistair Francis <alistair@alistair23.me>;
>Peter Maydell <peter.maydell@linaro.org>; Jason Wang
><jasowang@redhat.com>; Philippe Mathieu-Daudé <philmd@linaro.org>;
>Iglesias, Francisco <francisco.iglesias@amd.com>; Konrad, Frederic
><Frederic.Konrad@amd.com>; Boddu, Sai Pavan
><sai.pavan.boddu@amd.com>
>Subject: [PATCH 07/11] hw/net/cadence_gem: use FIELD to describe IRQ
>register fields
>
>Use de FIELD macro to describe the IRQ related register fields.
>
>Signed-off-by: Luc Michel <luc.michel@amd.com>
Reviewed-by: sai.pavan.boddu@amd.com
>---
> hw/net/cadence_gem.c | 51 +++++++++++++++++++++++++++++++++-------
>----
> 1 file changed, 39 insertions(+), 12 deletions(-)
>
>diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c index
>0acee1d544..6d084a3b31 100644
>--- a/hw/net/cadence_gem.c
>+++ b/hw/net/cadence_gem.c
>@@ -155,13 +155,46 @@ REG32(RXSTATUS, 0x20) /* RX Status reg */
> FIELD(RXSTATUS, RECEIVE_OVERRUN, 2, 1)
> FIELD(RXSTATUS, FRAME_RECEIVED, 1, 1)
> FIELD(RXSTATUS, BUF_NOT_AVAILABLE, 0, 1)
>
> REG32(ISR, 0x24) /* Interrupt Status reg */
>+ FIELD(ISR, TX_LOCKUP, 31, 1)
>+ FIELD(ISR, RX_LOCKUP, 30, 1)
>+ FIELD(ISR, TSU_TIMER, 29, 1)
>+ FIELD(ISR, WOL, 28, 1)
>+ FIELD(ISR, RECV_LPI, 27, 1)
>+ FIELD(ISR, TSU_SEC_INCR, 26, 1)
>+ FIELD(ISR, PTP_PDELAY_RESP_XMIT, 25, 1)
>+ FIELD(ISR, PTP_PDELAY_REQ_XMIT, 24, 1)
>+ FIELD(ISR, PTP_PDELAY_RESP_RECV, 23, 1)
>+ FIELD(ISR, PTP_PDELAY_REQ_RECV, 22, 1)
>+ FIELD(ISR, PTP_SYNC_XMIT, 21, 1)
>+ FIELD(ISR, PTP_DELAY_REQ_XMIT, 20, 1)
>+ FIELD(ISR, PTP_SYNC_RECV, 19, 1)
>+ FIELD(ISR, PTP_DELAY_REQ_RECV, 18, 1)
>+ FIELD(ISR, PCS_LP_PAGE_RECV, 17, 1)
>+ FIELD(ISR, PCS_AN_COMPLETE, 16, 1)
>+ FIELD(ISR, EXT_IRQ, 15, 1)
>+ FIELD(ISR, PAUSE_FRAME_XMIT, 14, 1)
>+ FIELD(ISR, PAUSE_TIME_ELAPSED, 13, 1)
>+ FIELD(ISR, PAUSE_FRAME_RECV, 12, 1)
>+ FIELD(ISR, RESP_NOT_OK, 11, 1)
>+ FIELD(ISR, RECV_OVERRUN, 10, 1)
>+ FIELD(ISR, LINK_CHANGE, 9, 1)
>+ FIELD(ISR, USXGMII_INT, 8, 1)
>+ FIELD(ISR, XMIT_COMPLETE, 7, 1)
>+ FIELD(ISR, AMBA_ERROR, 6, 1)
>+ FIELD(ISR, RETRY_EXCEEDED, 5, 1)
>+ FIELD(ISR, XMIT_UNDER_RUN, 4, 1)
>+ FIELD(ISR, TX_USED, 3, 1)
>+ FIELD(ISR, RX_USED, 2, 1)
>+ FIELD(ISR, RECV_COMPLETE, 1, 1)
>+ FIELD(ISR, MGNT_FRAME_SENT, 0, 1)
> REG32(IER, 0x28) /* Interrupt Enable reg */ REG32(IDR, 0x2c) /* Interrupt
>Disable reg */ REG32(IMR, 0x30) /* Interrupt Mask reg */
>+
> REG32(PHYMNTNC, 0x34) /* Phy Maintenance reg */ REG32(RXPAUSE, 0x38)
>/* RX Pause Time reg */ REG32(TXPAUSE, 0x3c) /* TX Pause Time reg */
>REG32(TXPARTIALSF, 0x40) /* TX Partial Store and Forward */
>REG32(RXPARTIALSF, 0x44) /* RX Partial Store and Forward */ @@ -306,16
>+339,10 @@ REG32(TYPE2_COMPARE_0_WORD_1, 0x704)
> FIELD(TYPE2_COMPARE_0_WORD_1, COMPARE_VLAN_ID, 10, 1)
>
> /*****************************************/
>
>
>-/* GEM_ISR GEM_IER GEM_IDR GEM_IMR */
>-#define GEM_INT_TXCMPL 0x00000080 /* Transmit Complete */
>-#define GEM_INT_AMBA_ERR 0x00000040
>-#define GEM_INT_TXUSED 0x00000008
>-#define GEM_INT_RXUSED 0x00000004
>-#define GEM_INT_RXCMPL 0x00000002
>
> #define GEM_PHYMNTNC_OP_R 0x20000000 /* read operation */
> #define GEM_PHYMNTNC_OP_W 0x10000000 /* write operation */
> #define GEM_PHYMNTNC_ADDR 0x0F800000 /* Address bits */
> #define GEM_PHYMNTNC_ADDR_SHFT 23
>@@ -1002,11 +1029,11 @@ static void gem_get_rx_desc(CadenceGEMState
>*s, int q)
>
> /* Descriptor owned by software ? */
> if (rx_desc_get_ownership(s->rx_desc[q]) == 1) {
> DB_PRINT("descriptor 0x%" HWADDR_PRIx " owned by sw.\n",
>desc_addr);
> s->regs[R_RXSTATUS] |= R_RXSTATUS_BUF_NOT_AVAILABLE_MASK;
>- gem_set_isr(s, q, GEM_INT_RXUSED);
>+ gem_set_isr(s, q, R_ISR_RX_USED_MASK);
> /* Handle interrupt consequences */
> gem_update_int_status(s);
> }
> }
>
>@@ -1102,11 +1129,11 @@ static ssize_t gem_receive(NetClientState *nc,
>const uint8_t *buf, size_t size)
> /* Find which queue we are targeting */
> q = get_queue_from_screen(s, rxbuf_ptr, rxbufsize);
>
> if (size > gem_get_max_buf_len(s, false)) {
> qemu_log_mask(LOG_GUEST_ERROR, "rx frame too long\n");
>- gem_set_isr(s, q, GEM_INT_AMBA_ERR);
>+ gem_set_isr(s, q, R_ISR_AMBA_ERROR_MASK);
> return -1;
> }
>
> while (bytes_to_copy) {
> hwaddr desc_addr;
>@@ -1179,11 +1206,11 @@ static ssize_t gem_receive(NetClientState *nc,
>const uint8_t *buf, size_t size)
>
> /* Count it */
> gem_receive_updatestats(s, buf, size);
>
> s->regs[R_RXSTATUS] |= R_RXSTATUS_FRAME_RECEIVED_MASK;
>- gem_set_isr(s, q, GEM_INT_RXCMPL);
>+ gem_set_isr(s, q, R_ISR_RECV_COMPLETE_MASK);
>
> /* Handle interrupt consequences */
> gem_update_int_status(s);
>
> return size;
>@@ -1292,11 +1319,11 @@ static void gem_transmit(CadenceGEMState *s)
> (p - s->tx_packet)) {
> qemu_log_mask(LOG_GUEST_ERROR, "TX descriptor @ 0x%" \
> HWADDR_PRIx " too large: size 0x%x space 0x%zx\n",
> packet_desc_addr, tx_desc_get_length(desc),
> gem_get_max_buf_len(s, true) - (p - s->tx_packet));
>- gem_set_isr(s, q, GEM_INT_AMBA_ERR);
>+ gem_set_isr(s, q, R_ISR_AMBA_ERROR_MASK);
> break;
> }
>
> /* Gather this fragment of the packet from "dma memory" to our
> * contig buffer.
>@@ -1330,11 +1357,11 @@ static void gem_transmit(CadenceGEMState *s)
> 4 * gem_get_desc_len(s, false);
> }
> DB_PRINT("TX descriptor next: 0x%08x\n", s->tx_desc_addr[q]);
>
> s->regs[R_TXSTATUS] |= R_TXSTATUS_TRANSMIT_COMPLETE_MASK;
>- gem_set_isr(s, q, GEM_INT_TXCMPL);
>+ gem_set_isr(s, q, R_ISR_XMIT_COMPLETE_MASK);
>
> /* Handle interrupt consequences */
> gem_update_int_status(s);
>
> /* Is checksum offload enabled? */ @@ -1380,11 +1407,11 @@ static
>void gem_transmit(CadenceGEMState *s)
>
> if (tx_desc_get_used(desc)) {
> s->regs[R_TXSTATUS] |= R_TXSTATUS_USED_BIT_READ_MASK;
> /* IRQ TXUSED is defined only for queue 0 */
> if (q == 0) {
>- gem_set_isr(s, 0, GEM_INT_TXUSED);
>+ gem_set_isr(s, 0, R_ISR_TX_USED_MASK);
> }
> gem_update_int_status(s);
> }
> }
> }
>--
>2.39.2
^ permalink raw reply [flat|nested] 25+ messages in thread
* RE: [PATCH 09/11] hw/net/cadence_gem: use FIELD to describe PHYMNTNC register fields
2023-10-17 19:44 ` [PATCH 09/11] hw/net/cadence_gem: use FIELD to describe PHYMNTNC " Luc Michel
@ 2023-10-18 10:23 ` Boddu, Sai Pavan
0 siblings, 0 replies; 25+ messages in thread
From: Boddu, Sai Pavan @ 2023-10-18 10:23 UTC (permalink / raw)
To: Michel, Luc, qemu-devel@nongnu.org
Cc: Michel, Luc, qemu-arm@nongnu.org, Edgar E . Iglesias,
Alistair Francis, Peter Maydell, Jason Wang,
Philippe Mathieu-Daudé, Iglesias, Francisco,
Konrad, Frederic
>-----Original Message-----
>From: Luc Michel <luc.michel@amd.com>
>Sent: Wednesday, October 18, 2023 1:14 AM
>To: qemu-devel@nongnu.org
>Cc: Michel, Luc <Luc.Michel@amd.com>; qemu-arm@nongnu.org; Edgar E .
>Iglesias <edgar.iglesias@gmail.com>; Alistair Francis <alistair@alistair23.me>;
>Peter Maydell <peter.maydell@linaro.org>; Jason Wang
><jasowang@redhat.com>; Philippe Mathieu-Daudé <philmd@linaro.org>;
>Iglesias, Francisco <francisco.iglesias@amd.com>; Konrad, Frederic
><Frederic.Konrad@amd.com>; Boddu, Sai Pavan
><sai.pavan.boddu@amd.com>
>Subject: [PATCH 09/11] hw/net/cadence_gem: use FIELD to describe
>PHYMNTNC register fields
>
>Use the FIELD macro to describe the PHYMNTNC register fields.
>
>Signed-off-by: Luc Michel <luc.michel@amd.com>
Reviewed-by: sai.pavan.boddu@amd.com
>---
> hw/net/cadence_gem.c | 27 ++++++++++++++-------------
> 1 file changed, 14 insertions(+), 13 deletions(-)
>
>diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c index
>955a8da134..4c5fe10316 100644
>--- a/hw/net/cadence_gem.c
>+++ b/hw/net/cadence_gem.c
>@@ -192,10 +192,18 @@ REG32(ISR, 0x24) /* Interrupt Status reg */
>REG32(IER, 0x28) /* Interrupt Enable reg */ REG32(IDR, 0x2c) /* Interrupt
>Disable reg */ REG32(IMR, 0x30) /* Interrupt Mask reg */
>
> REG32(PHYMNTNC, 0x34) /* Phy Maintenance reg */
>+ FIELD(PHYMNTNC, DATA, 0, 16)
>+ FIELD(PHYMNTNC, REG_ADDR, 18, 5)
>+ FIELD(PHYMNTNC, PHY_ADDR, 23, 5)
>+ FIELD(PHYMNTNC, OP, 28, 2)
>+ FIELD(PHYMNTNC, ST, 30, 2)
>+#define MDIO_OP_READ 0x3
>+#define MDIO_OP_WRITE 0x2
>+
> REG32(RXPAUSE, 0x38) /* RX Pause Time reg */ REG32(TXPAUSE, 0x3c) /* TX
>Pause Time reg */ REG32(TXPARTIALSF, 0x40) /* TX Partial Store and Forward
>*/ REG32(RXPARTIALSF, 0x44) /* RX Partial Store and Forward */
>REG32(JUMBO_MAX_LEN, 0x48) /* Max Jumbo Frame Size */ @@ -340,17
>+348,10 @@ REG32(TYPE2_COMPARE_0_WORD_1, 0x704)
>
> /*****************************************/
>
>
>
>-#define GEM_PHYMNTNC_OP_R 0x20000000 /* read operation */
>-#define GEM_PHYMNTNC_OP_W 0x10000000 /* write operation */
>-#define GEM_PHYMNTNC_ADDR 0x0F800000 /* Address bits */
>-#define GEM_PHYMNTNC_ADDR_SHFT 23
>-#define GEM_PHYMNTNC_REG 0x007C0000 /* register bits */
>-#define GEM_PHYMNTNC_REG_SHIFT 18
>-
> /* Marvell PHY definitions */
> #define BOARD_PHY_ADDRESS 0 /* PHY address we will emulate a device at
>*/
>
> #define PHY_REG_CONTROL 0
> #define PHY_REG_STATUS 1
>@@ -1539,16 +1540,16 @@ static uint64_t gem_read(void *opaque, hwaddr
>offset, unsigned size)
> case R_ISR:
> DB_PRINT("lowering irqs on ISR read\n");
> /* The interrupts get updated at the end of the function. */
> break;
> case R_PHYMNTNC:
>- if (retval & GEM_PHYMNTNC_OP_R) {
>+ if (FIELD_EX32(retval, PHYMNTNC, OP) == MDIO_OP_READ) {
> uint32_t phy_addr, reg_num;
>
>- phy_addr = (retval & GEM_PHYMNTNC_ADDR) >>
>GEM_PHYMNTNC_ADDR_SHFT;
>+ phy_addr = FIELD_EX32(retval, PHYMNTNC, PHY_ADDR);
> if (phy_addr == s->phy_addr) {
>- reg_num = (retval & GEM_PHYMNTNC_REG) >>
>GEM_PHYMNTNC_REG_SHIFT;
>+ reg_num = FIELD_EX32(retval, PHYMNTNC, REG_ADDR);
> retval &= 0xFFFF0000;
> retval |= gem_phy_read(s, reg_num);
> } else {
> retval |= 0xFFFF; /* No device at this address */
> }
>@@ -1662,16 +1663,16 @@ static void gem_write(void *opaque, hwaddr
>offset, uint64_t val,
> case R_SPADDR3HI:
> case R_SPADDR4HI:
> s->sar_active[(offset - R_SPADDR1HI) / 2] = true;
> break;
> case R_PHYMNTNC:
>- if (val & GEM_PHYMNTNC_OP_W) {
>+ if (FIELD_EX32(val, PHYMNTNC, OP) == MDIO_OP_WRITE) {
> uint32_t phy_addr, reg_num;
>
>- phy_addr = (val & GEM_PHYMNTNC_ADDR) >>
>GEM_PHYMNTNC_ADDR_SHFT;
>+ phy_addr = FIELD_EX32(val, PHYMNTNC, PHY_ADDR);
> if (phy_addr == s->phy_addr) {
>- reg_num = (val & GEM_PHYMNTNC_REG) >>
>GEM_PHYMNTNC_REG_SHIFT;
>+ reg_num = FIELD_EX32(val, PHYMNTNC, REG_ADDR);
> gem_phy_write(s, reg_num, val);
> }
> }
> break;
> }
>--
>2.39.2
^ permalink raw reply [flat|nested] 25+ messages in thread
* RE: [PATCH 10/11] hw/net/cadence_gem: perform PHY access on write only
2023-10-17 19:44 ` [PATCH 10/11] hw/net/cadence_gem: perform PHY access on write only Luc Michel
@ 2023-10-18 10:35 ` Boddu, Sai Pavan
0 siblings, 0 replies; 25+ messages in thread
From: Boddu, Sai Pavan @ 2023-10-18 10:35 UTC (permalink / raw)
To: Michel, Luc, qemu-devel@nongnu.org
Cc: Michel, Luc, qemu-arm@nongnu.org, Edgar E . Iglesias,
Alistair Francis, Peter Maydell, Jason Wang,
Philippe Mathieu-Daudé, Iglesias, Francisco,
Konrad, Frederic
>-----Original Message-----
>From: Luc Michel <luc.michel@amd.com>
>Sent: Wednesday, October 18, 2023 1:14 AM
>To: qemu-devel@nongnu.org
>Cc: Michel, Luc <Luc.Michel@amd.com>; qemu-arm@nongnu.org; Edgar E .
>Iglesias <edgar.iglesias@gmail.com>; Alistair Francis <alistair@alistair23.me>;
>Peter Maydell <peter.maydell@linaro.org>; Jason Wang
><jasowang@redhat.com>; Philippe Mathieu-Daudé <philmd@linaro.org>;
>Iglesias, Francisco <francisco.iglesias@amd.com>; Konrad, Frederic
><Frederic.Konrad@amd.com>; Boddu, Sai Pavan
><sai.pavan.boddu@amd.com>
>Subject: [PATCH 10/11] hw/net/cadence_gem: perform PHY access on write
>only
>
>The MDIO access is done only on a write to the PHYMNTNC register. A
>subsequent read is used to retrieve the result but does not trigger an MDIO
>access by itself.
>
>Refactor the PHY access logic to perform all accesses (MDIO reads and
>writes) at PHYMNTNC write time.
>
>Signed-off-by: Luc Michel <luc.michel@amd.com>
Reviewed-by: sai.pavan.boddu@amd.com
>---
> hw/net/cadence_gem.c | 56 ++++++++++++++++++++++++++------------------
> 1 file changed, 33 insertions(+), 23 deletions(-)
>
>diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c index
>4c5fe10316..21146f4242 100644
>--- a/hw/net/cadence_gem.c
>+++ b/hw/net/cadence_gem.c
>@@ -1519,10 +1519,42 @@ static void gem_phy_write(CadenceGEMState *s,
>unsigned reg_num, uint16_t val)
> break;
> }
> s->phy_regs[reg_num] = val;
> }
>
>+static void gem_handle_phy_access(CadenceGEMState *s) {
>+ uint32_t val = s->regs[R_PHYMNTNC];
>+ uint32_t phy_addr, reg_num;
>+
>+ phy_addr = FIELD_EX32(val, PHYMNTNC, PHY_ADDR);
>+
>+ if (phy_addr != s->phy_addr) {
>+ /* no phy at this address */
>+ if (FIELD_EX32(val, PHYMNTNC, OP) == MDIO_OP_READ) {
>+ s->regs[R_PHYMNTNC] = FIELD_DP32(val, PHYMNTNC, DATA, 0xffff);
>+ }
>+ return;
>+ }
>+
>+ reg_num = FIELD_EX32(val, PHYMNTNC, REG_ADDR);
>+
>+ switch (FIELD_EX32(val, PHYMNTNC, OP)) {
>+ case MDIO_OP_READ:
>+ s->regs[R_PHYMNTNC] = FIELD_DP32(val, PHYMNTNC, DATA,
>+ gem_phy_read(s, reg_num));
>+ break;
>+
>+ case MDIO_OP_WRITE:
>+ gem_phy_write(s, reg_num, val);
>+ break;
>+
>+ default:
>+ break; /* only clause 22 operations are supported */
>+ }
>+}
>+
> /*
> * gem_read32:
> * Read a GEM register.
> */
> static uint64_t gem_read(void *opaque, hwaddr offset, unsigned size) @@ -
>1539,24 +1571,10 @@ static uint64_t gem_read(void *opaque, hwaddr
>offset, unsigned size)
> switch (offset) {
> case R_ISR:
> DB_PRINT("lowering irqs on ISR read\n");
> /* The interrupts get updated at the end of the function. */
> break;
>- case R_PHYMNTNC:
>- if (FIELD_EX32(retval, PHYMNTNC, OP) == MDIO_OP_READ) {
>- uint32_t phy_addr, reg_num;
>-
>- phy_addr = FIELD_EX32(retval, PHYMNTNC, PHY_ADDR);
>- if (phy_addr == s->phy_addr) {
>- reg_num = FIELD_EX32(retval, PHYMNTNC, REG_ADDR);
>- retval &= 0xFFFF0000;
>- retval |= gem_phy_read(s, reg_num);
>- } else {
>- retval |= 0xFFFF; /* No device at this address */
>- }
>- }
>- break;
> }
>
> /* Squash read to clear bits */
> s->regs[offset] &= ~(s->regs_rtc[offset]);
>
>@@ -1663,19 +1681,11 @@ static void gem_write(void *opaque, hwaddr
>offset, uint64_t val,
> case R_SPADDR3HI:
> case R_SPADDR4HI:
> s->sar_active[(offset - R_SPADDR1HI) / 2] = true;
> break;
> case R_PHYMNTNC:
>- if (FIELD_EX32(val, PHYMNTNC, OP) == MDIO_OP_WRITE) {
>- uint32_t phy_addr, reg_num;
>-
>- phy_addr = FIELD_EX32(val, PHYMNTNC, PHY_ADDR);
>- if (phy_addr == s->phy_addr) {
>- reg_num = FIELD_EX32(val, PHYMNTNC, REG_ADDR);
>- gem_phy_write(s, reg_num, val);
>- }
>- }
>+ gem_handle_phy_access(s);
> break;
> }
>
> DB_PRINT("newval: 0x%08x\n", s->regs[offset]); }
>--
>2.39.2
^ permalink raw reply [flat|nested] 25+ messages in thread
* RE: [PATCH 11/11] hw/net/cadence_gem: enforce 32 bits variable size for CRC
2023-10-17 19:44 ` [PATCH 11/11] hw/net/cadence_gem: enforce 32 bits variable size for CRC Luc Michel
2023-10-18 9:23 ` Philippe Mathieu-Daudé
@ 2023-10-18 10:36 ` Boddu, Sai Pavan
1 sibling, 0 replies; 25+ messages in thread
From: Boddu, Sai Pavan @ 2023-10-18 10:36 UTC (permalink / raw)
To: Michel, Luc, qemu-devel@nongnu.org
Cc: Michel, Luc, qemu-arm@nongnu.org, Edgar E . Iglesias,
Alistair Francis, Peter Maydell, Jason Wang,
Philippe Mathieu-Daudé, Iglesias, Francisco,
Konrad, Frederic
>-----Original Message-----
>From: Luc Michel <luc.michel@amd.com>
>Sent: Wednesday, October 18, 2023 1:14 AM
>To: qemu-devel@nongnu.org
>Cc: Michel, Luc <Luc.Michel@amd.com>; qemu-arm@nongnu.org; Edgar E .
>Iglesias <edgar.iglesias@gmail.com>; Alistair Francis <alistair@alistair23.me>;
>Peter Maydell <peter.maydell@linaro.org>; Jason Wang
><jasowang@redhat.com>; Philippe Mathieu-Daudé <philmd@linaro.org>;
>Iglesias, Francisco <francisco.iglesias@amd.com>; Konrad, Frederic
><Frederic.Konrad@amd.com>; Boddu, Sai Pavan
><sai.pavan.boddu@amd.com>
>Subject: [PATCH 11/11] hw/net/cadence_gem: enforce 32 bits variable size for
>CRC
>
>The CRC was stored in an unsigned variable in gem_receive. Change it for a
>uint32_t to ensure we have the correct variable size here.
>
>Signed-off-by: Luc Michel <luc.michel@amd.com>
Reviewed-by: sai.pavan.boddu@amd.com
>---
> hw/net/cadence_gem.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
>diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c index
>21146f4242..d52530bae4 100644
>--- a/hw/net/cadence_gem.c
>+++ b/hw/net/cadence_gem.c
>@@ -1103,11 +1103,11 @@ static ssize_t gem_receive(NetClientState *nc,
>const uint8_t *buf, size_t size)
>
> /* Strip of FCS field ? (usually yes) */
> if (FIELD_EX32(s->regs[R_NWCFG], NWCFG, FCS_REMOVE)) {
> rxbuf_ptr = (void *)buf;
> } else {
>- unsigned crc_val;
>+ uint32_t crc_val;
>
> if (size > MAX_FRAME_SIZE - sizeof(crc_val)) {
> size = MAX_FRAME_SIZE - sizeof(crc_val);
> }
> bytes_to_copy = size;
>--
>2.39.2
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 00/11] Various updates for the Cadence GEM model
2023-10-17 19:44 [PATCH 00/11] Various updates for the Cadence GEM model Luc Michel
` (10 preceding siblings ...)
2023-10-17 19:44 ` [PATCH 11/11] hw/net/cadence_gem: enforce 32 bits variable size for CRC Luc Michel
@ 2023-10-27 12:16 ` Peter Maydell
11 siblings, 0 replies; 25+ messages in thread
From: Peter Maydell @ 2023-10-27 12:16 UTC (permalink / raw)
To: Luc Michel
Cc: qemu-devel, qemu-arm, Edgar E . Iglesias, Alistair Francis,
Jason Wang, Philippe Mathieu-Daudé, Francisco Iglesias,
Frederic Konrad, Sai Pavan Boddu
On Tue, 17 Oct 2023 at 20:44, Luc Michel <luc.michel@amd.com> wrote:
>
> Hi,
>
> This series brings small changes to the Cadence GEM Ethernet model.
> There is (almost) no behaviour change.
>
> Patches 1 to 9 replace handcrafted defines with the use of REG32 and
> FIELDS macros for register and fields declarations.
>
> Patch 10 fixes PHY accesses so that they are done only on a write to the
> PHYMNTNC register (as the real hardware does).
>
> Patch 11 fixes a potential bug on hosts where unsigned would not be 32
> bits.
Applied to target-arm.next, thanks.
Note to Sai for the future: in Reviewed-by: tags, as with
Signed-off-by: tags, the expected form is "Full Name <email@example.com>",
not just a bare email address. (I would actively ask for a change
on a signed-off-by line with an email alone, but for Reviewed-by
it's less significant.)
thanks
-- PMM
^ permalink raw reply [flat|nested] 25+ messages in thread
end of thread, other threads:[~2023-10-27 12:17 UTC | newest]
Thread overview: 25+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2023-10-17 19:44 [PATCH 00/11] Various updates for the Cadence GEM model Luc Michel
2023-10-17 19:44 ` [PATCH 01/11] hw/net/cadence_gem: use REG32 macro for register definitions Luc Michel
2023-10-18 6:22 ` Boddu, Sai Pavan
2023-10-17 19:44 ` [PATCH 02/11] hw/net/cadence_gem: use FIELD for screening registers Luc Michel
2023-10-18 10:14 ` Boddu, Sai Pavan
2023-10-17 19:44 ` [PATCH 03/11] hw/net/cadence_gem: use FIELD to describe NWCTRL register fields Luc Michel
2023-10-18 10:15 ` Boddu, Sai Pavan
2023-10-17 19:44 ` [PATCH 04/11] hw/net/cadence_gem: use FIELD to describe NWCFG " Luc Michel
2023-10-18 10:18 ` Boddu, Sai Pavan
2023-10-17 19:44 ` [PATCH 05/11] hw/net/cadence_gem: use FIELD to describe DMACFG " Luc Michel
2023-10-18 10:20 ` Boddu, Sai Pavan
2023-10-17 19:44 ` [PATCH 06/11] hw/net/cadence_gem: use FIELD to describe [TX|RX]STATUS " Luc Michel
2023-10-18 10:21 ` Boddu, Sai Pavan
2023-10-17 19:44 ` [PATCH 07/11] hw/net/cadence_gem: use FIELD to describe IRQ " Luc Michel
2023-10-18 10:22 ` Boddu, Sai Pavan
2023-10-17 19:44 ` [PATCH 08/11] hw/net/cadence_gem: use FIELD to describe DESCONF6 " Luc Michel
2023-10-18 9:22 ` Philippe Mathieu-Daudé
2023-10-17 19:44 ` [PATCH 09/11] hw/net/cadence_gem: use FIELD to describe PHYMNTNC " Luc Michel
2023-10-18 10:23 ` Boddu, Sai Pavan
2023-10-17 19:44 ` [PATCH 10/11] hw/net/cadence_gem: perform PHY access on write only Luc Michel
2023-10-18 10:35 ` Boddu, Sai Pavan
2023-10-17 19:44 ` [PATCH 11/11] hw/net/cadence_gem: enforce 32 bits variable size for CRC Luc Michel
2023-10-18 9:23 ` Philippe Mathieu-Daudé
2023-10-18 10:36 ` Boddu, Sai Pavan
2023-10-27 12:16 ` [PATCH 00/11] Various updates for the Cadence GEM model Peter Maydell
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