* [PATCH v2 01/23] cpu-defs.h; Add MMU_INDEX() helper
2023-08-06 12:17 [PATCH v2 00/23] Introduce MMU_INDEX() Helge Deller
@ 2023-08-06 12:17 ` Helge Deller
2023-08-06 12:17 ` [PATCH v2 02/23] target/i386: Use " Helge Deller
` (21 subsequent siblings)
22 siblings, 0 replies; 27+ messages in thread
From: Helge Deller @ 2023-08-06 12:17 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Add a MMU_INDEX() helper to specify which MMU entry to use.
Currently this is just an 1:1 mapper, but in a follow-up
patch it will enable us to generate smaller (and maybe faster)
tcg code.
Signed-off-by: Helge Deller <deller@gmx.de>
---
include/exec/cpu-defs.h | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h
index fb4c8d480f..07bcdd38b2 100644
--- a/include/exec/cpu-defs.h
+++ b/include/exec/cpu-defs.h
@@ -60,6 +60,11 @@
*/
#define NB_MMU_MODES 16
+/*
+ * MMU_INDEX() helper to specify MMU index.
+ */
+#define MMU_INDEX(n) (n)
+
#if defined(CONFIG_SOFTMMU) && defined(CONFIG_TCG)
#include "exec/tlb-common.h"
--
2.41.0
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH v2 02/23] target/i386: Use MMU_INDEX() helper
2023-08-06 12:17 [PATCH v2 00/23] Introduce MMU_INDEX() Helge Deller
2023-08-06 12:17 ` [PATCH v2 01/23] cpu-defs.h; Add MMU_INDEX() helper Helge Deller
@ 2023-08-06 12:17 ` Helge Deller
2023-08-06 12:17 ` [PATCH v2 03/23] target/hppa: " Helge Deller
` (20 subsequent siblings)
22 siblings, 0 replies; 27+ messages in thread
From: Helge Deller @ 2023-08-06 12:17 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Use the new MMU_INDEX() helper to specify the index of the CPUTLB which
should be used. Additionally, in a follow-up patch this helper allows
then to optimize the tcg code generation.
Signed-off-by: Helge Deller <deller@gmx.de>
---
target/i386/cpu.h | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index e0771a1043..8fb1012346 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -2251,11 +2251,11 @@ uint64_t cpu_get_tsc(CPUX86State *env);
#define cpu_list x86_cpu_list
/* MMU modes definitions */
-#define MMU_KSMAP_IDX 0
-#define MMU_USER_IDX 1
-#define MMU_KNOSMAP_IDX 2
-#define MMU_NESTED_IDX 3
-#define MMU_PHYS_IDX 4
+#define MMU_KSMAP_IDX MMU_INDEX(0)
+#define MMU_USER_IDX MMU_INDEX(1)
+#define MMU_KNOSMAP_IDX MMU_INDEX(2)
+#define MMU_NESTED_IDX MMU_INDEX(3)
+#define MMU_PHYS_IDX MMU_INDEX(4)
static inline int cpu_mmu_index(CPUX86State *env, bool ifetch)
{
--
2.41.0
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH v2 03/23] target/hppa: Use MMU_INDEX() helper
2023-08-06 12:17 [PATCH v2 00/23] Introduce MMU_INDEX() Helge Deller
2023-08-06 12:17 ` [PATCH v2 01/23] cpu-defs.h; Add MMU_INDEX() helper Helge Deller
2023-08-06 12:17 ` [PATCH v2 02/23] target/i386: Use " Helge Deller
@ 2023-08-06 12:17 ` Helge Deller
2023-08-06 12:17 ` [PATCH v2 04/23] target/alpha: " Helge Deller
` (19 subsequent siblings)
22 siblings, 0 replies; 27+ messages in thread
From: Helge Deller @ 2023-08-06 12:17 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Use the new MMU_INDEX() helper to specify the index of the CPUTLB which
should be used. Additionally, in a follow-up patch this helper allows
then to optimize the tcg code generation.
Signed-off-by: Helge Deller <deller@gmx.de>
---
target/hppa/cpu.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h
index 75c5c0ccf7..f32d328e95 100644
--- a/target/hppa/cpu.h
+++ b/target/hppa/cpu.h
@@ -30,9 +30,9 @@
basis. It's probably easier to fall back to a strong memory model. */
#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL
-#define MMU_KERNEL_IDX 0
-#define MMU_USER_IDX 3
-#define MMU_PHYS_IDX 4
+#define MMU_KERNEL_IDX MMU_INDEX(0)
+#define MMU_USER_IDX MMU_INDEX(3)
+#define MMU_PHYS_IDX MMU_INDEX(4)
#define TARGET_INSN_START_EXTRA_WORDS 1
/* Hardware exceptions, interrupts, faults, and traps. */
--
2.41.0
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH v2 04/23] target/alpha: Use MMU_INDEX() helper
2023-08-06 12:17 [PATCH v2 00/23] Introduce MMU_INDEX() Helge Deller
` (2 preceding siblings ...)
2023-08-06 12:17 ` [PATCH v2 03/23] target/hppa: " Helge Deller
@ 2023-08-06 12:17 ` Helge Deller
2023-08-06 12:17 ` [PATCH v2 05/23] target/avr: " Helge Deller
` (18 subsequent siblings)
22 siblings, 0 replies; 27+ messages in thread
From: Helge Deller @ 2023-08-06 12:17 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Use the new MMU_INDEX() helper to specify the index of the CPUTLB which
should be used. Additionally, in a follow-up patch this helper allows
then to optimize the tcg code generation.
Signed-off-by: Helge Deller <deller@gmx.de>
---
target/alpha/cpu.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h
index 13306665af..9bf80cdb35 100644
--- a/target/alpha/cpu.h
+++ b/target/alpha/cpu.h
@@ -194,9 +194,9 @@ enum {
PALcode cheats and uses the KSEG mapping for its code+data rather than
physical addresses. */
-#define MMU_KERNEL_IDX 0
-#define MMU_USER_IDX 1
-#define MMU_PHYS_IDX 2
+#define MMU_KERNEL_IDX MMU_INDEX(0)
+#define MMU_USER_IDX MMU_INDEX(1)
+#define MMU_PHYS_IDX MMU_INDEX(2)
typedef struct CPUArchState {
uint64_t ir[31];
--
2.41.0
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH v2 05/23] target/avr: Use MMU_INDEX() helper
2023-08-06 12:17 [PATCH v2 00/23] Introduce MMU_INDEX() Helge Deller
` (3 preceding siblings ...)
2023-08-06 12:17 ` [PATCH v2 04/23] target/alpha: " Helge Deller
@ 2023-08-06 12:17 ` Helge Deller
2023-08-06 12:17 ` [PATCH v2 06/23] target/hexagon: " Helge Deller
` (17 subsequent siblings)
22 siblings, 0 replies; 27+ messages in thread
From: Helge Deller @ 2023-08-06 12:17 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Use the new MMU_INDEX() helper to specify the index of the CPUTLB which
should be used. Additionally, in a follow-up patch this helper allows
then to optimize the tcg code generation.
Signed-off-by: Helge Deller <deller@gmx.de>
---
target/avr/cpu.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/avr/cpu.h b/target/avr/cpu.h
index 7225174668..8b5916d243 100644
--- a/target/avr/cpu.h
+++ b/target/avr/cpu.h
@@ -40,8 +40,8 @@
* ST/LD instructions access data space
* LPM/SPM and instruction fetching access code memory space
*/
-#define MMU_CODE_IDX 0
-#define MMU_DATA_IDX 1
+#define MMU_CODE_IDX MMU_INDEX(0)
+#define MMU_DATA_IDX MMU_INDEX(1)
#define EXCP_RESET 1
#define EXCP_INT(n) (EXCP_RESET + (n) + 1)
--
2.41.0
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH v2 06/23] target/hexagon: Use MMU_INDEX() helper
2023-08-06 12:17 [PATCH v2 00/23] Introduce MMU_INDEX() Helge Deller
` (4 preceding siblings ...)
2023-08-06 12:17 ` [PATCH v2 05/23] target/avr: " Helge Deller
@ 2023-08-06 12:17 ` Helge Deller
2023-08-06 12:17 ` [PATCH v2 07/23] target/loongarch: " Helge Deller
` (16 subsequent siblings)
22 siblings, 0 replies; 27+ messages in thread
From: Helge Deller @ 2023-08-06 12:17 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Use the new MMU_INDEX() helper to specify the index of the CPUTLB which
should be used. Additionally, in a follow-up patch this helper allows
then to optimize the tcg code generation.
Signed-off-by: Helge Deller <deller@gmx.de>
---
target/hexagon/cpu.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h
index daef5c3f00..b4cf9f1a7d 100644
--- a/target/hexagon/cpu.h
+++ b/target/hexagon/cpu.h
@@ -51,7 +51,7 @@
void hexagon_cpu_list(void);
#define cpu_list hexagon_cpu_list
-#define MMU_USER_IDX 0
+#define MMU_USER_IDX MMU_INDEX(0)
typedef struct {
target_ulong va;
--
2.41.0
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH v2 07/23] target/loongarch: Use MMU_INDEX() helper
2023-08-06 12:17 [PATCH v2 00/23] Introduce MMU_INDEX() Helge Deller
` (5 preceding siblings ...)
2023-08-06 12:17 ` [PATCH v2 06/23] target/hexagon: " Helge Deller
@ 2023-08-06 12:17 ` Helge Deller
2023-08-06 12:17 ` [PATCH v2 08/23] target/mips: " Helge Deller
` (15 subsequent siblings)
22 siblings, 0 replies; 27+ messages in thread
From: Helge Deller @ 2023-08-06 12:17 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Use the new MMU_INDEX() helper to specify the index of the CPUTLB which
should be used. Additionally, in a follow-up patch this helper allows
then to optimize the tcg code generation.
Signed-off-by: Helge Deller <deller@gmx.de>
---
target/loongarch/cpu.h | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
index fa371ca8ba..ab15146d77 100644
--- a/target/loongarch/cpu.h
+++ b/target/loongarch/cpu.h
@@ -404,9 +404,9 @@ struct LoongArchCPUClass {
*/
#define MMU_PLV_KERNEL 0
#define MMU_PLV_USER 3
-#define MMU_IDX_KERNEL MMU_PLV_KERNEL
-#define MMU_IDX_USER MMU_PLV_USER
-#define MMU_IDX_DA 4
+#define MMU_IDX_KERNEL MMU_INDEX(MMU_PLV_KERNEL)
+#define MMU_IDX_USER MMU_INDEX(MMU_PLV_USER)
+#define MMU_IDX_DA MMU_INDEX(4)
static inline int cpu_mmu_index(CPULoongArchState *env, bool ifetch)
{
@@ -414,7 +414,7 @@ static inline int cpu_mmu_index(CPULoongArchState *env, bool ifetch)
return MMU_IDX_USER;
#else
if (FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PG)) {
- return FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV);
+ return MMU_INDEX(FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV));
}
return MMU_IDX_DA;
#endif
--
2.41.0
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH v2 08/23] target/mips: Use MMU_INDEX() helper
2023-08-06 12:17 [PATCH v2 00/23] Introduce MMU_INDEX() Helge Deller
` (6 preceding siblings ...)
2023-08-06 12:17 ` [PATCH v2 07/23] target/loongarch: " Helge Deller
@ 2023-08-06 12:17 ` Helge Deller
2023-08-06 12:17 ` [PATCH v2 09/23] target/openrisc: " Helge Deller
` (14 subsequent siblings)
22 siblings, 0 replies; 27+ messages in thread
From: Helge Deller @ 2023-08-06 12:17 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Use the new MMU_INDEX() helper to specify the index of the CPUTLB which
should be used. Additionally, in a follow-up patch this helper allows
then to optimize the tcg code generation.
Signed-off-by: Helge Deller <deller@gmx.de>
---
target/mips/cpu.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index f81bd06f5e..4039d59f61 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -1231,14 +1231,14 @@ extern uint32_t cpu_rddsp(uint32_t mask_num, CPUMIPSState *env);
* MMU modes definitions. We carefully match the indices with our
* hflags layout.
*/
-#define MMU_USER_IDX 2
+#define MMU_USER_IDX MMU_INDEX(2)
static inline int hflags_mmu_index(uint32_t hflags)
{
if (hflags & MIPS_HFLAG_ERL) {
- return 3; /* ERL */
+ return MMU_INDEX(3); /* ERL */
} else {
- return hflags & MIPS_HFLAG_KSU;
+ return MMU_INDEX(hflags & MIPS_HFLAG_KSU);
}
}
--
2.41.0
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH v2 09/23] target/openrisc: Use MMU_INDEX() helper
2023-08-06 12:17 [PATCH v2 00/23] Introduce MMU_INDEX() Helge Deller
` (7 preceding siblings ...)
2023-08-06 12:17 ` [PATCH v2 08/23] target/mips: " Helge Deller
@ 2023-08-06 12:17 ` Helge Deller
2023-08-06 12:17 ` [PATCH v2 10/23] target/riscv: " Helge Deller
` (13 subsequent siblings)
22 siblings, 0 replies; 27+ messages in thread
From: Helge Deller @ 2023-08-06 12:17 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Use the new MMU_INDEX() helper to specify the index of the CPUTLB which
should be used. Additionally, in a follow-up patch this helper allows
then to optimize the tcg code generation.
Signed-off-by: Helge Deller <deller@gmx.de>
---
target/openrisc/cpu.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h
index ce4d605eb7..c216f2fb77 100644
--- a/target/openrisc/cpu.h
+++ b/target/openrisc/cpu.h
@@ -50,9 +50,9 @@ struct OpenRISCCPUClass {
#define TARGET_INSN_START_EXTRA_WORDS 1
enum {
- MMU_NOMMU_IDX = 0,
- MMU_SUPERVISOR_IDX = 1,
- MMU_USER_IDX = 2,
+ MMU_NOMMU_IDX = MMU_INDEX(0),
+ MMU_SUPERVISOR_IDX = MMU_INDEX(1),
+ MMU_USER_IDX = MMU_INDEX(2),
};
#define SET_FP_CAUSE(reg, v) do {\
--
2.41.0
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH v2 10/23] target/riscv: Use MMU_INDEX() helper
2023-08-06 12:17 [PATCH v2 00/23] Introduce MMU_INDEX() Helge Deller
` (8 preceding siblings ...)
2023-08-06 12:17 ` [PATCH v2 09/23] target/openrisc: " Helge Deller
@ 2023-08-06 12:17 ` Helge Deller
2023-08-06 14:30 ` Richard Henderson
2023-08-06 12:17 ` [PATCH v2 11/23] target/s390x: " Helge Deller
` (12 subsequent siblings)
22 siblings, 1 reply; 27+ messages in thread
From: Helge Deller @ 2023-08-06 12:17 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Use the new MMU_INDEX() helper to specify the index of the CPUTLB which
should be used. Additionally, in a follow-up patch this helper allows
then to optimize the tcg code generation.
Signed-off-by: Helge Deller <deller@gmx.de>
---
target/riscv/cpu.h | 4 ++--
target/riscv/cpu_helper.c | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 6ea22e0eea..6aba1df64a 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -88,7 +88,7 @@ typedef enum {
EXT_STATUS_DIRTY,
} RISCVExtStatus;
-#define MMU_USER_IDX 3
+#define MMU_USER_IDX MMU_INDEX(3)
#define MAX_RISCV_PMPS (16)
@@ -446,7 +446,7 @@ void riscv_cpu_list(void);
void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp);
#define cpu_list riscv_cpu_list
-#define cpu_mmu_index riscv_cpu_mmu_index
+#define cpu_mmu_index(e,i) MMU_INDEX(riscv_cpu_mmu_index(e,i))
#ifndef CONFIG_USER_ONLY
void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 9f611d89bb..a8e6950217 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -107,7 +107,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
#else
flags = FIELD_DP32(flags, TB_FLAGS, PRIV, env->priv);
- flags |= cpu_mmu_index(env, 0);
+ flags |= riscv_cpu_mmu_index(env, 0);
fs = get_field(env->mstatus, MSTATUS_FS);
vs = get_field(env->mstatus, MSTATUS_VS);
--
2.41.0
^ permalink raw reply related [flat|nested] 27+ messages in thread
* Re: [PATCH v2 10/23] target/riscv: Use MMU_INDEX() helper
2023-08-06 12:17 ` [PATCH v2 10/23] target/riscv: " Helge Deller
@ 2023-08-06 14:30 ` Richard Henderson
2023-08-06 14:42 ` Helge Deller
0 siblings, 1 reply; 27+ messages in thread
From: Richard Henderson @ 2023-08-06 14:30 UTC (permalink / raw)
To: Helge Deller, qemu-devel
On 8/6/23 05:17, Helge Deller wrote:
> Use the new MMU_INDEX() helper to specify the index of the CPUTLB which
> should be used. Additionally, in a follow-up patch this helper allows
> then to optimize the tcg code generation.
>
> Signed-off-by: Helge Deller <deller@gmx.de>
> ---
> target/riscv/cpu.h | 4 ++--
> target/riscv/cpu_helper.c | 2 +-
> 2 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 6ea22e0eea..6aba1df64a 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -88,7 +88,7 @@ typedef enum {
> EXT_STATUS_DIRTY,
> } RISCVExtStatus;
>
> -#define MMU_USER_IDX 3
> +#define MMU_USER_IDX MMU_INDEX(3)
>
> #define MAX_RISCV_PMPS (16)
>
> @@ -446,7 +446,7 @@ void riscv_cpu_list(void);
> void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp);
>
> #define cpu_list riscv_cpu_list
> -#define cpu_mmu_index riscv_cpu_mmu_index
> +#define cpu_mmu_index(e,i) MMU_INDEX(riscv_cpu_mmu_index(e,i))
>
> #ifndef CONFIG_USER_ONLY
> void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index 9f611d89bb..a8e6950217 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -107,7 +107,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
> #else
> flags = FIELD_DP32(flags, TB_FLAGS, PRIV, env->priv);
>
> - flags |= cpu_mmu_index(env, 0);
> + flags |= riscv_cpu_mmu_index(env, 0);
> fs = get_field(env->mstatus, MSTATUS_FS);
> vs = get_field(env->mstatus, MSTATUS_VS);
This is the sort of non-obvious changes that I hoped to avoid by restricting all changes
to accel/tcg/cputlb.c.
r~
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v2 10/23] target/riscv: Use MMU_INDEX() helper
2023-08-06 14:30 ` Richard Henderson
@ 2023-08-06 14:42 ` Helge Deller
0 siblings, 0 replies; 27+ messages in thread
From: Helge Deller @ 2023-08-06 14:42 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
On 8/6/23 16:30, Richard Henderson wrote:
> On 8/6/23 05:17, Helge Deller wrote:
>> Use the new MMU_INDEX() helper to specify the index of the CPUTLB which
>> should be used. Additionally, in a follow-up patch this helper allows
>> then to optimize the tcg code generation.
>>
>> Signed-off-by: Helge Deller <deller@gmx.de>
>> ---
>> target/riscv/cpu.h | 4 ++--
>> target/riscv/cpu_helper.c | 2 +-
>> 2 files changed, 3 insertions(+), 3 deletions(-)
>>
>> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
>> index 6ea22e0eea..6aba1df64a 100644
>> --- a/target/riscv/cpu.h
>> +++ b/target/riscv/cpu.h
>> @@ -88,7 +88,7 @@ typedef enum {
>> EXT_STATUS_DIRTY,
>> } RISCVExtStatus;
>>
>> -#define MMU_USER_IDX 3
>> +#define MMU_USER_IDX MMU_INDEX(3)
>>
>> #define MAX_RISCV_PMPS (16)
>>
>> @@ -446,7 +446,7 @@ void riscv_cpu_list(void);
>> void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp);
>>
>> #define cpu_list riscv_cpu_list
>> -#define cpu_mmu_index riscv_cpu_mmu_index
>> +#define cpu_mmu_index(e,i) MMU_INDEX(riscv_cpu_mmu_index(e,i))
>>
>> #ifndef CONFIG_USER_ONLY
>> void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
>> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
>> index 9f611d89bb..a8e6950217 100644
>> --- a/target/riscv/cpu_helper.c
>> +++ b/target/riscv/cpu_helper.c
>> @@ -107,7 +107,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
>> #else
>> flags = FIELD_DP32(flags, TB_FLAGS, PRIV, env->priv);
>>
>> - flags |= cpu_mmu_index(env, 0);
>> + flags |= riscv_cpu_mmu_index(env, 0);
>> fs = get_field(env->mstatus, MSTATUS_FS);
>> vs = get_field(env->mstatus, MSTATUS_VS);
>
> This is the sort of non-obvious changes that I hoped to avoid by restricting all changes to accel/tcg/cputlb.c.
True.
And, since I've found some other missing pieces now too (e.g. in hppa)
I'm currently tempted to fully agree with you, that handling this
in accel/tcg/cputlb.c only is the better (and cleaner) solution.
I'll try you approach.
Helge
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH v2 11/23] target/s390x: Use MMU_INDEX() helper
2023-08-06 12:17 [PATCH v2 00/23] Introduce MMU_INDEX() Helge Deller
` (9 preceding siblings ...)
2023-08-06 12:17 ` [PATCH v2 10/23] target/riscv: " Helge Deller
@ 2023-08-06 12:17 ` Helge Deller
2023-08-06 12:17 ` [PATCH v2 12/23] target/sparc: " Helge Deller
` (11 subsequent siblings)
22 siblings, 0 replies; 27+ messages in thread
From: Helge Deller @ 2023-08-06 12:17 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Use the new MMU_INDEX() helper to specify the index of the CPUTLB which
should be used. Additionally, in a follow-up patch this helper allows
then to optimize the tcg code generation.
Signed-off-by: Helge Deller <deller@gmx.de>
---
target/s390x/cpu.h | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h
index eb5b65b7d3..05a4b7b299 100644
--- a/target/s390x/cpu.h
+++ b/target/s390x/cpu.h
@@ -38,7 +38,7 @@
#define TARGET_INSN_START_EXTRA_WORDS 2
-#define MMU_USER_IDX 0
+#define MMU_USER_IDX MMU_INDEX(0)
#define S390_MAX_CPUS 248
@@ -342,10 +342,10 @@ extern const VMStateDescription vmstate_s390_cpu;
#define CR14_CHANNEL_REPORT_SC 0x0000000010000000ULL
/* MMU */
-#define MMU_PRIMARY_IDX 0
-#define MMU_SECONDARY_IDX 1
-#define MMU_HOME_IDX 2
-#define MMU_REAL_IDX 3
+#define MMU_PRIMARY_IDX MMU_INDEX(0)
+#define MMU_SECONDARY_IDX MMU_INDEX(1)
+#define MMU_HOME_IDX MMU_INDEX(2)
+#define MMU_REAL_IDX MMU_INDEX(3)
static inline int cpu_mmu_index(CPUS390XState *env, bool ifetch)
{
--
2.41.0
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH v2 12/23] target/sparc: Use MMU_INDEX() helper
2023-08-06 12:17 [PATCH v2 00/23] Introduce MMU_INDEX() Helge Deller
` (10 preceding siblings ...)
2023-08-06 12:17 ` [PATCH v2 11/23] target/s390x: " Helge Deller
@ 2023-08-06 12:17 ` Helge Deller
2023-08-06 12:17 ` [PATCH v2 13/23] target/xtensa: " Helge Deller
` (10 subsequent siblings)
22 siblings, 0 replies; 27+ messages in thread
From: Helge Deller @ 2023-08-06 12:17 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Use the new MMU_INDEX() helper to specify the index of the CPUTLB which
should be used. Additionally, in a follow-up patch this helper allows
then to optimize the tcg code generation.
Signed-off-by: Helge Deller <deller@gmx.de>
---
target/sparc/cpu.h | 20 ++++++++++----------
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h
index 98044572f2..0c84033326 100644
--- a/target/sparc/cpu.h
+++ b/target/sparc/cpu.h
@@ -659,16 +659,16 @@ hwaddr cpu_get_phys_page_nofault(CPUSPARCState *env, target_ulong addr,
/* MMU modes definitions */
#if defined (TARGET_SPARC64)
-#define MMU_USER_IDX 0
-#define MMU_USER_SECONDARY_IDX 1
-#define MMU_KERNEL_IDX 2
-#define MMU_KERNEL_SECONDARY_IDX 3
-#define MMU_NUCLEUS_IDX 4
-#define MMU_PHYS_IDX 5
+#define MMU_USER_IDX MMU_INDEX(0)
+#define MMU_USER_SECONDARY_IDX MMU_INDEX(1)
+#define MMU_KERNEL_IDX MMU_INDEX(2)
+#define MMU_KERNEL_SECONDARY_IDX MMU_INDEX(3)
+#define MMU_NUCLEUS_IDX MMU_INDEX(4)
+#define MMU_PHYS_IDX MMU_INDEX(5)
#else
-#define MMU_USER_IDX 0
-#define MMU_KERNEL_IDX 1
-#define MMU_PHYS_IDX 2
+#define MMU_USER_IDX MMU_INDEX(0)
+#define MMU_KERNEL_IDX MMU_INDEX(1)
+#define MMU_PHYS_IDX MMU_INDEX(2)
#endif
#if defined (TARGET_SPARC64)
@@ -701,7 +701,7 @@ static inline int cpu_mmu_index(CPUSPARCState *env, bool ifetch)
if ((env->mmuregs[0] & MMU_E) == 0) { /* MMU disabled */
return MMU_PHYS_IDX;
} else {
- return env->psrs;
+ return MMU_INDEX(env->psrs);
}
#else
/* IMMU or DMMU disabled. */
--
2.41.0
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH v2 13/23] target/xtensa: Use MMU_INDEX() helper
2023-08-06 12:17 [PATCH v2 00/23] Introduce MMU_INDEX() Helge Deller
` (11 preceding siblings ...)
2023-08-06 12:17 ` [PATCH v2 12/23] target/sparc: " Helge Deller
@ 2023-08-06 12:17 ` Helge Deller
2023-08-06 12:17 ` [PATCH v2 14/23] target/arm: " Helge Deller
` (9 subsequent siblings)
22 siblings, 0 replies; 27+ messages in thread
From: Helge Deller @ 2023-08-06 12:17 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Use the new MMU_INDEX() helper to specify the index of the CPUTLB which
should be used. Additionally, in a follow-up patch this helper allows
then to optimize the tcg code generation.
Signed-off-by: Helge Deller <deller@gmx.de>
---
target/xtensa/cpu.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h
index 87fe992ba6..2f1349b13d 100644
--- a/target/xtensa/cpu.h
+++ b/target/xtensa/cpu.h
@@ -699,11 +699,11 @@ static inline uint32_t xtensa_replicate_windowstart(CPUXtensaState *env)
}
/* MMU modes definitions */
-#define MMU_USER_IDX 3
+#define MMU_USER_IDX MMU_INDEX(3)
static inline int cpu_mmu_index(CPUXtensaState *env, bool ifetch)
{
- return xtensa_get_cring(env);
+ return MMU_INDEX(xtensa_get_cring(env));
}
#define XTENSA_TBFLAG_RING_MASK 0x3
--
2.41.0
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH v2 14/23] target/arm: Use MMU_INDEX() helper
2023-08-06 12:17 [PATCH v2 00/23] Introduce MMU_INDEX() Helge Deller
` (12 preceding siblings ...)
2023-08-06 12:17 ` [PATCH v2 13/23] target/xtensa: " Helge Deller
@ 2023-08-06 12:17 ` Helge Deller
2023-08-06 14:31 ` Richard Henderson
2023-08-06 12:17 ` [PATCH v2 15/23] target/cris: " Helge Deller
` (8 subsequent siblings)
22 siblings, 1 reply; 27+ messages in thread
From: Helge Deller @ 2023-08-06 12:17 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Use the new MMU_INDEX() helper to specify the index of the CPUTLB which
should be used. Additionally, in a follow-up patch this helper allows
then to optimize the tcg code generation.
Signed-off-by: Helge Deller <deller@gmx.de>
---
target/arm/cpu.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 88e5accda6..16e18fb22a 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -2930,7 +2930,7 @@ typedef enum ARMMMUIdxBit {
#undef TO_CORE_BIT
-#define MMU_USER_IDX 0
+#define MMU_USER_IDX MMU_INDEX(0)
/* Indexes used when registering address spaces with cpu_address_space_init */
typedef enum ARMASIdx {
@@ -3166,7 +3166,7 @@ FIELD(TBFLAG_A64, NAA, 30, 1)
*/
static inline int cpu_mmu_index(CPUARMState *env, bool ifetch)
{
- return EX_TBFLAG_ANY(env->hflags, MMUIDX);
+ return MMU_INDEX(EX_TBFLAG_ANY(env->hflags, MMUIDX));
}
/**
--
2.41.0
^ permalink raw reply related [flat|nested] 27+ messages in thread
* Re: [PATCH v2 14/23] target/arm: Use MMU_INDEX() helper
2023-08-06 12:17 ` [PATCH v2 14/23] target/arm: " Helge Deller
@ 2023-08-06 14:31 ` Richard Henderson
0 siblings, 0 replies; 27+ messages in thread
From: Richard Henderson @ 2023-08-06 14:31 UTC (permalink / raw)
To: Helge Deller, qemu-devel
On 8/6/23 05:17, Helge Deller wrote:
> Use the new MMU_INDEX() helper to specify the index of the CPUTLB which
> should be used. Additionally, in a follow-up patch this helper allows
> then to optimize the tcg code generation.
>
> Signed-off-by: Helge Deller <deller@gmx.de>
> ---
> target/arm/cpu.h | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/target/arm/cpu.h b/target/arm/cpu.h
> index 88e5accda6..16e18fb22a 100644
> --- a/target/arm/cpu.h
> +++ b/target/arm/cpu.h
> @@ -2930,7 +2930,7 @@ typedef enum ARMMMUIdxBit {
>
> #undef TO_CORE_BIT
>
> -#define MMU_USER_IDX 0
> +#define MMU_USER_IDX MMU_INDEX(0)
>
> /* Indexes used when registering address spaces with cpu_address_space_init */
> typedef enum ARMASIdx {
> @@ -3166,7 +3166,7 @@ FIELD(TBFLAG_A64, NAA, 30, 1)
> */
> static inline int cpu_mmu_index(CPUARMState *env, bool ifetch)
> {
> - return EX_TBFLAG_ANY(env->hflags, MMUIDX);
> + return MMU_INDEX(EX_TBFLAG_ANY(env->hflags, MMUIDX));
> }
This cannot possibly work, since you've not changed any of the real mmu idx (ARMMMUIdx).
r~
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH v2 15/23] target/cris: Use MMU_INDEX() helper
2023-08-06 12:17 [PATCH v2 00/23] Introduce MMU_INDEX() Helge Deller
` (13 preceding siblings ...)
2023-08-06 12:17 ` [PATCH v2 14/23] target/arm: " Helge Deller
@ 2023-08-06 12:17 ` Helge Deller
2023-08-06 12:17 ` [PATCH v2 16/23] target/m68k: " Helge Deller
` (7 subsequent siblings)
22 siblings, 0 replies; 27+ messages in thread
From: Helge Deller @ 2023-08-06 12:17 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Use the new MMU_INDEX() helper to specify the index of the CPUTLB which
should be used. Additionally, in a follow-up patch this helper allows
then to optimize the tcg code generation.
Signed-off-by: Helge Deller <deller@gmx.de>
---
target/cris/cpu.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/cris/cpu.h b/target/cris/cpu.h
index 8e37c6e50d..4064a16564 100644
--- a/target/cris/cpu.h
+++ b/target/cris/cpu.h
@@ -248,10 +248,10 @@ enum {
#define CPU_RESOLVING_TYPE TYPE_CRIS_CPU
/* MMU modes definitions */
-#define MMU_USER_IDX 1
+#define MMU_USER_IDX MMU_INDEX(1)
static inline int cpu_mmu_index (CPUCRISState *env, bool ifetch)
{
- return !!(env->pregs[PR_CCS] & U_FLAG);
+ return MMU_INDEX(!!(env->pregs[PR_CCS] & U_FLAG));
}
/* Support function regs. */
--
2.41.0
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH v2 16/23] target/m68k: Use MMU_INDEX() helper
2023-08-06 12:17 [PATCH v2 00/23] Introduce MMU_INDEX() Helge Deller
` (14 preceding siblings ...)
2023-08-06 12:17 ` [PATCH v2 15/23] target/cris: " Helge Deller
@ 2023-08-06 12:17 ` Helge Deller
2023-08-06 12:17 ` [PATCH v2 17/23] target/microblaze: " Helge Deller
` (6 subsequent siblings)
22 siblings, 0 replies; 27+ messages in thread
From: Helge Deller @ 2023-08-06 12:17 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Use the new MMU_INDEX() helper to specify the index of the CPUTLB which
should be used. Additionally, in a follow-up patch this helper allows
then to optimize the tcg code generation.
Signed-off-by: Helge Deller <deller@gmx.de>
---
target/m68k/cpu.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h
index cf70282717..8321868506 100644
--- a/target/m68k/cpu.h
+++ b/target/m68k/cpu.h
@@ -571,11 +571,11 @@ enum {
#define cpu_list m68k_cpu_list
/* MMU modes definitions */
-#define MMU_KERNEL_IDX 0
-#define MMU_USER_IDX 1
+#define MMU_KERNEL_IDX MMU_INDEX(0)
+#define MMU_USER_IDX MMU_INDEX(1)
static inline int cpu_mmu_index (CPUM68KState *env, bool ifetch)
{
- return (env->sr & SR_S) == 0 ? 1 : 0;
+ return (env->sr & SR_S) == 0 ? MMU_USER_IDX : MMU_KERNEL_IDX;
}
bool m68k_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
--
2.41.0
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH v2 17/23] target/microblaze: Use MMU_INDEX() helper
2023-08-06 12:17 [PATCH v2 00/23] Introduce MMU_INDEX() Helge Deller
` (15 preceding siblings ...)
2023-08-06 12:17 ` [PATCH v2 16/23] target/m68k: " Helge Deller
@ 2023-08-06 12:17 ` Helge Deller
2023-08-06 12:17 ` [PATCH v2 18/23] target/m68k: " Helge Deller
` (5 subsequent siblings)
22 siblings, 0 replies; 27+ messages in thread
From: Helge Deller @ 2023-08-06 12:17 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Use the new MMU_INDEX() helper to specify the index of the CPUTLB which
should be used. Additionally, in a follow-up patch this helper allows
then to optimize the tcg code generation.
Signed-off-by: Helge Deller <deller@gmx.de>
---
target/microblaze/cpu.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
index f6cab6ce19..eed0d1d8ad 100644
--- a/target/microblaze/cpu.h
+++ b/target/microblaze/cpu.h
@@ -394,9 +394,9 @@ void mb_tcg_init(void);
#define CPU_RESOLVING_TYPE TYPE_MICROBLAZE_CPU
/* MMU modes definitions */
-#define MMU_NOMMU_IDX 0
-#define MMU_KERNEL_IDX 1
-#define MMU_USER_IDX 2
+#define MMU_NOMMU_IDX MMU_INDEX(0)
+#define MMU_KERNEL_IDX MMU_INDEX(1)
+#define MMU_USER_IDX MMU_INDEX(2)
/* See NB_MMU_MODES in cpu-defs.h. */
#include "exec/cpu-all.h"
--
2.41.0
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH v2 18/23] target/m68k: Use MMU_INDEX() helper
2023-08-06 12:17 [PATCH v2 00/23] Introduce MMU_INDEX() Helge Deller
` (16 preceding siblings ...)
2023-08-06 12:17 ` [PATCH v2 17/23] target/microblaze: " Helge Deller
@ 2023-08-06 12:17 ` Helge Deller
2023-08-06 12:17 ` [PATCH v2 19/23] target/ppc: " Helge Deller
` (4 subsequent siblings)
22 siblings, 0 replies; 27+ messages in thread
From: Helge Deller @ 2023-08-06 12:17 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Use the new MMU_INDEX() helper to specify the index of the CPUTLB which
should be used. Additionally, in a follow-up patch this helper allows
then to optimize the tcg code generation.
Signed-off-by: Helge Deller <deller@gmx.de>
---
target/nios2/cpu.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h
index 477a3161fd..77f9e3803e 100644
--- a/target/nios2/cpu.h
+++ b/target/nios2/cpu.h
@@ -277,8 +277,8 @@ void do_nios2_semihosting(CPUNios2State *env);
#define CPU_SAVE_VERSION 1
/* MMU modes definitions */
-#define MMU_SUPERVISOR_IDX 0
-#define MMU_USER_IDX 1
+#define MMU_SUPERVISOR_IDX MMU_INDEX(0)
+#define MMU_USER_IDX MMU_INDEX(1)
static inline int cpu_mmu_index(CPUNios2State *env, bool ifetch)
{
--
2.41.0
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH v2 19/23] target/ppc: Use MMU_INDEX() helper
2023-08-06 12:17 [PATCH v2 00/23] Introduce MMU_INDEX() Helge Deller
` (17 preceding siblings ...)
2023-08-06 12:17 ` [PATCH v2 18/23] target/m68k: " Helge Deller
@ 2023-08-06 12:17 ` Helge Deller
2023-08-06 12:17 ` [PATCH v2 20/23] target/rx: " Helge Deller
` (3 subsequent siblings)
22 siblings, 0 replies; 27+ messages in thread
From: Helge Deller @ 2023-08-06 12:17 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Use the new MMU_INDEX() helper to specify the index of the CPUTLB which
should be used. Additionally, in a follow-up patch this helper allows
then to optimize the tcg code generation.
Signed-off-by: Helge Deller <deller@gmx.de>
---
target/ppc/cpu.h | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 25fac9577a..dfd9ba2518 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -1474,13 +1474,14 @@ int ppc_dcr_write(ppc_dcr_t *dcr_env, int dcrn, uint32_t val);
#define cpu_list ppc_cpu_list
/* MMU modes definitions */
-#define MMU_USER_IDX 0
+#define MMU_USER_IDX MMU_INDEX(0)
static inline int cpu_mmu_index(CPUPPCState *env, bool ifetch)
{
#ifdef CONFIG_USER_ONLY
return MMU_USER_IDX;
#else
- return (env->hflags >> (ifetch ? HFLAGS_IMMU_IDX : HFLAGS_DMMU_IDX)) & 7;
+ int idx = (env->hflags >> (ifetch ? HFLAGS_IMMU_IDX : HFLAGS_DMMU_IDX)) & 7;
+ return MMU_INDEX(idx);
#endif
}
--
2.41.0
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH v2 20/23] target/rx: Use MMU_INDEX() helper
2023-08-06 12:17 [PATCH v2 00/23] Introduce MMU_INDEX() Helge Deller
` (18 preceding siblings ...)
2023-08-06 12:17 ` [PATCH v2 19/23] target/ppc: " Helge Deller
@ 2023-08-06 12:17 ` Helge Deller
2023-08-06 12:17 ` [PATCH v2 21/23] target/sh4: " Helge Deller
` (2 subsequent siblings)
22 siblings, 0 replies; 27+ messages in thread
From: Helge Deller @ 2023-08-06 12:17 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Use the new MMU_INDEX() helper to specify the index of the CPUTLB which
should be used. Additionally, in a follow-up patch this helper allows
then to optimize the tcg code generation.
Signed-off-by: Helge Deller <deller@gmx.de>
---
target/rx/cpu.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/rx/cpu.h b/target/rx/cpu.h
index 7f03ffcfed..bb19a456d3 100644
--- a/target/rx/cpu.h
+++ b/target/rx/cpu.h
@@ -154,7 +154,7 @@ static inline void cpu_get_tb_cpu_state(CPURXState *env, vaddr *pc,
static inline int cpu_mmu_index(CPURXState *env, bool ifetch)
{
- return 0;
+ return MMU_INDEX(0);
}
static inline uint32_t rx_cpu_pack_psw(CPURXState *env)
--
2.41.0
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH v2 21/23] target/sh4: Use MMU_INDEX() helper
2023-08-06 12:17 [PATCH v2 00/23] Introduce MMU_INDEX() Helge Deller
` (19 preceding siblings ...)
2023-08-06 12:17 ` [PATCH v2 20/23] target/rx: " Helge Deller
@ 2023-08-06 12:17 ` Helge Deller
2023-08-06 12:17 ` [PATCH v2 22/23] target/tricore: " Helge Deller
2023-08-06 12:17 ` [PATCH v2 23/23] cpu-defs.h: Reduce generated code size by inverting MMU_INDEX() Helge Deller
22 siblings, 0 replies; 27+ messages in thread
From: Helge Deller @ 2023-08-06 12:17 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Use the new MMU_INDEX() helper to specify the index of the CPUTLB which
should be used. Additionally, in a follow-up patch this helper allows
then to optimize the tcg code generation.
Signed-off-by: Helge Deller <deller@gmx.de>
---
target/sh4/cpu.h | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h
index 1399d3840f..9adb1bb893 100644
--- a/target/sh4/cpu.h
+++ b/target/sh4/cpu.h
@@ -260,15 +260,16 @@ void cpu_load_tlb(CPUSH4State * env);
#define cpu_list sh4_cpu_list
/* MMU modes definitions */
-#define MMU_USER_IDX 1
+#define MMU_KERNEL_IDX MMU_INDEX(0)
+#define MMU_USER_IDX MMU_INDEX(1)
static inline int cpu_mmu_index (CPUSH4State *env, bool ifetch)
{
/* The instruction in a RTE delay slot is fetched in privileged
mode, but executed in user mode. */
if (ifetch && (env->flags & TB_FLAG_DELAY_SLOT_RTE)) {
- return 0;
+ return MMU_KERNEL_IDX;
} else {
- return (env->sr & (1u << SR_MD)) == 0 ? 1 : 0;
+ return (env->sr & (1u << SR_MD)) == 0 ? MMU_USER_IDX : MMU_KERNEL_IDX;
}
}
--
2.41.0
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH v2 22/23] target/tricore: Use MMU_INDEX() helper
2023-08-06 12:17 [PATCH v2 00/23] Introduce MMU_INDEX() Helge Deller
` (20 preceding siblings ...)
2023-08-06 12:17 ` [PATCH v2 21/23] target/sh4: " Helge Deller
@ 2023-08-06 12:17 ` Helge Deller
2023-08-06 12:17 ` [PATCH v2 23/23] cpu-defs.h: Reduce generated code size by inverting MMU_INDEX() Helge Deller
22 siblings, 0 replies; 27+ messages in thread
From: Helge Deller @ 2023-08-06 12:17 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Use the new MMU_INDEX() helper to specify the index of the CPUTLB which
should be used. Additionally, in a follow-up patch this helper allows
then to optimize the tcg code generation.
Signed-off-by: Helge Deller <deller@gmx.de>
---
target/tricore/cpu.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h
index 3708405be8..6c8ba27737 100644
--- a/target/tricore/cpu.h
+++ b/target/tricore/cpu.h
@@ -366,7 +366,7 @@ int tricore_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n);
void fpu_set_state(CPUTriCoreState *env);
-#define MMU_USER_IDX 2
+#define MMU_USER_IDX MMU_INDEX(2)
void tricore_cpu_list(void);
@@ -374,7 +374,7 @@ void tricore_cpu_list(void);
static inline int cpu_mmu_index(CPUTriCoreState *env, bool ifetch)
{
- return 0;
+ return MMU_INDEX(0);
}
#include "exec/cpu-all.h"
--
2.41.0
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH v2 23/23] cpu-defs.h: Reduce generated code size by inverting MMU_INDEX()
2023-08-06 12:17 [PATCH v2 00/23] Introduce MMU_INDEX() Helge Deller
` (21 preceding siblings ...)
2023-08-06 12:17 ` [PATCH v2 22/23] target/tricore: " Helge Deller
@ 2023-08-06 12:17 ` Helge Deller
22 siblings, 0 replies; 27+ messages in thread
From: Helge Deller @ 2023-08-06 12:17 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
The MMU is placed within CPUNegativeOffsetState, which means the
smallest negative offsets are at the end of the struct (see comment for
struct CPUTLB).
But in target/cpu.h usually MMU indexes in the range 0-8 are used, which
means that the negative offsets are bigger than if MMU indexes 9-15
would have been used.
This patch inverts the given MMU index, so that the MMU indices now
count down from (MMU_USER_IDX-1) to 0 and thus the tcg will see smaller
negative offsets.
When looking at the generated code, for every memory-access in the guest
the x86-64 tcg generated up to now:
IN:
0x000ebdf5: 8b 04 24 movl (%esp), %eax
OUT:
...
0x003619: 48 23 bd 10 ff ff ff andq -0xf0(%rbp), %rdi
0x003620: 48 03 bd 18 ff ff ff addq -0xe8(%rbp), %rdi
...
With the smaller negative offset it will now instead generate:
OUT:
...
0x003499: 48 23 7d c0 andq -0x40(%rbp), %rdi
0x00349d: 48 03 7d c8 addq -0x38(%rbp), %rdi
So, every memory acces in the guest now saves 6 bytes (=2 * 3)
of instruction code in the fast path.
Overall, this patch reduces the generated instruction size by ~3%
and may improve overall performance.
Signed-off-by: Helge Deller <deller@gmx.de>
---
include/exec/cpu-defs.h | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h
index 07bcdd38b2..7ba0481bc4 100644
--- a/include/exec/cpu-defs.h
+++ b/include/exec/cpu-defs.h
@@ -62,8 +62,13 @@
/*
* MMU_INDEX() helper to specify MMU index.
+ *
+ * Inverse the number here to count downwards from NB_MMU_MODES-1 to 0. Since
+ * the MMU is placed within CPUNegativeOffsetState, this makes the negative
+ * offsets smaller for which the tcg backend will generate shorter instruction
+ * sequencies to access the MMU.
*/
-#define MMU_INDEX(n) (n)
+#define MMU_INDEX(n) (NB_MMU_MODES - 1 - (n))
#if defined(CONFIG_SOFTMMU) && defined(CONFIG_TCG)
#include "exec/tlb-common.h"
--
2.41.0
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