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Tue, 09 Jan 2024 00:41:13 -0800 (PST) Message-ID: Date: Tue, 9 Jan 2024 19:40:59 +1100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 26/35] target/arm: Implement FEAT_NV2 redirection of sysregs to RAM Content-Language: en-US To: Peter Maydell Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org References: <20231218113305.2511480-1-peter.maydell@linaro.org> <20231218113305.2511480-27-peter.maydell@linaro.org> <88dcdb40-2fa3-449e-a3f7-41d75269a968@linaro.org> From: Richard Henderson In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 1/5/24 03:23, Peter Maydell wrote: > On Wed, 27 Dec 2023 at 23:55, Richard Henderson > wrote: >> >> On 12/18/23 22:32, Peter Maydell wrote: >>> + if (s->nv && s->nv2 && ri->nv2_redirect_offset) { >> >> Again, s->nv test is redundant. > > Fixed, thanks. > >>> + /* >>> + * Some registers always redirect to memory; some only do so if >>> + * HCR_EL2.NV1 is 0, and some only if NV1 is 1 (these come in >>> + * pairs which share an offset; see the table in R_CSRPQ). >>> + */ >>> + if (ri->nv2_redirect_offset & NV2_REDIR_NV1) { >>> + nv2_mem_redirect = s->nv1; >>> + } else if (ri->nv2_redirect_offset & NV2_REDIR_NO_NV1) { >>> + nv2_mem_redirect = !s->nv1; >>> + } else { >>> + nv2_mem_redirect = true; >>> + } >> >> I wondered if it would be clearer with the "both" case having both bits set. While I see >> that the first defined offset is 0x20, offset 0x00 is still reserved and *could* be used. >> At which point ri->nv2_redirect_offset would need a non-zero value for a zero offset. >> >> Maybe clearer as >> >> nv2_mem_redirect = (ri->nv2_redirect_offset & >> (s->nv1 ? NV2_REDIR_NV1_1 : NV2_REDIR_NV1_0)); >> >> ? >> >> This is more verbose for the (common?) case of redirect regardless of nv1, so maybe not. > > Yes, my motivation for the notation I used is that I wanted to > make the specification of the cpreg structs in the common case > simple and not too long-winded. If offset 0 does ever get > allocated, we'll have to come back and revisit this. But > new entries clearly seem to be being allocated at the other > end of the table, so I think our chances are good... > >>> + if (s->nv2_mem_be) { >>> + mop |= MO_BE; >>> + } >> >> MO_BSWAP is host dependent -- needs >> >> mop |= (s->nv2_mem_be ? MO_BE : MO_LE); > > Fixed. > > With those two fixes, can I have a reviewed-by? This is the > only patch without one, and all the fixes seem to me like > very minor things not worth sending out a full v2 for. Reviewed-by: Richard Henderson r~