qemu-devel.nongnu.org archive mirror
 help / color / mirror / Atom feed
From: Richard Henderson <richard.henderson@linaro.org>
To: "Philippe Mathieu-Daudé" <f4bug@amsat.org>,
	"WANG Xuerui" <git@xen0n.name>,
	qemu-devel@nongnu.org
Cc: Peter Maydell <peter.maydell@linaro.org>,
	Laurent Vivier <laurent@vivier.eu>
Subject: Re: [PATCH v5 09/30] tcg/loongarch64: Implement tcg_out_mov and tcg_out_movi
Date: Sat, 25 Sep 2021 10:04:30 -0400	[thread overview]
Message-ID: <dd22f801-6d96-3dc6-3a51-2d5adb21d80c@linaro.org> (raw)
In-Reply-To: <b1b97929-ef62-72ec-609f-bd84c49481d1@amsat.org>

On 9/25/21 5:54 AM, Philippe Mathieu-Daudé wrote:
>> +    /* High bits must be set; load with lu12i.w + optional ori.  */
>> +    tcg_target_long hi12 = sextreg(val, 12, 20);
> 
> Please declare variables in function prologue.

Ah, true.  Officially, that's qemu coding style.  I tend to overlook it because I don't 
like the rule.


>> +    tcg_out_opc_lu12i_w(s, rd, hi12);
>> +    if (lo != 0) {
>> +        tcg_out_opc_ori(s, rd, rd, lo & 0xfff);
> 
> Isn't lo already 12-bit? Why the mask?

lo was extracted signed, for addi; ori wants the value unsigned.
The value range asserts in tcg_out_opc_* will notice the difference.

>> +    /* Slow path.  Initialize the low 32 bits, then concat high bits.  */
>> +    tcg_out_movi_i32(s, rd, val);
>> +
>> +    bool rd_high_bits_are_ones = (int32_t)val < 0;
> 
> Declare in prologue, however this is hard to read. KISS:

If anything was to change here, I think I'd simply re-use "lo":

     lo = (int32_t)val;

and then check lo < 0 rather than rd_high_bits_are_ones as a boolean.

>> +        rd_high_bits_are_ones = hi32 < 0;
> 
> Again KISS:
> 
>             if (hi32 < 0) {
>                 rd_high_bits_are_ones = true;
>             }

This is certainly not KISS, and also wrong.  We would want an unconditional write to 
rd_high_bits_are_ones.  Although if there were any change,

     lo = hi32.

so that, again, we test lo < 0 for hi52.


r~


  reply	other threads:[~2021-09-25 14:07 UTC|newest]

Thread overview: 58+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-09-24 17:24 [PATCH v5 00/30] LoongArch64 port of QEMU TCG WANG Xuerui
2021-09-24 17:24 ` [PATCH v5 01/30] elf: Add machine type value for LoongArch WANG Xuerui
2021-09-24 17:24 ` [PATCH v5 02/30] MAINTAINERS: Add tcg/loongarch64 entry with myself as maintainer WANG Xuerui
2021-09-24 17:25 ` [PATCH v5 03/30] tcg/loongarch64: Add the tcg-target.h file WANG Xuerui
2021-09-24 17:25 ` [PATCH v5 04/30] tcg/loongarch64: Add generated instruction opcodes and encoding helpers WANG Xuerui
2021-09-25  3:51   ` WANG Xuerui
2021-09-25 14:20     ` Richard Henderson
2021-09-25 14:31       ` Philippe Mathieu-Daudé
2021-09-25 15:20         ` Richard Henderson
2021-09-25 17:11           ` WANG Xuerui
2021-09-25 17:24             ` Philippe Mathieu-Daudé
2021-09-25 16:19       ` WANG Xuerui
2021-09-24 17:25 ` [PATCH v5 05/30] tcg/loongarch64: Add register names, allocation order and input/output sets WANG Xuerui
2021-09-24 17:25 ` [PATCH v5 06/30] tcg/loongarch64: Define the operand constraints WANG Xuerui
2021-09-25  9:39   ` Philippe Mathieu-Daudé
2021-09-24 17:25 ` [PATCH v5 07/30] tcg/loongarch64: Implement necessary relocation operations WANG Xuerui
2021-09-24 17:25 ` [PATCH v5 08/30] tcg/loongarch64: Implement the memory barrier op WANG Xuerui
2021-09-25  9:40   ` Philippe Mathieu-Daudé
2021-09-24 17:25 ` [PATCH v5 09/30] tcg/loongarch64: Implement tcg_out_mov and tcg_out_movi WANG Xuerui
2021-09-25  9:54   ` Philippe Mathieu-Daudé
2021-09-25 14:04     ` Richard Henderson [this message]
2021-09-25 17:05       ` Philippe Mathieu-Daudé
2021-09-25 16:47     ` WANG Xuerui
2021-09-24 17:25 ` [PATCH v5 10/30] tcg/loongarch64: Implement goto_ptr WANG Xuerui
2021-09-24 17:25 ` [PATCH v5 11/30] tcg/loongarch64: Implement sign-/zero-extension ops WANG Xuerui
2021-09-25  9:58   ` Philippe Mathieu-Daudé
2021-09-24 17:25 ` [PATCH v5 12/30] tcg/loongarch64: Implement not/and/or/xor/nor/andc/orc ops WANG Xuerui
2021-09-25  9:59   ` Philippe Mathieu-Daudé
2021-09-24 17:25 ` [PATCH v5 13/30] tcg/loongarch64: Implement deposit/extract ops WANG Xuerui
2021-09-24 17:25 ` [PATCH v5 14/30] tcg/loongarch64: Implement bswap{16,32,64} ops WANG Xuerui
2021-09-24 17:25 ` [PATCH v5 15/30] tcg/loongarch64: Implement clz/ctz ops WANG Xuerui
2021-09-24 17:25 ` [PATCH v5 16/30] tcg/loongarch64: Implement shl/shr/sar/rotl/rotr ops WANG Xuerui
2021-09-25 10:05   ` Philippe Mathieu-Daudé
2021-09-25 14:09     ` Richard Henderson
2021-09-25 14:18       ` Philippe Mathieu-Daudé
2021-09-24 17:25 ` [PATCH v5 17/30] tcg/loongarch64: Implement add/sub ops WANG Xuerui
2021-09-25 10:02   ` Philippe Mathieu-Daudé
2021-09-24 17:25 ` [PATCH v5 18/30] tcg/loongarch64: Implement mul/mulsh/muluh/div/divu/rem/remu ops WANG Xuerui
2021-09-25 10:06   ` Philippe Mathieu-Daudé
2021-09-24 17:25 ` [PATCH v5 19/30] tcg/loongarch64: Implement br/brcond ops WANG Xuerui
2021-09-25 10:13   ` Philippe Mathieu-Daudé
2021-09-25 14:12     ` Richard Henderson
2021-09-25 14:38       ` Philippe Mathieu-Daudé
2021-09-24 17:25 ` [PATCH v5 20/30] tcg/loongarch64: Implement setcond ops WANG Xuerui
2021-09-24 17:25 ` [PATCH v5 21/30] tcg/loongarch64: Implement tcg_out_call WANG Xuerui
2021-09-24 17:25 ` [PATCH v5 22/30] tcg/loongarch64: Implement simple load/store ops WANG Xuerui
2021-09-25 10:17   ` Philippe Mathieu-Daudé
2021-09-24 17:25 ` [PATCH v5 23/30] tcg/loongarch64: Add softmmu load/store helpers, implement qemu_ld/qemu_st ops WANG Xuerui
2021-09-24 23:59   ` Richard Henderson
2021-09-24 17:25 ` [PATCH v5 24/30] tcg/loongarch64: Implement tcg_target_qemu_prologue WANG Xuerui
2021-09-24 17:25 ` [PATCH v5 25/30] tcg/loongarch64: Implement exit_tb/goto_tb WANG Xuerui
2021-09-24 17:25 ` [PATCH v5 26/30] tcg/loongarch64: Implement tcg_target_init WANG Xuerui
2021-09-24 17:25 ` [PATCH v5 27/30] tcg/loongarch64: Register the JIT WANG Xuerui
2021-09-24 17:25 ` [PATCH v5 28/30] linux-user: Add safe syscall handling for loongarch64 hosts WANG Xuerui
2021-09-24 17:25 ` [PATCH v5 29/30] accel/tcg/user-exec: Implement CPU-specific signal handler " WANG Xuerui
2021-09-25 10:25   ` Philippe Mathieu-Daudé
2021-09-24 17:25 ` [PATCH v5 30/30] configure, meson.build: Mark support " WANG Xuerui
2021-09-25 10:28   ` Philippe Mathieu-Daudé

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=dd22f801-6d96-3dc6-3a51-2d5adb21d80c@linaro.org \
    --to=richard.henderson@linaro.org \
    --cc=f4bug@amsat.org \
    --cc=git@xen0n.name \
    --cc=laurent@vivier.eu \
    --cc=peter.maydell@linaro.org \
    --cc=qemu-devel@nongnu.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).