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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-40fc6921b7dsm17448312f8f.42.2025.09.29.03.26.43 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 29 Sep 2025 03:26:43 -0700 (PDT) Message-ID: Date: Mon, 29 Sep 2025 12:26:42 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v6 00/47] AMD Versal Gen 2 support Content-Language: en-US To: Luc Michel , qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: Peter Maydell , Francisco Iglesias , "Edgar E . Iglesias" , Alistair Francis , Frederic Konrad , Sai Pavan Boddu References: <20250926070806.292065-1-luc.michel@amd.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: <20250926070806.292065-1-luc.michel@amd.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=philmd@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 26/9/25 09:07, Luc Michel wrote: > Francisco Iglesias (1): > hw/intc/arm_gicv3: Introduce a 'first-cpu-index' property > > Luc Michel (46): > hw/arm/xlnx-versal: split the xlnx-versal type > hw/arm/xlnx-versal: prepare for FDT creation > hw/arm/xlnx-versal: uart: refactor creation > hw/arm/xlnx-versal: canfd: refactor creation > hw/arm/xlnx-versal: sdhci: refactor creation > hw/arm/xlnx-versal: gem: refactor creation > hw/arm/xlnx-versal: adma: refactor creation > hw/arm/xlnx-versal: xram: refactor creation > hw/arm/xlnx-versal: usb: refactor creation > hw/arm/xlnx-versal: efuse: refactor creation > hw/arm/xlnx-versal: ospi: refactor creation > hw/arm/xlnx-versal: VersalMap: add support for OR'ed IRQs > hw/arm/xlnx-versal: PMC IOU SCLR: refactor creation > hw/arm/xlnx-versal: bbram: refactor creation > hw/arm/xlnx-versal: trng: refactor creation > hw/arm/xlnx-versal: rtc: refactor creation > hw/arm/xlnx-versal: cfu: refactor creation > hw/arm/xlnx-versal: crl: refactor creation > hw/arm/xlnx-versal-virt: virtio: refactor creation > hw/arm/xlnx-versal: refactor CPU cluster creation > hw/arm/xlnx-versal: add the mp_affinity property to the CPU mapping > hw/arm/xlnx-versal: instantiate the GIC ITS in the APU > hw/arm/xlnx-versal: add support for multiple GICs > hw/arm/xlnx-versal: add support for GICv2 > hw/arm/xlnx-versal: rpu: refactor creation > hw/arm/xlnx-versal: ocm: refactor creation > hw/arm/xlnx-versal: ddr: refactor creation > hw/arm/xlnx-versal: add the versal_get_num_cpu accessor > hw/misc/xlnx-versal-crl: remove unnecessary include directives > hw/misc/xlnx-versal-crl: split into base/concrete classes > hw/misc/xlnx-versal-crl: refactor device reset logic > hw/arm/xlnx-versal: reconnect the CRL to the other devices > hw/arm/xlnx-versal: use hw/arm/bsa.h for timer IRQ indices > hw/arm/xlnx-versal: tidy up > hw/misc/xlnx-versal-crl: add the versal2 version > hw/arm/xlnx-versal: add a per_cluster_gic switch to > VersalCpuClusterMap > hw/arm/xlnx-versal: add the target field in IRQ descriptor > target/arm/tcg/cpu64: add the cortex-a78ae CPU > hw/arm/xlnx-versal: add versal2 SoC > hw/arm/xlnx-versal-virt: rename the machine to amd-versal-virt > hw/arm/xlnx-versal-virt: split into base/concrete classes > hw/arm/xlnx-versal-virt: tidy up > docs/system/arm/xlnx-versal-virt: update supported devices > docs/system/arm/xlnx-versal-virt: add a note about dumpdtb > hw/arm/xlnx-versal-virt: add the xlnx-versal2-virt machine > tests/functional/test_aarch64_xlnx_versal: test the versal2 machine Series: Tested-by: Philippe Mathieu-Daudé