From: Richard Henderson <richard.henderson@linaro.org>
To: Alistair Francis <alistair.francis@wdc.com>,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: alistair23@gmail.com, bmeng.cn@gmail.com, palmer@dabbelt.com
Subject: Re: [PATCH v1 5/5] hw/intc: ibex_timer: Convert the timer to use RISC-V CPU GPIO lines
Date: Fri, 9 Jul 2021 08:43:55 -0700 [thread overview]
Message-ID: <dd6cc6eb-ff90-d7f3-9f0f-e35f9691554d@linaro.org> (raw)
In-Reply-To: <85c77d5c22719a8a93561f5fbe4d0bc0d63b6266.1625801410.git.alistair.francis@wdc.com>
On 7/8/21 8:31 PM, Alistair Francis wrote:
> @@ -48,5 +48,7 @@ struct IbexTimerState {
> uint32_t timebase_freq;
>
> qemu_irq irq;
> +
> + qemu_irq m_timer_irqs;
The plural here is a bit misleading. Otherwise,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
next prev parent reply other threads:[~2021-07-09 15:45 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-09 3:30 [PATCH v1 1/5] target/riscv: Expose interrupt pending bits as GPIO lines Alistair Francis
2021-07-09 3:30 ` [PATCH v1 2/5] hw/intc: sifive_clint: Use RISC-V CPU " Alistair Francis
2021-07-09 15:36 ` Richard Henderson
2021-07-12 4:49 ` Alistair Francis
2021-07-13 4:05 ` Anup Patel
2021-07-14 6:11 ` Alistair Francis
2021-07-22 12:15 ` Anup Patel
2021-07-09 3:31 ` [PATCH v1 3/5] hw/intc: ibex_plic: Convert the PLIC to use " Alistair Francis
2021-07-09 7:26 ` Philippe Mathieu-Daudé
2021-07-09 15:39 ` Richard Henderson
2021-07-09 3:31 ` [PATCH v1 4/5] hw/intc: sifive_plic: " Alistair Francis
2021-07-09 7:26 ` Philippe Mathieu-Daudé
2021-07-09 15:41 ` Richard Henderson
2021-07-13 4:31 ` Anup Patel
2021-07-13 5:08 ` Anup Patel
2021-07-09 3:31 ` [PATCH v1 5/5] hw/intc: ibex_timer: Convert the timer " Alistair Francis
2021-07-09 7:26 ` Philippe Mathieu-Daudé
2021-07-09 15:43 ` Richard Henderson [this message]
2021-07-09 7:25 ` [PATCH v1 1/5] target/riscv: Expose interrupt pending bits as " Philippe Mathieu-Daudé
2021-07-09 15:20 ` Richard Henderson
2021-07-10 14:40 ` Bin Meng
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