From: CLEMENT MATHIEU--DRIF <clement.mathieu--drif@eviden.com>
To: Zhenzhong Duan <zhenzhong.duan@intel.com>,
"qemu-devel@nongnu.org" <qemu-devel@nongnu.org>
Cc: "alex.williamson@redhat.com" <alex.williamson@redhat.com>,
"clg@redhat.com" <clg@redhat.com>,
"eric.auger@redhat.com" <eric.auger@redhat.com>,
"mst@redhat.com" <mst@redhat.com>,
"peterx@redhat.com" <peterx@redhat.com>,
"jasowang@redhat.com" <jasowang@redhat.com>,
"jgg@nvidia.com" <jgg@nvidia.com>,
"nicolinc@nvidia.com" <nicolinc@nvidia.com>,
"joao.m.martins@oracle.com" <joao.m.martins@oracle.com>,
"kevin.tian@intel.com" <kevin.tian@intel.com>,
"yi.l.liu@intel.com" <yi.l.liu@intel.com>,
"chao.p.peng@intel.com" <chao.p.peng@intel.com>,
Yi Sun <yi.y.sun@linux.intel.com>,
Marcel Apfelbaum <marcel.apfelbaum@gmail.com>,
Paolo Bonzini <pbonzini@redhat.com>,
Richard Henderson <richard.henderson@linaro.org>,
Eduardo Habkost <eduardo@habkost.net>
Subject: Re: [PATCH v1 14/17] intel_iommu: piotlb invalidation should notify unmap
Date: Wed, 24 Jul 2024 06:04:25 +0000 [thread overview]
Message-ID: <dd6cf2fc-a18d-4730-a351-be4057b6fb31@eviden.com> (raw)
In-Reply-To: <700f34b1-d020-4a1f-86d0-878a0628cc5e@eviden.com>
On 24/07/2024 07:45, CLEMENT MATHIEU--DRIF wrote:
> Maybe I'm missing something but why do we invalidate device IOTLB
> upon piotlb receipt of a regular IOTLB inv desc?
> I don't get why we don't wait for a device IOTLB inv desc?
I thought you were planning to remove that after the last rfc version
>
> On 18/07/2024 10:16, Zhenzhong Duan wrote:
>> Caution: External email. Do not open attachments or click links, unless this email comes from a known sender and you know the content is safe.
>>
>>
>> This is used by some emulated devices which caches address
>> translation result. When piotlb invalidation issued in guest,
>> those caches should be refreshed.
>>
>> Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
>> Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
>> ---
>> hw/i386/intel_iommu.c | 35 ++++++++++++++++++++++++++++++++++-
>> 1 file changed, 34 insertions(+), 1 deletion(-)
>>
>> diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
>> index 8b66d6cfa5..c0116497b1 100644
>> --- a/hw/i386/intel_iommu.c
>> +++ b/hw/i386/intel_iommu.c
>> @@ -2910,7 +2910,7 @@ static void vtd_piotlb_pasid_invalidate(IntelIOMMUState *s,
>> continue;
>> }
>>
>> - if (!s->scalable_modern) {
>> + if (!s->scalable_modern || !vtd_as_has_map_notifier(vtd_as)) {
>> vtd_address_space_sync(vtd_as);
>> }
>> }
>> @@ -2922,6 +2922,9 @@ static void vtd_piotlb_page_invalidate(IntelIOMMUState *s, uint16_t domain_id,
>> bool ih)
>> {
>> VTDIOTLBPageInvInfo info;
>> + VTDAddressSpace *vtd_as;
>> + VTDContextEntry ce;
>> + hwaddr size = (1 << am) * VTD_PAGE_SIZE;
>>
>> info.domain_id = domain_id;
>> info.pasid = pasid;
>> @@ -2932,6 +2935,36 @@ static void vtd_piotlb_page_invalidate(IntelIOMMUState *s, uint16_t domain_id,
>> g_hash_table_foreach_remove(s->iotlb,
>> vtd_hash_remove_by_page_piotlb, &info);
>> vtd_iommu_unlock(s);
>> +
>> + QLIST_FOREACH(vtd_as, &s->vtd_as_with_notifiers, next) {
>> + if (!vtd_dev_to_context_entry(s, pci_bus_num(vtd_as->bus),
>> + vtd_as->devfn, &ce) &&
>> + domain_id == vtd_get_domain_id(s, &ce, vtd_as->pasid)) {
>> + uint32_t rid2pasid = VTD_CE_GET_RID2PASID(&ce);
>> + IOMMUTLBEvent event;
>> +
>> + if ((vtd_as->pasid != PCI_NO_PASID || pasid != rid2pasid) &&
>> + vtd_as->pasid != pasid) {
>> + continue;
>> + }
>> +
>> + /*
>> + * Page-Selective-within-PASID PASID-based-IOTLB Invalidation
>> + * does not flush stage-2 entries. See spec section 6.5.2.4
>> + */
>> + if (!s->scalable_modern) {
>> + continue;
>> + }
>> +
>> + event.type = IOMMU_NOTIFIER_UNMAP;
>> + event.entry.target_as = &address_space_memory;
>> + event.entry.iova = addr;
>> + event.entry.perm = IOMMU_NONE;
>> + event.entry.addr_mask = size - 1;
>> + event.entry.translated_addr = 0;
>> + memory_region_notify_iommu(&vtd_as->iommu, 0, event);
>> + }
>> + }
>> }
>>
>> static bool vtd_process_piotlb_desc(IntelIOMMUState *s,
>> --
>> 2.34.1
>>
next prev parent reply other threads:[~2024-07-24 6:05 UTC|newest]
Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-07-18 8:16 [PATCH v1 00/17] intel_iommu: Enable stage-1 translation for emulated device Zhenzhong Duan
2024-07-18 8:16 ` [PATCH v1 01/17] intel_iommu: Use the latest fault reasons defined by spec Zhenzhong Duan
2024-07-23 7:12 ` CLEMENT MATHIEU--DRIF
2024-07-29 7:39 ` Yi Liu
2024-07-29 8:42 ` Michael S. Tsirkin
2024-07-29 9:39 ` Yi Liu
2024-07-18 8:16 ` [PATCH v1 02/17] intel_iommu: Make pasid entry type check accurate Zhenzhong Duan
2024-07-18 9:06 ` CLEMENT MATHIEU--DRIF
2024-07-18 8:16 ` [PATCH v1 03/17] intel_iommu: Add a placeholder variable for scalable modern mode Zhenzhong Duan
2024-07-18 9:02 ` CLEMENT MATHIEU--DRIF
2024-07-19 2:47 ` Duan, Zhenzhong
2024-07-19 3:22 ` Yi Liu
2024-07-19 3:37 ` Duan, Zhenzhong
2024-07-19 3:39 ` Duan, Zhenzhong
2024-07-19 4:26 ` CLEMENT MATHIEU--DRIF
2024-07-23 7:12 ` CLEMENT MATHIEU--DRIF
2024-07-23 8:50 ` Duan, Zhenzhong
2024-07-19 4:21 ` CLEMENT MATHIEU--DRIF
2024-07-18 8:16 ` [PATCH v1 04/17] intel_iommu: Flush stage-2 cache in PADID-selective PASID-based iotlb invalidation Zhenzhong Duan
2024-07-23 16:02 ` CLEMENT MATHIEU--DRIF
2024-07-24 2:59 ` Duan, Zhenzhong
2024-07-24 5:16 ` CLEMENT MATHIEU--DRIF
2024-07-24 5:19 ` Duan, Zhenzhong
2024-07-18 8:16 ` [PATCH v1 05/17] intel_iommu: Rename slpte to pte Zhenzhong Duan
2024-07-18 8:16 ` [PATCH v1 06/17] intel_iommu: Implement stage-1 translation Zhenzhong Duan
2024-07-18 8:16 ` [PATCH v1 07/17] intel_iommu: Check if the input address is canonical Zhenzhong Duan
2024-07-18 8:16 ` [PATCH v1 08/17] intel_iommu: Set accessed and dirty bits during first stage translation Zhenzhong Duan
2024-07-18 8:16 ` [PATCH v1 09/17] intel_iommu: Flush stage-1 cache in iotlb invalidation Zhenzhong Duan
2024-07-23 7:12 ` CLEMENT MATHIEU--DRIF
2024-07-18 8:16 ` [PATCH v1 10/17] intel_iommu: Process PASID-based " Zhenzhong Duan
2024-07-23 16:18 ` CLEMENT MATHIEU--DRIF
2024-07-18 8:16 ` [PATCH v1 11/17] intel_iommu: Extract device IOTLB invalidation logic Zhenzhong Duan
2024-07-24 8:35 ` CLEMENT MATHIEU--DRIF
2024-07-24 8:42 ` Duan, Zhenzhong
2024-07-18 8:16 ` [PATCH v1 12/17] intel_iommu: Add an internal API to find an address space with PASID Zhenzhong Duan
2024-07-18 8:16 ` [PATCH v1 13/17] intel_iommu: Add support for PASID-based device IOTLB invalidation Zhenzhong Duan
2024-07-18 8:16 ` [PATCH v1 14/17] intel_iommu: piotlb invalidation should notify unmap Zhenzhong Duan
2024-07-24 5:45 ` CLEMENT MATHIEU--DRIF
2024-07-24 6:04 ` CLEMENT MATHIEU--DRIF [this message]
2024-07-24 6:07 ` Duan, Zhenzhong
2024-07-24 6:11 ` CLEMENT MATHIEU--DRIF
2024-07-18 8:16 ` [PATCH v1 15/17] intel_iommu: Set default aw_bits to 48 in scalable modren mode Zhenzhong Duan
2024-07-18 9:14 ` CLEMENT MATHIEU--DRIF
2024-07-18 8:16 ` [PATCH v1 16/17] intel_iommu: Modify x-scalable-mode to be string option Zhenzhong Duan
2024-07-18 9:25 ` CLEMENT MATHIEU--DRIF
2024-07-19 2:53 ` Duan, Zhenzhong
2024-07-19 4:23 ` CLEMENT MATHIEU--DRIF
2024-07-18 8:16 ` [PATCH v1 17/17] tests/qtest: Add intel-iommu test Zhenzhong Duan
2024-07-24 5:58 ` CLEMENT MATHIEU--DRIF
2024-07-24 6:14 ` Duan, Zhenzhong
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=dd6cf2fc-a18d-4730-a351-be4057b6fb31@eviden.com \
--to=clement.mathieu--drif@eviden.com \
--cc=alex.williamson@redhat.com \
--cc=chao.p.peng@intel.com \
--cc=clg@redhat.com \
--cc=eduardo@habkost.net \
--cc=eric.auger@redhat.com \
--cc=jasowang@redhat.com \
--cc=jgg@nvidia.com \
--cc=joao.m.martins@oracle.com \
--cc=kevin.tian@intel.com \
--cc=marcel.apfelbaum@gmail.com \
--cc=mst@redhat.com \
--cc=nicolinc@nvidia.com \
--cc=pbonzini@redhat.com \
--cc=peterx@redhat.com \
--cc=qemu-devel@nongnu.org \
--cc=richard.henderson@linaro.org \
--cc=yi.l.liu@intel.com \
--cc=yi.y.sun@linux.intel.com \
--cc=zhenzhong.duan@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).