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From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: "Luc Michel" <luc.michel@amd.com>,
	qemu-devel@nongnu.org, qemu-arm@nongnu.org,
	"Manos Pitsidianakis" <manos.pitsidianakis@linaro.org>,
	"Alex Bennée" <alex.bennee@linaro.org>
Cc: Peter Maydell <peter.maydell@linaro.org>,
	Francisco Iglesias <francisco.iglesias@amd.com>,
	"Edgar E . Iglesias" <edgar.iglesias@amd.com>,
	Alistair Francis <alistair@alistair23.me>,
	Frederic Konrad <frederic.konrad@amd.com>,
	Sai Pavan Boddu <sai.pavan.boddu@amd.com>
Subject: Re: [PATCH v4 20/47] hw/arm/xlnx-versal: refactor CPU cluster creation
Date: Fri, 29 Aug 2025 00:16:37 +0200	[thread overview]
Message-ID: <dd70c16b-9b46-407a-af8b-b6dcb7608def@linaro.org> (raw)
In-Reply-To: <20250822151614.187856-21-luc.michel@amd.com>

On 22/8/25 17:15, Luc Michel wrote:
> Refactor the CPU cluster creation using the VersalMap structure. There
> is no functional change. The clusters properties are now described in
> the VersalMap structure. For now only the APU is converted. The RPU will
> be taken care of by next commits.
> 
> Signed-off-by: Luc Michel <luc.michel@amd.com>
> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com>
> ---
>   include/hw/arm/xlnx-versal.h |  12 +-
>   hw/arm/xlnx-versal-virt.c    |  80 +-------
>   hw/arm/xlnx-versal.c         | 352 ++++++++++++++++++++++++++---------
>   3 files changed, 275 insertions(+), 169 deletions(-)

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>

> diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c
> index b981d012558..27594f78c8f 100644
> --- a/hw/arm/xlnx-versal-virt.c
> +++ b/hw/arm/xlnx-versal-virt.c


> @@ -394,20 +328,18 @@ static void versal_virt_init(MachineState *machine)
>       fdt_create(s);
>       versal_set_fdt(&s->soc, s->fdt);
>       sysbus_realize(SYS_BUS_DEVICE(&s->soc), &error_fatal);
>       create_virtio_regions(s);
>   
> -    fdt_add_gic_nodes(s);
> -    fdt_add_timer_nodes(s);
> -    fdt_add_cpu_nodes(s, psci_conduit);
>       fdt_add_clk_node(s, "/old-clk125", 125000000, s->phandle.clk_125Mhz);
>       fdt_add_clk_node(s, "/old-clk25", 25000000, s->phandle.clk_25Mhz);
>   
> -    /* Make the APU cpu address space visible to virtio and other
> -     * modules unaware of multiple address-spaces.  */
> -    memory_region_add_subregion_overlap(get_system_memory(),
> -                                        0, &s->soc.fpd.apu.mr, 0);
> +    /*
> +     * Map the SoC address space onto system memory. This will allow virtio and
> +     * other modules unaware of multiple address-spaces to work.
> +     */
> +    memory_region_add_subregion(get_system_memory(), 0, &s->soc.mr_ps);

I was not aware of that shortcoming (Cc'ing Manos & Alex).



  reply	other threads:[~2025-08-30 17:59 UTC|newest]

Thread overview: 65+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-08-22 15:15 [PATCH v4 00/47] AMD Versal Gen 2 support Luc Michel
2025-08-22 15:15 ` [PATCH v4 01/47] hw/arm/xlnx-versal: split the xlnx-versal type Luc Michel
2025-08-28 22:07   ` Philippe Mathieu-Daudé
2025-08-22 15:15 ` [PATCH v4 02/47] hw/arm/xlnx-versal: prepare for FDT creation Luc Michel
2025-08-22 15:15 ` [PATCH v4 03/47] hw/arm/xlnx-versal: uart: refactor creation Luc Michel
2025-08-22 15:15 ` [PATCH v4 04/47] hw/arm/xlnx-versal: canfd: " Luc Michel
2025-08-22 15:15 ` [PATCH v4 05/47] hw/arm/xlnx-versal: sdhci: " Luc Michel
2025-08-28 22:19   ` Philippe Mathieu-Daudé
2025-09-02  7:14     ` Luc Michel
2025-08-22 15:15 ` [PATCH v4 06/47] hw/arm/xlnx-versal: gem: " Luc Michel
2025-08-22 15:15 ` [PATCH v4 07/47] hw/arm/xlnx-versal: adma: " Luc Michel
2025-08-22 15:15 ` [PATCH v4 08/47] hw/arm/xlnx-versal: xram: " Luc Michel
2025-08-22 15:15 ` [PATCH v4 09/47] hw/arm/xlnx-versal: usb: " Luc Michel
2025-08-22 15:15 ` [PATCH v4 10/47] hw/arm/xlnx-versal: efuse: " Luc Michel
2025-08-22 15:15 ` [PATCH v4 11/47] hw/arm/xlnx-versal: ospi: " Luc Michel
2025-08-22 15:15 ` [PATCH v4 12/47] hw/arm/xlnx-versal: VersalMap: add support for OR'ed IRQs Luc Michel
2025-08-28 22:10   ` Philippe Mathieu-Daudé
2025-08-22 15:15 ` [PATCH v4 13/47] hw/arm/xlnx-versal: PMC IOU SCLR: refactor creation Luc Michel
2025-08-22 15:15 ` [PATCH v4 14/47] hw/arm/xlnx-versal: bbram: " Luc Michel
2025-08-22 15:15 ` [PATCH v4 15/47] hw/arm/xlnx-versal: trng: " Luc Michel
2025-08-22 15:15 ` [PATCH v4 16/47] hw/arm/xlnx-versal: rtc: " Luc Michel
2025-08-22 15:15 ` [PATCH v4 17/47] hw/arm/xlnx-versal: cfu: " Luc Michel
2025-08-22 15:15 ` [PATCH v4 18/47] hw/arm/xlnx-versal: crl: " Luc Michel
2025-08-22 15:15 ` [PATCH v4 19/47] hw/arm/xlnx-versal-virt: virtio: " Luc Michel
2025-08-22 15:15 ` [PATCH v4 20/47] hw/arm/xlnx-versal: refactor CPU cluster creation Luc Michel
2025-08-28 22:16   ` Philippe Mathieu-Daudé [this message]
2025-08-22 15:15 ` [PATCH v4 21/47] hw/arm/xlnx-versal: add the mp_affinity property to the CPU mapping Luc Michel
2025-08-22 15:15 ` [PATCH v4 22/47] hw/arm/xlnx-versal: instantiate the GIC ITS in the APU Luc Michel
2025-08-22 15:15 ` [PATCH v4 23/47] hw/intc/arm_gicv3: Introduce a 'first-cpu-index' property Luc Michel
2025-08-26 19:33   ` Edgar E. Iglesias
2025-08-26 20:05     ` Peter Maydell
2025-09-11 10:45   ` Boddu, Sai Pavan
2025-09-11 14:08   ` Peter Maydell
2025-08-22 15:15 ` [PATCH v4 24/47] hw/arm/xlnx-versal: add support for multiple GICs Luc Michel
2025-08-22 15:15 ` [PATCH v4 25/47] hw/arm/xlnx-versal: add support for GICv2 Luc Michel
2025-08-22 15:15 ` [PATCH v4 26/47] hw/arm/xlnx-versal: rpu: refactor creation Luc Michel
2025-08-22 15:15 ` [PATCH v4 27/47] hw/arm/xlnx-versal: ocm: " Luc Michel
2025-08-22 15:15 ` [PATCH v4 28/47] hw/arm/xlnx-versal: ddr: " Luc Michel
2025-08-22 15:15 ` [PATCH v4 29/47] hw/arm/xlnx-versal: add the versal_get_num_cpu accessor Luc Michel
2025-08-22 15:15 ` [PATCH v4 30/47] hw/misc/xlnx-versal-crl: remove unnecessary include directives Luc Michel
2025-08-22 15:15 ` [PATCH v4 31/47] hw/misc/xlnx-versal-crl: split into base/concrete classes Luc Michel
2025-08-22 15:15 ` [PATCH v4 32/47] hw/misc/xlnx-versal-crl: refactor device reset logic Luc Michel
2025-08-22 15:15 ` [PATCH v4 33/47] hw/arm/xlnx-versal: reconnect the CRL to the other devices Luc Michel
2025-08-22 15:15 ` [PATCH v4 34/47] hw/arm/xlnx-versal: use hw/arm/bsa.h for timer IRQ indices Luc Michel
2025-08-22 15:16 ` [PATCH v4 35/47] hw/arm/xlnx-versal: tidy up Luc Michel
2025-08-22 15:16 ` [PATCH v4 36/47] hw/misc/xlnx-versal-crl: add the versal2 version Luc Michel
2025-08-28 22:22   ` Philippe Mathieu-Daudé
2025-09-02  7:21     ` Luc Michel
2025-08-22 15:16 ` [PATCH v4 37/47] hw/arm/xlnx-versal: add a per_cluster_gic switch to VersalCpuClusterMap Luc Michel
2025-08-28 22:06   ` Philippe Mathieu-Daudé
2025-08-22 15:16 ` [PATCH v4 38/47] hw/arm/xlnx-versal: add the target field in IRQ descriptor Luc Michel
2025-08-22 15:16 ` [PATCH v4 39/47] target/arm/tcg/cpu64: add the cortex-a78ae CPU Luc Michel
2025-09-11 14:31   ` Peter Maydell
2025-09-12  7:02     ` Luc Michel
2025-08-22 15:16 ` [PATCH v4 40/47] hw/arm/xlnx-versal: add versal2 SoC Luc Michel
2025-08-28 22:04   ` Philippe Mathieu-Daudé
2025-08-22 15:16 ` [PATCH v4 41/47] hw/arm/xlnx-versal-virt: rename the machine to amd-versal-virt Luc Michel
2025-08-22 15:16 ` [PATCH v4 42/47] hw/arm/xlnx-versal-virt: split into base/concrete classes Luc Michel
2025-08-22 15:16 ` [PATCH v4 43/47] hw/arm/xlnx-versal-virt: tidy up Luc Michel
2025-08-22 15:16 ` [PATCH v4 44/47] docs/system/arm/xlnx-versal-virt: update supported devices Luc Michel
2025-08-22 15:16 ` [PATCH v4 45/47] docs/system/arm/xlnx-versal-virt: add a note about dumpdtb Luc Michel
2025-08-22 15:16 ` [PATCH v4 46/47] hw/arm/xlnx-versal-virt: add the xlnx-versal2-virt machine Luc Michel
2025-08-22 15:16 ` [PATCH v4 47/47] tests/functional/test_aarch64_xlnx_versal: test the versal2 machine Luc Michel
2025-09-11  7:08 ` [PATCH v4 00/47] AMD Versal Gen 2 support Luc Michel
2025-09-11 14:05   ` Peter Maydell

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